MODULE – 2

8051 INSTRUCTIONS SET

Assembly programming and instruction of 8051
In the early days of the computer, programmers coded in machine language, consisting of 0s and 1s is
tedious, slow and prone to error. Assembly languages, which provides mnemonics for the machine code
instructions, plus other features, were developed. An Assembly language program consists of a series
of lines of Assembly language instructions. Assembly language is referred to as a low-level language. It
deals directly with the internal structure of the CPU.
Assembly language instruction includes a mnemonic (abbreviation easy to remember) the commands
to the CPU, telling it what those to do with those items optionally followed by one or two operands the
data items being manipulated. A given Assembly language program is a series of statements, or lines.
Assembly language instructions tell the CPU what to do. Directives (or pseudo-instructions) Give
directions to the assembler.

Assembling and running an 8051 program

The step of Assembly language program are outlines as follows:
1) First we use an editor to type a program, many excellent editors or word processors are available
that can be used to create and/or edit the program. Notice that the editor must be able to produce an
ASCII file. For many assemblers, the file names follow the usual DOS conventions, but the source file has
the extension “asm“ or “src”, depending on which assembly you are using
2) The “asm” source file containing the program code created in step 1 is fed to an 8051assembler.
The assembler converts the instructions into machine code. The assembler will produce an object file
and a list file. The extension for the object file is “obj” while the extension for the list file is “lst”.
3) Assembler require a third step called linking. The linker program takes one or more object code
files and produce an absolute object file with the extension “abs”. This abs file is used by 8051 trainers
that have a monitor program.
4) Next the “abs” file is fed into a program called “OH” (object to hex converter) which creates a file
with extension “hex” that is ready to burn into ROM. This program comes with all 8051 assemblers.
Recent Windows-based assemblers combine step 2 through 4 into one step.

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 Fig: Flowchart showing Assembly programming.

Instruction syntax
General syntax for 8051 assembly language is as follows
LABEL: OPCODE OPERAND ;COMMENT

LABEL: (THIS IS NOT NECESSARY UNLESS THAT SPECIFIC LINE HAS TO BE ADDRESSED). The label is a symbolic
address for the instruction. When the program is assembled, the label will be given specific address in
which that instruction is stored. Unless that specific line of instruction is needed by a branching
instruction in the program, it is not necessary to label that line.

OPCODE: Opcode is the symbolic representation of the operation. The assembler converts the opcode
to a unique binary code (machine language).

OPERAND: While opcode specifies what operation to perform, operand specifies where to perform that
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action. The operand field generally contains the source and destination of the data. In some cases, only
source or destination will be available instead of both. The operand will be either address of the data,
or data itself. Destination and source addresses are separated by ( ,) comma. Assembler will come to
know when one operand name ends and other begins.

COMMENT: Always comment will begin with ; or // symbol. To improve the program quality,
programmer may always use comments in the program.

An 8051-instruction syntax is shown below.

Mnemonic Destination operand Source operand

Addressing modes

Various methods of accessing the data are called addressing modes. 8051 addressing modes are
classified as follows.

1. Immediate addressing.

2. Register addressing.

3. Direct addressing.

4. Indirect addressing.

5. Indexed addressing.

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Immediate addressing
In this addressing mode the data is provided as a part of instruction itself. In other words, data
immediately follows the instruction. Notice that the immediate data must be preceded by the pound
sign, ‘ # `. this addressing mode can be used to load information into any of the registers, including the
DPTR register.
Eg: MOV A, #30H
ADD A, #83 # Symbol indicates the data is immediate.

MOV DPTR, #4521H

Register addressing
In this addressing mode the register will hold the data. One of the eight general registers (R0 to R7) can
be used and specified as the operand.

Eg: MOV A, R0
ADD A, R6
• R0 – R7 will be selected from the current selection of register bank. The default register bank will
be bank 0.
• It should be noted that the source and destination registers must match in size. In other words,
coding “ MOV DPTR, A” will give an error , since the source is an 8-bit register and destination is a
16-bit register.
• Notice that we can move data between the accumulator and Rn (for n = 0 to 7) but movement of
data between Rn registers is not allowed.
Eg: “MOV R4, R7” is invalid

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Direct addressing

There are two ways to access the internal memory. Using direct address and indirect address. Using
direct addressing mode, we can not only address the internal memory but SFRs also. Indirect
addressing, an 8-bit internal data memory address is specified as part of the instruction and hence, it
can specify the address only in the range of 00H to 7FH. In this addressing mode, data is obtained
directly from the memory.

Eg: MOV A, 60h

ADD A, 30h
MOV R4, 7Fh

Indirect addressing

The indirect addressing mode uses a register to hold the actual address that will be used in data
movement. Registers R0 and R1 and DPTR are the only registers that can be used as data pointers.
Indirect addressing cannot be used to refer to SFR registers. Both R0 and R1 can hold 8 bit address and
DPTR can hold 16 bit address.

Eg: MOV A,@R0

ADD A,@R1
MOVX A,@DPTR
Indexed addressing

In indexed addressing, either the program counter (PC), or the data pointer (DTPR)—is used to hold
the base address, and the A is used to hold the offset address. Adding the value of the base address to
the value of the offset address forms the effective address. Indexed addressing is used with JMP or MOVC
instructions. Look up tables are easily implemented with the help of index addressing.

Eg: MOVC A, @A+DPTR // copies the contents of memory location pointed by the sum of the
accumulator A and the DPTR into accumulator A.

MOVC A, @A+PC // copies the contents of memory location pointed by the sum of the accumulator
A and the program counter into accumulator A.

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Instruction set

8051 clock and instruction cycle

The heart of 8051 is the circuitry that generates the clock pulses by which all internal operations are
synchronized. Pins XTAL1 and XTAL2 are provided for connecting resonator to form an oscillator. The
crystal frequency is the basic internal frequency of the microcontroller. 8051 is designed to operate
between 1MHz to 16MHz and generally operates with a crystal frequency 11.04962 MHz.
The oscillator formed by the crystal, capacitor and an on-chip inverter generate a pulse train at the
frequency of the crystal. The clock frequency establishes the smallest interval to accomplish any simple
instruction. The time taken to complete any instruction is called as machine cycle or instruction cycle.
In 8051 one instruction cycle consists of 6 states or 12 clock cycles, instruction cycle is also referred as
Machine cycle.

Fig: Instruction cycle of 8051(Instruction cycle has six states (S 1 - S 6 ). Each state has two
pulses (P1 and P2))

Instruction Timings

• The 8051 internal operations and external read/write operations are controlled by the oscillator
clock.
• T-state, Machine cycle and Instruction cycle are terms used in instruction timings.
• T-state is defined as one subdivision of the operation performed in one clock period. The terms 'T-
state' and 'clock period' are often used synonymously.
• Machine cycle is defined as 12 oscillator periods. A machine cycle consists of six states and each
state lasts for two oscillator periods.
• An instruction takes one to four machine cycles to execute an instruction. Instruction cycle is
defined as the time required for completing the execution of an instruction.
• The 8051-instruction cycle consists of one to four machine cycles.
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Eg: If 8051 microcontroller is operated with 12 MHz oscillator, find the execution time for the following
four instructions.

1. ADD A, 45H
2. SUBB A, #55H
3. MOV DPTR, #2000H
4. MUL AB
To calculate the time any particular instruction will take to be executed, find the number of cycles, C.
The time to execute that instruction is then found by multiplying C by 12 and dividing the product by
the crystal frequency:
T inst = C X 12d

Crystal frequency

Since the oscillator frequency is 12 MHz, the clock period is, Clock period = 1/12 MHz = 0.08333 µS.
Time for 1 machine cycle = 0.08333 µS x 12 =1 µS.

Instruction No. of machine cycles Execution time

1. ADD A, 45H 1 1 µs

2. SUBB A, #55H 2 2 µs
3. MOV DPTR, #2000H 2 2 µs
4. MUL AB 4 4 µs

8051 Instructions
The instructions of 8051 can be broadly classified under the following headings.
1. Data transfer instructions

2. Arithmetic instructions

3. Logical instructions

4. Branch instructions

5. Subroutine instructions

6. Bit manipulation instructions

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Data transfer instructions.

In this group, the instructions perform data transfer operations of the following types.
a. Move the contents of a register Rn to A
i. MOV A,R2
ii. MOV A,R7
b. Move the contents of a register A to Rn
i. MOV R4,A
ii. MOV R1,A
c. Move an immediate 8 bit data to register A or to Rn or to a memory location(direct or
indirect)
i. MOV A, #45H iv. MOV @R0, #0E8H
ii. MOV R6, #51H v. MOV DPTR, #0F5A2H
iii. MOV 30H, #44H vi. MOV DPTR, #5467H

d. Move the contents of a memory location to A or A to a memory location using direct and
indirect addressing
i. MOV A, 65H
ii. MOV A, @R0
iii. MOV 45H, A
iv. MOV @R1, A

Fig: Addressing Using MOV, MOVX and MOVC

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 e. Move the contents of a memory location to Rn or Rn to a memory location
using direct addressing
i. MOV R3, 65H
ii. MOV 45H, R2
f. Move the contents of memory location to another memory location using
direct and indirect addressing
i. MOV 47H, 65H
ii. MOV 45H, @R0
g. Move the contents of an external memory to A or A to an external
memory
i. MOVX A,@R1
ii. MOVX @R0,A
h. Move the contents of program memory to A
i. MOVC A, @A+PC
ii. MOVC A, @A+DPTR
i. Push and Pop instructions
[SP]=07 //CONTENT OF SP IS 07 (DEFAULT VALUE)
MOV R6, #25H [R6]=25H //CONTENT OF R6 IS 25H
MOV R1, #12H [R1]=12H //CONTENT OF R1 IS 12H
MOV R4, #0F3H [R4]=F3H //CONTENT OF R4 IS F3H

PUSH 6 [SP]=08 [08]=[06]=25H //CONTENT OF 08 IS 25H

PUSH 1 [SP]=09 [09]=[01]=12H //CONTENT OF 09 IS 12H
PUSH 4 [SP]=0A [0A]=[04]=F3H //CONTENT OF 0A IS F3H

POP 6 [06]=[0A]=F3H [SP]=09 //CONTENT OF 06 IS F3H

POP 1 [01]=[09]=12H [SP]=08 //CONTENT OF 01 IS 12H
POP 4 [04]=[08]=25H [SP]=07 //CONTENT OF 04 IS 25H

j. Exchange instructions
The content of source ie., register, direct memory or indirect memory will be
exchanged with the contents of destination ie., accumulator.
i. XCH A,R3
ii. XCH A,@R1
iii. XCH A,54h

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 k. Exchange digit.
Exchange the lower order nibble of Accumulator (A0-A3) with lower order nibble of
the internal RAM location which is indirectly addressed by the register.
i. XCHD A,@R1
ii. XCHD A,@R0

Data transfer instructions

MOV <dest-byte>,<src-byte>
Function: Move byte variable
Description: The byte variable indicated by the second operand is copied into the location
specified by the first operand. The source byte is not affected. No other register or flag is
affected.
1. mov direct , A

2. mov A, @Ri

3. mov A, Rn

4. mov direct, direct

5. mov A, #data

EX: MOV 30h, A

MOV A, @R0 ; moves the content of memory pointed to by Ro into A

MOV A, R1; moves the content of Register R1 to Accumulator A

MOV 20h,30h; moves the content of memory location 30h to 20h

MOV A,#45h; moves 45h to Accumulator A

MOV <dest-bit>, <src-bit>

Function: Move bit data
Description: MOV <dest-bit>, <src-bit> copies the Boolean variable indicated by the second
operand into the location specified by the first operand. One of the operands must be the
carry flag; the other may be any directly addressable bit. No other register or flag is affected.
Example: MOV P1.3, C; moves the carry bit to 3rd bit of port1

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MOV DPTR, #data16
Function: Load Data Pointer with a 16-bit constant
Description: MOV DPTR,#data16 loads the Data Pointer with the 16-bit constant indicated.
The 16-bit constant is loaded into the second and third bytes of the instruction. The second
byte (DPH) is the high-order byte, while the third byte(DPL) holds the lower-order byte. No
flags are affected.
This is the only instruction which moves 16 bits of data at once.
Example: The instruction DPTR, # 4567H loads the value 4567H into the Data Pointer. DPH
holds 45H, and DPL holds 67H.

MOVC A, @A+ <base-reg>

Function: Move Code byte
Description: The MOVC instructions load the Accumulator with a code byte or constant
from program memory. The address of the byte fetched is the sum of the original unsigned
8-bit Accumulator contents and the contents of a 16-bit base register, which may be either
the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the
following instruction before being added with the Accumulator; otherwise, the base register
is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits
may propagate through higher-order bits. No flags are affected.
Example:
MOVC A,@A+PC
(PC) (PC) + 1
(A) ((A)+ (PC))

MOVX <dest-byte>,<src-byte>
Function: Move External

Description: The MOVX instructions transfer data between the Accumulator and a byte of
external data memory, which is why “X” is appended to MOV. There are two types of
instructions, differing in whether they provide an 8-bit or 16-bit indirect address to the
external data RAM.

This form of MOVX is faster and more efficient when accessing very large data arrays (up to
64K bytes), since no additional instructions are needed to set up the output ports.

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Example:

MOVX A,@DPTR
MOVX @DPTR, A
(A) ((DPTR))
PUSH direct
Function: Push onto stack
Description: The Stack Pointer is incremented by one. The contents of the indicated variable
is then copied into the internal RAM location addressed by the Stack Pointer. No flags are
affected.
Example: On entering an interrupt routine, the Stack Pointer contains 09H. The Data Pointer
holds the value 0123H. The following instruction sequence,

PUSH DPL
PUSH DPH
leaves the Stack Pointer set to 0BH and stores 23H and 01H in internal RAM locations 0AH and
0BH respectively.

POP direct
Function: Pop from stack.
Description: The contents of the internal RAM location addressed by the Stack Pointer is read,
and the Stack Pointer is decremented by one. The value read is then transferred to the directly
addressed byte indicated. No flags are affected.

Example: The Stack Pointer originally contains the value 32H, and internal RAM locations 30H
through 32H contain the values 20H, 23H, and 01H, respectively. The following instruction
sequence,

POP DPH
POP DPL leaves the Stack Pointer equal to the value 30H and sets the Data Pointer to 0123H.

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Arithmetic instructions.
The 8051 can perform addition, subtraction. Multiplication and division operations on 8-bit
numbers.

Addition
In this group, we have instructions to
i. Add the contents of A with immediate data with or without carry.
i. ADD A, #45H
ii. ADDC A, #OB4H
ii. Add the contents of A with register Rn with or without carry.
i. ADD A, R5
ii. ADDC A, R2
iii. Add the contents of A with contents of memory with or without carry using direct and
indirect addressing

i. ADD A, 51H
ii. ADDC A, 75H
iii. ADD A, @R1
iv. ADDC A, @R0
Note: CY AC and OV flags will be affected by this operation.
ADD A, <src-byte>

Function: Add

Description: ADD adds the byte variable indicated to the Accumulator, leaving the result in
the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out
from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag
indicates an overflow occurred. OV is set if a carry-out of bit 7 but not bit 6; otherwise, OV is
cleared. When adding signed integers, OV indicates a negative number produced as the sum of
two positive operands, or a positive sum from two negative operands. Four source operand
addressing modes are allowed: register, direct, register-indirect, or immediate.

Example: The Accumulator holds 0C3H (11000011B), and register 0 holds 0AAH
(10101010B). The following instruction,

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ADD A, R0

leaves 6DH (01101101B) in the Accumulator with the AC flag cleared and both the carry flag
and OV set to 1.

ADD A, direct
(A) (A) + (direct)
ADD A, @Ri
(A) (A) + data

ADDC A, <src-byte>

Function: Add with Carry

Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the
Accumulator contents, leaving the result in the Accumulator. The carry and auxiliary-carry
flags are set respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When
adding signed integers, OV indicates a negative number produced as the sum of two positive
operands or a positive sum from two negative operands. Four source operand addressing
modes are allowed: register, direct, register-indirect, or immediate.

Example: The Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B)
with the carry flag set. The following instruction,

ADDC A,R0

leaves 6EH (01101110B) in the Accumulator with AC cleared and both the Carry flag and OV
set to 1.

ADDC A, Rn
Operation: ADDC
(A) + (C) + (Rn)

ADDC A, direct
Operation: ADDC
(A) (A) + (C) + (direct)

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ADDC A, @Ri
Operation: ADDC
(A) (A) + (C) + ((Ri))

ADDC A, #data
Operation: ADDC
(A) (A) + (C) + #data

Subtraction
In this group, we have instructions to
i. Subtract the contents of A with immediate data with or without carry.
i. SUBB A, #45H
ii. SUBB A, #OB4H
ii. Subtract the contents of A with register Rn with or without carry.
i. SUBB A, R5
ii. SUBB A, R2
iii. Subtract the contents of A with contents of memory with or without carry using direct and
indirect addressing

i. SUBB A, 51H
ii. SUBB A, 75H
iii. SUBB A, @R1
iv. SUBB A, @R0
Note: CY AC and OV flags will be affected by this operation.

SUBB A, <src-byte>
Function: Subtract with borrow
Description: SUBB subtracts the indicated variable and the carry flag together from the
Accumulator, leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a
borrow is needed for bit 7 and clears C otherwise. (If C was set before executing a SUBB
instruction, this indicates that a borrow was needed for the previous step in a multiple-
precision subtraction, so the carry is subtracted from the Accumulator along with the source

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operand.) AC is set if a borrow is needed for bit 3 and cleared otherwise. The source operand
allows four addressing modes: register, direct, register-indirect, or immediate.

SUBB A, Rn
Operation: SUBB
(A) (A) - (C) - (Rn)

SUBB A, direct
Operation: SUBB
(A) (A) - (C) - (direct)

SUBB A, @Ri
Operation: SUBB
(A) (A) - (C) - ((Ri))

Multiplication

MUL AB. This instruction multiplies two 8 bit unsigned numbers which are stored in A and B
register. After multiplication the lower byte of the result will be stored in accumulator and
higher byte of result will be stored in B register.

Eg: MOV A, #45H ;[A]=45H

MOV B, #0F5H ; [B]=F5H
MUL AB ; [A] x [B] = 45 x F5 = 4209
;[A]=09H, [B]=42H

MUL AB

Function: Multiply

Description: MUL AB multiplies the unsigned 8-bit integers in the Accumulator and register
B. The low-order byte of the 16-bit product is left in the Accumulator, and the high-order byte
in B. If the product is greater than 255 (0FFH), the overflow flag is set; otherwise, it is cleared.
The carry flag is always cleared.

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Example: Originally the Accumulator holds the value 80 (50H). Register B holds the value 160
(0A0H). The instruction,

MUL AB: will give the product 12,800 (3200H), so B is changed to 32H (00110010B) and the
Accumulator is cleared. The overflow flag is set, carry is cleared.

Division

DIV AB. This instruction divides the 8 bit unsigned number which is stored in A by the 8 bit
unsigned number which is stored in B register. After division the result will be stored in
accumulator and remainder will be stored in B register.

Eg: MOV A,#0E8H ;[A]=0E8H

MOV B,#1BH ;[B]=1BH
DIV A ;[A] / [B] = E8 /1B = 08 H with remainder 10H
;[A] = 08H, [B]=10H

DIV AB

Function: Divide

Description: DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned
eight-bit integer in register B. The Accumulator receives the integer part of the quotient;
register B receives the integer remainder. The carry and OV flags are cleared.

Exception: if B had originally contained 00H, the values returned in the Accumulator and B-
register are undefined and the overflow flag are set. The carry flag is cleared in any case.

Example: The Accumulator contains 251 (0FBH or 11111011B) and B contains 18 (12H or
00010010B). The following instruction, DIV AB leaves 13 in the Accumulator (0DH or
00001101B) and the value 17 (11H or 00010001B) in B, since 251 = (13 x 18) + 17. Carry and
OV are both cleared.

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DA A (Decimal Adjust After Addition)

When two BCD numbers are added, the answer is a non-BCD number. To get the result in BCD,
we use DA A instruction after the addition. DA A works as follows.

• If lower nibble is greater than 9 or auxiliary carry is 1, 6 is added to lower nibble.

• If upper nibble is greater than 9 or carry is 1, 6 is added to upper nibble.

Eg 1: MOV A,#23H
MOV R1,#55H
ADD A,R1 // [A]=78
DA A // [A]=78 no changes in the accumulator after DA A

Eg 2:MOV A ,#53H
MOV R1,#58H
ADD A,R1 // [A]=ABh
DA A // [A]=11, C=1 . ANSWER IS 111. Accumulator data is changed after DA A

DA A

Function: Decimal-adjust Accumulator for Addition

Description: DA A adjusts the eight-bit value in the Accumulator resulting from the earlier
addition of two variables (each in packed-BCD format), producing two four-bit digits. Any ADD
or ADDC instruction may have been used to perform the addition. If Accumulator bits 3 through
0 are greater than nine or if the AC flag is one, six is added to the Accumulator producing the
proper BCD digit in the low-order nibble. This internal addition sets the carry flag if a carry-
out of the low-order four-bit field propagates through all high-order bits, but it does not clear
the carry flag otherwise.

If the carry flag is now set, or if the four high-order bits now exceed nine, these high-order bits
are added with six, producing the proper BCD digit in the high-order nibble. Again, this sets the
carry flag if there is a carry-out of the high-order bits, but does not clear the carry.

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Increment
increments the operand by one.
INC A INC Rn INC DIRECT INC @Ri INC DPTR

INC increments the value of source by 1. If the initial value of register is FFh, incrementing the
value will cause it to reset to 0. The Carry Flag is not set when the value "rolls over" from 255
to 0.

In the case of "INC DPTR", the value two-byte unsigned integer value of DPTR is incremented.
If the initial value of DPTR is FFFFh, incrementing the value will cause it to reset to 0.

INC <byte>

Function: Increment

Description: INC increments the indicated variable by 1. An original value of 0FFH overflows
to 00H. No flags are affected.

Example: Register 0 contains 7EH (011111110B). Internal RAM locations 7EH and 7FH
contain 0FFH and 40H, respectively. The following instruction sequence,

INC R0

INC @R0 leaves register 0 set to 7FH and internal RAM locations 7EH and 7FH holding 00H and
41H, respectively.

INC A

Operation: INC (A) (A) + 1

INC DPTR

Function: Increment Data Pointer

Description: INC DPTR increments the 16-bit data pointer by 1. A 16-bit increment (modulo

216) is performed, and an overflow of the low-order byte of the data pointer (DPL) from 0FFH
to 00H increments the high-order byte (DPH). No flags are affected. This is the only 16-bit
register which can be incremented.

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Example: Registers DPH and DPL contain 12H and 0FEH, respectively. The following
instruction sequence,

INC DPTR
INC DPTR changes DPH and DPL to 13H and 01H.

Decrement

decrements the operand by one.

DEC A DEC Rn DEC DIRECT DEC @Ri

DEC decrements the value of source by 1. If the initial value of is 0, decrementing the value will
cause it to reset to FFh. The Carry Flag is not set when the value "rolls over" from 0 to FFh.

DEC <byte>

Function: Decrement

Description: DEC byte decrements the variable indicated by 1. An original value of 00H
underflows to 0FFH. No flags are affected.

Example: Register 0 contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain
00H and 40H, respectively. The following instruction sequence,

DEC R0

DEC @R0

leaves register 0 set to 7EH and internal RAM locations 7EH and 7FH set to 0FFH and 3FH.

DEC A

DEC Rn

DEC direct

DEC @Ri

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SWAP A

Function: Swap nibbles within the Accumulator

Description: SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the
Accumulator (bits 3 through 0 and bits 7 through 4). The operation can also be thought of as a
4- bit rotate instruction. No flags are affected.

Example: The Accumulator holds the value 0C5H (11000101B). The instruction, SWAP A
leaves the Accumulator holding the value 5CH (01011100B)

Operation: SWAP (A3-0) D (A7-4)

XCH A, <byte>

Function: Exchange Accumulator with byte variable

Description: XCH loads the Accumulator with the contents of the indicated variable, at the
same time writing the original Accumulator contents to the indicated variable. The
source/destination operand can use register, direct, or register-indirect addressing.

Example: R0 contains the address 20H. The Accumulator holds the value 3FH (0011111lB).
Internal RAM location 20H holds the value 75H (01110101B). The following instruction, XCH
A,@R0 leaves RAM location 20H holding the values 3FH (00111111B) and 75H (01110101B)
in the accumulator.

XCHD A, @Ri

Function: Exchange Digit

Description: XCHD exchanges the low-order nibble of the Accumulator (bits 3 through 0),
generally representing a hexadecimal or BCD digit, with that of the internal RAM location
indirectly addressed by the specified register. The high-order nibbles (bits 7-4) of each register
are not affected. No flags are affected.

Example: R0 contains the address 20H. The Accumulator holds the value 36H (00110110B).
Internal RAM location 20H holds the value 75H (01110101B). The following instruction, XCHD

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A,@R0 leaves RAM location 20H holding the value 76H (01110110B) and 35H (00110101B) in
the Accumulator.

CPL A

Function: Complement Accumulator

Description: CPLA logically complements each bit of the Accumulator (one‟s complement).
Bits which previously contained a 1 are changed to a 0 and vice-versa. No flags are affected.

Example: The Accumulator contains 5CH (01011100B).

The following instruction, CPL A leaves the Accumulator set to 0A3H (10100011B).

CPL bit

Function: Complement bit

Description: CPL bit complements the bit variable specified. A bit that had been a 1 is changed
to 0 and vice-versa. No other flags are affected. CLR can operate on the carry or any directly
addressable bit.

Example: Port 1 has previously been written with 5BH (01011101B). The following
instruction sequence, CPL P1.1CPL

P1.2 leaves the port set to 5BH (01011011B).

NOP

Function: No Operation

Description: Execution continues at the following instruction. Other than the PC, no registers
or flags are affected.

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Logical Instructions
Logical AND
ANL destination, source: ANL does a bitwise "AND" operation between source and
destination, leaving the resulting value in destination. The value in source is not affected. "AND"
instruction logically AND the bits of source and destination.
ANL A, #DATA
ANL A, Rn
ANL A, DIRECT
ANL A, @Ri
ANL DIRECT, A
ANL DIRECT, #DATA
ANL <dest-byte>, <src-byte>

Function: Logical-AND for byte variables

Description: ANL performs the bitwise logical-AND operation between the variables indicated
and stores the results in the destination variable. No flags are affected. The two operands allow
six addressing mode combinations. When the destination is the Accumulator, the source can
use register, direct, register-indirect, or immediate addressing; when the destination is a direct
address, the source can be the Accumulator or immediate data.

Example: If the Accumulator holds 0C3H (1100001lB), and register 0 holds 55H (01010101B),
then the following instruction, ANL A, R0 leaves 41H (01000001B) in the Accumulator.

When the destination is a directly addressed byte, this instruction clears combinations of bits
in any RAM location or hardware register. The mask byte determining the pattern of bits to be
cleared would either be a constant contained in the instruction or a value computed in the
Accumulator at run-time. The following instruction, ANL P1,#01110011B clears bits 7, 3, and
2 of output port 1.

Logical OR
ORL destination, source: ORL does a bitwise "OR" operation between source and destination,
leaving the resulting value in destination. The value in source is not affected. " OR " instruction
logically OR the bits of source and destination.
ORL A,#DATA
ORL A, Rn
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ORL A,DIRECT
ORL A,@Ri
ORL DIRECT,A
ORL DIRECT, #DATA

Logical Ex-OR
XRL destination, source: XRL does a bitwise "EX-OR" operation between source and
destination, leaving the resulting value in destination. The value in source is not affected. " XRL
" instruction logically EX-OR the bits of source and destination.
XRL A,#DATA
XRL A,Rn
XRL A,DIRECT
XRL A,@Ri
XRL DIRECT,A
XRL DIRECT, #DATA
Logical NOT
CPL complements operand, leaving the result in operand. If operand is a single bit, then the
state of the bit will be reversed. If operand is the Accumulator, then all the bits in the
Accumulator will be reversed.
CPL A
CPL C
CPL bit address

Rotate Instructions
RR A

This instruction is rotate right the accumulator. Its operation is illustrated below. Each bit is
shifted one location to the right, with bit 0 going to bit 7.

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RL A
Rotate left the accumulator. Each bit is shifted one location to the left, with bit 7 going to bit 0

RRC A

Rotate right through the carry. Each bit is shifted one location to the right, with bit 0 going into
the carry bit in the PSW, while the carry was at goes into bit 7

RLC A

Rotate left through the carry. Each bit is shifted one location to the left, with bit 7 going into the
carry bit in the PSW, while the carry goes into bit 0.

Rotate Instructions
RL A

Function: Rotate Accumulator Left

Description: The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated
into the bit 0 position. No flags are affected.

Example: The Accumulator holds the value 0C5H (11000101B). The following instruction,

RL A leaves the Accumulator holding the value 8BH (10001011B) with the carry unaffected.

RLC A

Function: Rotate Accumulator Left through the Carry flag

Description: The eight bits in the Accumulator and the carry flag are together rotated one bit
to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit
0 position. No other flags are affected.
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Example: The Accumulator holds the value 0C5H(11000101B), and the carry is zero. The
following instruction, RLC A leaves the Accumulator holding the value 8BH (10001010B) with
the carry set.

RRC A

Function: Rotate Accumulator Right through Carry flag

Description: The eight bits in the Accumulator and the carry flag are together rotated one bit
to the right. Bit 0 moves into the carry flag; the original value of the carry flag moves into the
bit 7 position. No other flags are affected.

Example: The Accumulator holds the value 0C5H (11000101B), the carry is zero. The
following instruction, RRC A leaves the Accumulator holding the value 62 (01100010B) with
the carry set.
Branch (JUMP) Instructions

Jump and Call Program Range

There are 3 types of jump instructions. They are: -
1. Relative Jump
2. Short Absolute Jump
3. Long Absolute Jump

Relative Jump
Jump that replaces the PC (program counter) content with a new address that is greater than
(the address following the jump instruction by 127 or less) or less than (the address following
the jump by 128 or less) is called a relative jump. Schematically, the relative jump can be shown
as follows: -

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The advantages of the relative jump are as follows: -

1. Only 1 byte of jump address needs to be specified in the 2's complement form, ie. For
jumping ahead, the range is 0 to 127 and for jumping back, the range is -1 to -128.

2. Specifying only one byte reduces the size of the instruction and speeds up program
execution.

3. The program with relative jumps can be relocated without reassembling to generate
absolute jump addresses.

Disadvantages of the absolute jump: -

1. Short jump range (-128 to 127 from the instruction following the jump instruction)

Instructions that use Relative Jump

SJMP <relative address>; this is unconditional jump

The remaining relative jumps are conditional jumps
JC <relative address>
JNC <relative address>
JB bit, <relative address>
JNB bit, <relative address>
JBC bit, <relative address>
CJNE <destination byte>, <source byte>, <relative address>
DJNZ <byte>, <relative address>
JZ <relative address>
JNZ <relative address>

Short Absolute Jump

In this case only 11bits of the absolute jump address are needed. The absolute jump address is
calculated in the following manner.

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 In 8051, 64 Kbyte of program memory space is divided into 32 pages of 2 Kbyte each. The
hexadecimal addresses of the pages are given as follows: -

Page (Hex) Address (Hex)

00 0000 - 07FF
01 0800 - 0FFF
02 1000 - 17FF
03 1800 - 1FFF
.
.
1E F000 - F7FF
1F F800 - FFFF

It can be seen that the upper 5bits of the program counter (PC) hold the page number and the
lower 11bits of the PC hold the address within that page. Thus, an absolute address is formed
by taking page numbers of the instruction (from the program counter) following the jump and
attaching the specified 11bits to it to form the 16-bit address.

Advantage: The instruction length becomes 2 bytes. Example of short absolute jump: -

ACALL <address 11>

AJMP <address 11>

Long Absolute Jump/Call

Applications that need to access the entire program memory from 0000H to FFFFH use long
absolute jump. Since the absolute address has to be specified in the op-code, the instruction
length is 3 bytes (except for JMP @ A+DPTR). This jump is not re-locatable.

Example: -

LCALL <address 16>

LJMP <address 16> JMP @A+DPTR

Another classification of jump instruction is

1. Unconditional Jump
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2. Conditional Jump

1. The unconditional jump is a jump in which control is transferred unconditionally to the

target location.

a. LJMP (long jump): This is a 3-byte instruction. First byte is the op-code and second and
third bytes represent the 16-bit target address which is any memory location from 0000 to
FFFFH.

Function: Long Jump

Syntax: LJMP code address.
eg: LJMP 3000H

b. AJMP: this causes unconditional branch to the indicated address, by loading the 11-bit
address to 0 -10 bits of the program counter. The destination must be therefore within the
same 2K blocks.

Description: AJMP unconditionally jumps to the indicated code address. The new value for the
Program Counter is calculated by replacing the least-significant-byte of the Program Counter
with the second byte of the AJMP instruction, and replacing bits 0-2 of the most-significant-
byte of the Program Counter with 3 bits that indicate the page of the byte following the AJMP
instruction. Bits 3-7 of the most-significant-byte of the Program Counter remain unchanged.
Since only 11 bits of the Program Counter are affected by AJMP, jumps may only be made to
code located within the same 2k block as the first byte that follows AJMP.

c. SJMP (short jump): This is a 2-byte instruction. First byte is the op-code and second byte is
the relative target address, 00 to FFH (forward +127 and backward -128 bytes from the current
PC value). To calculate the target address of a short jump, the second byte is added to the PC
value which is address of the instruction immediately below the jump.

Function: Short Jump

Syntax: SJMP reladdr

2. Conditional Jump instructions.

JBC Jump if bit ＝ 1 and clear bit

JNB Jump if bit ＝ 0

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JB Jump if bit ＝ 1

JNC Jump if CY ＝ 0

JC Jump if CY ＝ 1

CJNE reg, #data Jump if byte ≠ #data

CJNE A, byte Jump if A ≠ byte

DJNZ Decrement and Jump if A ≠ 0

JNZ Jump if A ≠ 0

JZ Jump if A ＝ 0

All conditional jumps are short jumps.

These instructions jumps to the specified location after checking a condition.

Operation: JNC
Function: Jump if Carry Not Set
Syntax: JNC reladdr
Description: JNC branches to the address indicated by reladdr if the carry bit is not set. If the
carry bit is set program execution continues with the instruction following the JNB instruction.

Operation: JC
Function: Jump if Carry Set
Syntax: JC reladdr
Description: JC will branch to the address indicated by reladdr if the Carry Bit is set. If the
Carry Bit is not set program execution continues with the instruction following the JC
instruction.

Operation: JNZ
Function: Jump if Accumulator Not Zero
Syntax: JNZ reladdr

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Description: JNZ will branch to the address indicated by reladdr if the Accumulator contains
any value except 0. If the value of the Accumulator is zero program execution continues with
the instruction following the JNZ instruction.

Operation: JZ
Function: Jump if Accumulator Zero
Syntax: JZ reladdr
Description: JZ branches to the address indicated by reladdr if the Accumulator contains the
value 0. If the value of the Accumulator is non-zero program execution continues with the
instruction following the JNZ instruction.

Operation: DJNZ
Function: Decrement and Jump if Not Zero
Syntax: DJNZ register, reladdr
Description: DJNZ decrements the value of register by 1. If the initial value of register is 0,
decrementing the value will cause it to reset to 255 (0xFF Hex). If the new value of register is
not 0 the program will branch to the address indicated by relative addr. If the new value of
register is 0 program flow continues with the instruction following the DJNZ instruction.

Operation: CJNE
Function: Compare and Jump If Not Equal
Syntax: CJNE operand1,operand2,reladdr
Description: CJNE compares the value of operand1 and operand2 and branches to the
indicated relative address if operand1 and operand2 are not equal. If the two operands are
equal program flow continues with the instruction following the CJNE instruction. The Carry
bit (C) is set if operand1 is less than operand2, otherwise it is cleared.

Bit level jump instructions:

Bit level JUMP instructions will check the conditions of the bit and if condition is true, it jumps
to the address specified in the instruction. All the bit jumps are relative jumps.

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JB bit, rel ; jump if the direct bit is set to the relative address specified.

JNB bit, rel ; jump if the direct bit is clear to the relative address specified.

JBC bit, rel ; jump if the direct bit is set to the relative address specified and then clear the
bit.

Operation: JNB
Function: Jump if Bit Not Set
Syntax: JNB bit addr, reladdr
Description: JNB will branch to the address indicated by reladdress if the indicated bit is not
set. If the bit is set program execution continues with the instruction following the JNB
instruction.

Operation: JB
Function: Jump if Bit Set
Syntax: JB bit addr, reladdr
Description: JB branches to the address indicated by reladdr if the bit indicated by bit addr is
set. If the bit is not set program execution continues with the instruction following the JB
instruction.

Bit manipulation instructions

8051 has 128 bit addressable memory. Bit addressable sfrs and bit addressable port pins. It is
possible to perform following bit wise operations for these bit addressable locations.

1. Logical AND

A. ANL C, bit(bit address) ; ‘logically AND’ carry and content of bit address, store result in

carry

B. ANL C, /bit ; ‘logically AND’ carry and complement of content of bit address,

store result in carry

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2. Logical OR
A. ORL C, bit(bit address) ; ‘logically OR’ carry and content of bit address, store result in
carry

B. ORL C, /bit; ; ‘logically OR’ carry and complement of content of bit address, store result in
carry

3. CLR bit
A. CLR bit ; content of bit address specified will be cleared.

B. CLR c ; content of carry will be cleared.

4. CPL bit
A. CPL bit ; content of bit address specified will be complemented.

B. CPL c ; content of carry will be complemented

Single Bit Instructions

Instruction Function
SETB bit Set the bit (bit = 1)
CLR bit Clear the bit (bit = 0)
CPL bit Complement the bit (bit = NOT bit)
JB bit, target Jump to target if bit = 1 (jump if bit)
JNB bit, target Jump to target if bit = 0 (Jump if no bit)
JBC bit, target Jump to target if bit = 1, clear bit (jump if bit, then clear)

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