DEPARTMENT OF COMPUTER ENGINEERING

MODULE 01: THE INTEL MICROPROCESSORS 8086/8088 ARCHITECTURE

SR.NO TOPIC NAME PAGE NO UNIVERSITY QUESTION

1.1 8086/8088 CPU Architecture 1-5 DEC18
1.2 Programmer‘s Model /Flag Register 5-7 MAY18, DEC18, MAY16
1.3 Functional Pin Diagram 8-9
1.4 Memory Segmentation 9-11 MAY18, DEC17,MAY16
1.5 Study of 8284 Clock Generator 12-12 DEC17,
1.6 Study of 8288 Bus Controller 12-13 DEC16
1.7 Functioning of 8086 in Minimum mode 14-15 MAY18, DEC17,DEC16
and Maximum mode
1.8 Timing diagrams for Read and Write 15-17 MAY18, MAY16, DEC17
operations in minimum and maximum mode

1.1 8086/8088 CPU Architecture:

Microprocessor: A microprocessor is a computer processor which incorporates the functions

of a computer's central processing unit (CPU) on a single integrated circuit (IC), or at most a few
integrated circuits.

MICROPROCESSOR 8086 ARCHITECTURE:

1. 8086 is a 40 pin IC.

2. It is a 16-bit processor.
3. Its operating voltage is 5 volts.
4. Its operating frequency is 5 MHz.
5. Total memory addressing capacity is 1MB (external).
6. It has 16-bit data bus and 20-bit address bus.
7. It has fourteen 16-bit registers.
8. Higher throughput (speed).
9. It has around 20000 transistors in its circuitry and it is made in HMOS technology.

1 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING

Fig: Block Diagram of IC-8086

Explanation:

8086 Microprocessor is divided into two functional units, i.e.

EU: Execution Unit

BIU: Bus Interface Unit

EU (Execution Unit)

Execution unit gives instructions to BIU stating from where to fetch the data and then decode
and execute those instructions. Its function is to control operations on data using the instruction
decoder & ALU. EU has no direct connection with system buses as shown in the above figure, it
performs operations over data through BIU.

Let us now discuss the functional parts of 8086 microprocessors.

ALU
It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.
Flag Register

2 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result
stored in the accumulator. It has 9 flags and they are divided into 2 groups − Conditional Flags
and Control Flags.

Conditional Flags
It represents the result of the last arithmetic or logical instruction executed. Following is the list
of conditional flags −

 Carry flag − this flag indicates an overflow condition for arithmetic operations.
 Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow
from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e.
carry given by D3 bit to D4 is AF flag. The processor uses this flag to perform binary to
BCD conversion.
 Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower
order 8-bits of the result contains even number of 1’s, then the Parity Flag is set. For odd
number of 1’s, the Parity Flag is reset.
 Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero
else it is set to 0.
 Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is
negative, then the sign flag is set to 1 else set to 0.
 Overflow flag − this flag represents the result when the system capacity is exceeded.

Control Flags

Control flags controls the operations of the execution unit. Following is the list of control flags −

 Trap flag − It is used for single step control and allows the user to execute one
instruction at a time for debugging. If it is set, then the program can be run in a single
step mode.
 Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the
interruption of a program. It is set to 1 for interrupt enabled condition and set to 0 for
interrupt disabled condition.
 Direction flag − It is used in string operation. As the name suggests when it is set then
string bytes are accessed from the higher memory address to the lower memory address
and vice-a-versa.

General purpose register

There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These
registers can be used individually to store 8-bit data and can be used in pairs to store 16bit data.
The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred
to the AX, BX, CX, and DX respectively.

3 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING
 AX register − It is also known as accumulator register. It is used to store operands for
arithmetic operations.
 BX register − It is used as a base register. It is used to store the starting base address of
the memory area within the data segment.
 CX register − It is referred to as counter. It is used in loop instruction to store the loop
counter.
 DX register − this register is used to hold I/O port address for I/O instruction.

Stack pointer register

It is a 16-bit register, which holds the address from the start of the segment to the memory
location, where a word was most recently stored on the stack.

BIU (Bus Interface Unit)

BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses,
fetching instructions from the memory, reading data from the ports and the memory as well as
writing data to the ports and the memory. EU has no direction connection with System Buses so
this is possible with the BIU. EU and BIU are connected with the Internal Bus.

It has the following functional parts −

 Instruction queue − BIU contains the instruction queue. BIU gets upto 6 bytes of next
instructions and stores them in the instruction queue. When EU executes instructions and
is ready for its next instruction, then it simply reads the instruction from this instruction
queue resulting in increased execution speed.
 Fetching the next instruction while the current instruction executes is called pipelining.
 Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the
addresses of instructions and data in memory, which are used by the processor to access
memory locations. It also contains 1 pointer register IP, which holds the address of the
next instruction to executed by the EU.
o CS − It stands for Code Segment. It is used for addressing a memory location in
the code segment of the memory, where the executable program is stored.
o DS − It stands for Data Segment. It consists of data used by the program and is
accessed in the data segment by an offset address or the content of other register
that holds the offset address.
o SS − It stands for Stack Segment. It handles memory to store data and addresses
during execution.
o ES − It stands for Extra Segment. ES is additional data segment, which is used by
the string to hold the extra destination data.
 Instruction pointer − It is a 16-bit register used to hold the address of the next
instruction to be executed.

4 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING

1.2 PROGRAMMER‘S MODEL:

The programming model of the 8086 is considered to be program visible because its registers
are used during application programming and are specified by the instructions.

5 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING

1. It consists of 9 active flags out of 16. The remaining 7 flags marked ‘U’ are undefined
flags.
2. These 9 flags are of two types:
 6 Status flags
 3 Control flags
6 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING
Status flags:

1. Carry flag (CY)-

 It is set whenever there is a carry or borrow out of the MSB (most significant bit) of a
result. D7 bit for an 8 bit operation and D15 bit for a 16 bit operation.

1. Parity flag (PF)-

2. It is set if the result has even parity. If parity is odd, PF is reset.
3. This flag is normally used for data transmission errors.
4. Auxiliary carry flag (AC)-
5. It is set if a carry is generated out of the lower nibble.
6. It is used only in 8 bit operations like DAA and DAS.
7. Zero flag (ZF)-
8. It is set if the result is zero.
9. Sign flag (SF)-
10. It is set if the MSB of the result is 1. For signed operations such a number is treated as
negative.
11. Overflow flag (OF)-
12. It will be set if the result of a signed operation is too large to fit in the number of bits
available to represent it.
13. It can be checked using the instruction INTO (Interrupt on Overflow).

Control flags:

1. Trap flag (TF)-

2. It is used to set the trace mode i.e. start single stepping mode.
3. Here the microprocessor is interrupted after every instruction so that the program can be
debugged.
4. Interrupt enable flag (IF)-
5. It is used to mask (disable) or unmask (enable) the INTR interrupt.
6. If user sets IF flag, the CPU will recognize external interrupt requests. Clearing IF
disables these interrupts.
7. Direction flag (DF)-
8. If this flag is set, SI and DI are in auto-decrementing mode in string operations.

7 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING
1.3 8086 PIN DESCRIPTION:

8086 can operate in two modes these are the minimum mode and maximum mode .For minimum mode, a
unique processor system with a single 8086 and for Maximum mode a multi-processor system with more
than one 8086.

MN/MX(bar) : is an input pin used to select one of this mode .when MN/MX is high the 8086
operates in minimum mode. When MN/MX is low 8086 is configured to support multiprocessor
system.
The AD0-AD15 lines are a 16bit multiplexed addressed or data bus. During the 1 st clock cycle AD0-
AD15 are the low order 16Bit adders. The 8086 has a total of 20 address lines, the upper 4 lines are
multiplexed with the state signal that is A16/S3, A17/S4, A18/S5, A19 /S6.During the first clock period
of a best cycle the entire 20bit address is available on these lines.

During all other clock cycles for memory and I/O

operations AD15-AD0 contain the 16 bit data and S3, S4, S5, S6 become the status line .S3 and S4 are
decoded as follows

A17/S4 A16/S3 Function:

0 0 Extra Segment
0 1 Stack Segment
1 0 code or No segment
1 1 Data Segment

8 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING
There for the 1 clock cycle of an instruction execution the A17/S4 and A16/S3 pins Specify
st

which Segment register generate the segment portions of the 8086 address

BHE/S7 is used as best high enable during the 1st click cycle of an instruction execution .the
BHE can be used in conjunction with AD0 to select the memory

RD is low when the data is read from memory or I/O location.

TEST is an input pin and is only used by the wait instruction .the 8086 enter a wait state after
execution of the wait instruction until a low is Sean on the test pin.

INTR is a mask able interrupt input.

NIM is the non-mask able interrupt input.

RESET is the system set reset input signal it terminates all the activities it clear
PSW,IP,DS,SS,ES and the instruction Queue.

DT/R (Data Transmit or receive): is an o/p signal required in system that uses the data bus
transceiver

ALE is an address latch enable: Is an o/p signal provided by the 8086 and can be used to de-
multiplex AD0 to AD15 in to A10 toA15 and D0 to D15.

M/IO is an 8086 output signal to distinguish a memory access and i/o access.
WR is used by the 8086 for performing write memory or write i/o operation.
INTA (interrupt acknowledgement signal)
INTA is the interrupt acknowledgment signal

HOLD and HOLDA a high on the HOLD pin indicates that another master is required to take
over the S/M bus

CLK clock provides the basic timing signals for the 8086 and bus controls.

1.4 MEMORY SEGMENTATION:

The process of dividing a memory is called as memory segmentation i.e. divided into 4 part
Code segment
Data segment
Extra segment
Stack segment

1. Code Segment (CS): The CS register is used for addressing a memory location in the
Code Segment of the memory, where the executable program is stored.
9 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING
2. Data Segment (DS): The DS contains most data used by program. Data are accessed in
the Data Segment by an offset address or the content of other register that holds the offset
address.
3. Stack Segment (SS): SS defined the area of memory used for the stack.
4. Extra Segment (ES): ES is additional data segment that is used by some of the string to
hold the destination data.

10 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING

Advantages of memory segmentation:

1. Segmentation provides a powerful memory management mechanism.

2. It allows programmers to partition their programs into modules that operate
independently of one another.
3. Segments allow two processes to easily share data.
4. It allows to extend the address ability of a processor i.e. segmentation allows the use of
16 bit registers to give an addressing capability of 1 MB. Without segmentation, it would
require 20 bit registers.
5. Segmentation makes it possible to separate the memory areas for stack, code and data.
6. It is possible to increase the memory size of code data or stack segments beyond 64 KB
by allotting more than one segment for each area

11 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING
1.5 STUDY OF 8284 CLOCK GENERATOR

The Intel 8284 is a clock oscillator chip developed primarily for supplying clock signals for the
Intel-8086/8087/8088/8089 series of processors.

Crystal oscillator is used to maintain the frequency level

The 8284A clock generator consists of a synchronous divide-by-three counter. It has several output
including CLK, PCLK, OSC, Reset, Ready. Out of this 3 pins are connected to the 8088 microprocessor
which is CLK, Reset, and Ready.

CLK- This is the clock output used by the processor and other devices that directly using the processor
local bus. CLK output is 33% duty cycle clock driver.
RESET- This signal is used to reset the 8086 microprocessor
READY-This signal used to indicate the readiness of the microprocessor. It will be cleared after the
guaranteed hold time to the processor has been met.

1.6 INTEL 8288 IS A BUS CONTROLLER:

The Intel 8288 is a bus controller designed for Intel 8086/8087/8088/8089. The chip is supplied in 20-pin
DIP package. The 8086 (and 8088) operate in maximum mode, so they are configured primarily for
multiprocessor operation or for working with coprocessors.

An 8288 bus controller is used to generate the relevant signals for interfacing memory and I/O devices in
the maximum mode

The 8288 input and output signals:

12 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING
 SO, SL and S2: The inputs (8086 Status outputs) are decoded to generate command
signals.
 AEN: A low Address Enable signal activates the memory control signals.
 CEN: The Control Enable signal enables the 8288 command outputs.
 IOB: High on the I/O Bus input operates the 8288 in the I/O bus mode in systems where
there are separate system bus and I/O bus.
 CLK: The Clock input
 DEN: The Data bus Enable signal controls the data bus buffers in the system. This signal
is active-high in contrast to the DEN signal in the minimum mode
 ALE: The Address Latch Enable signal is used to de-multiplex address and data lines
signals.
 DT/R: The Data Transmit/Receive signal controls bidirectional data bus buffer.
 MRDC, MWTC, IORC and lOWC: The 8288 generates the normal Memory Read,
Memory Write, I/O Read, I/O Write Control signals.
 AMWC and AIOWC: These are Advanced Memory and Advanced I/O Write Control
signals.
 INTA: The Interrupt Acknowledge output.
 MCE/PDEN: The Master Cascade Enable/Peripheral Data Enable output serves dual
function. If IOB input is low it selects cascading of interrupt controllers, and if high
enables the I/0 bus transceivers.

Fig: IC-8088 bus controller

13 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING

1.7 FUNCTIONING OF 8086 IN MINIMUM MODE AND MAXIMUM MODE

1.7.1 8086 IN MINIMUM MODE:

1.7.2 8086 IN MAXIMUM MODE:

14 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING

1.8. TIMING DIAGRAM:

Read cycle Timing Diagram for Minimum Mode:

These are explained in steps:

1. When processor is ready to initiate the bus cycle, it applies a pulse to ALE during T1.
Before the falling edge of ALE, the address, BHE, M/IO, DEN and DT/R must be stable
i.e. DEN = high and DT/R = 0 for input or DT/R = 1 for output.
2. At the trailing edge of ALE, ICs 74LS373 or 8282 latches the address.
3. During T2 the address signals are disabled and S3-S7 ale available on
AD16/S3-AD19/S6 and BHE/S7. Also DEN is lowered to enable transceiver.
4. In case of input operation, RD is activated during T2 and AD° to AD15 go in high
impedance preparing for input.
5. If memory or I/O interface can perform the transfer immediately; there are no wait states
and data is output on the bus during T3.

15 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING
6. After the data is accepted by the processor, RD is raised high at the beginning of T4.
7. Upon detecting this transition during T.4, the memory or I/O device will disable its data
signals.
8. For an output operation, processor applies WR = 0 and then the data on the data bus
during T2.
9. In T4, WR is raised high and data signals are disabled.
10. For either input or output operation, DEN is raised during 14 to disable the transceiver.
Also M/I0 is set according to the next transfer at this time or during next T1 state. Thus
length of bus cycle in 8086 is four clock cycle. If the bus is to be inactive after
completion of bus cycle, then the gap between the successive cycles is filled by ideal
state clock cycles.

16 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING
Memory read timing cycle in maximum mode:

Write cycle timing diagram for minimum mode:

17 ARMIET/COMPUTER/SEM-V/MP
 DEPARTMENT OF COMPUTER ENGINEERING
QUESTION BANK
Q 1: What is a microprocessor?
Q 2: What are different features of 8086 microprocessor/
Q 3: State and explain the 8086 architecture?
Q 4: what is memory segmentation?
Q 5: Explain the programming model of 8086?
Q 6: What is 8086 flag register?
Q 7: explain the timing diagram of 8086?
ASSIGNMENT
Q 1: State and explain the 8086 flag register?
Q 2: Explain the timing diagram of 8086?
Q 2: Explain the programming model of 8086?

18 ARMIET/COMPUTER/SEM-V/MP