Scribd
Upload
17 views2 pages

Ect304 Vlsi Circuit Design, June 2023

The document outlines the examination structure for the VLSI Circuit Design course at APJ Abdul Kalam Technological University, detailing the types of questions in both Part A and Part B. Part A consists of short answer questions worth 3 marks each, while Part B includes full questions from different modules worth 14 marks each. Topics covered include CMOS logic, ASIC design, SoC architecture, and fabrication processes.

Uploaded by

sandra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
17 views2 pages

Ect304 Vlsi Circuit Design, June 2023

The document outlines the examination structure for the VLSI Circuit Design course at APJ Abdul Kalam Technological University, detailing the types of questions in both Part A and Part B. Part A consists of short answer questions worth 3 marks each, while Part B includes full questions from different modules worth 14 marks each. Topics covered include CMOS logic, ASIC design, SoC architecture, and fabrication processes.

Uploaded by

sandra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

B 1200ECT30405230L /-\ V)

,- .t)
ol
,

Reg No.: Name: >j EI


APJ ABDUL KAI,AM TECHNOLOGICAL UNIVERSI
B.Tech Degree 56 (R, S) i 54 (PT) (R, S) Examination June 2023 (2019

Course Code: ECT304


Course Name: VLSI CIRCUIT DESIGN
Max. Marks: 100 Duration:3 Hours
PART A
Answer all questions, each carries 3 marks. Marks

I State Moore's law. (3)


2 Explain what is a SoC. Give applications. (3)
a
J How can you implem ent A(B + A using static CMOS logic? (3)

4 Explain the implementation of a2:l multiplexer using transmission gate logic. (3)
5 Draw the circuit of a 3 input NOR gate using Dynamic CMOS logic. (3)
6 Explain the working of a one transistor DRAM memory cell. (3)
7 What is the critical path and worst case delay in a l6 bit ripple carry adder? (3)
8 Compare the delay performance of ripple carry,linear select and square root carry (3)
select adders as the number of bits increases.

9 Compare wet and dry oxidation in fabrication process. (3)


l0 What is the difference between stick diagram and layout diagram in VLSI design? (3)

PART B
Answer one full question from each module, each carries 14 marks.
Module I
ll a) With flow chart explain ASIC design flow. (10)
b) Compare ASIC and FPGA (4)

a3
12 a) With block diagram explain the internal architecture of a SoC. (7)
b) Explain Full custom and standard cell based ASIC designs. (7)

Module II
13 a) From the VI characteristics of NMOS and PMOS transistors, how can you (10)
graphically arrive at the VTC of a CMOS inverter? Show the different regions of
operation of CMOS inverter in the VTC.
b) Explain the working of a pass transistor. (4)
OR

Page lof2
1200ECT30405230L

14 a) Derive the expression for switching threshold of a CMOS inverter. (T)


b) What are the factors that bffect the static and dynamic power dissipations in a (7)
CMOS circuit? Discuss the total power dissipation with proper equations and
derivations.

Module III
l5 a) Discuss the signal degradation issue that occurs while we cascade dynamic logic (T)
gates. How can we overcome it in domino logic?

b) Explain the implementation of 4x4 NOR based ROM array to store the following (7)
datainword lines- I 000,0 I I 0,0 I 00" 00 I 0.
OR
16 a) With circuit diagram explain the read operation in a 6 transistor static RAM (10)
memory.
b) Write a note on NP domino logic. (4)
Module IV
l7 a) Draw and explain the circuit diagram using CMOS logic to generate sum and carry (7)
out signals in a2bit binary full adder.
b) With block diagram explain the operation of a 16 bit carry bypass adder. (7)
OR
18 a) Explain the implementation of a 16 bit linear carry select adder with block (10)
diagram and compare its delay performance with carry bypass adder.

t b) Draw the implementation of a 4x4 anay multiplier. (4)


Module V
19 a) Explain the steps involved in photolithography process. (7)
b) Explain with set up diagram the process involved in ion implantation process. (7)
OR;
20 a) Explain the process of crystal growth from raw Silicon with sketches. (7)
b) Draw the rough sketch showing the layout diagram of a2input CMOS NAND (7)
gate. Also give the design rules used.
*:1.**

PageZof2

You might also like