WEE DAY TOPICS COVERED VERIFY

K S

DAY Introduction to VLSI Physical Design leant about Introduction to VLSI Design
1 Introduction to VLSI Design

DAY VLSI Physical Design studied about VLSI Physical Design

2
WEEK 1

DAY Complexity Analysis for Algorithms analyied about the Complexity Analysis for Algorithms
3

DAY Graphs for Physical Design studied about Graphs for Physical Design
4

DAY Graph searching Algorithms analyied about the Graph searching Algorithms
5

DAY Graph searching Algorithms analyied about the Graph searching Algorithms
1

DAY Spanning Tree and Shortest Path Algorithms analyied about the Spanning Tree and Shortest Path Algorithms
2
WEEK 2

DAY Spanning Tree and Shortest Path Algorithms analyied about the Spanning Tree and Shortest Path Algorithms
3

DAY Static Timing Analysis Learnt about Timing Analysis

4 Overview of Timing Analysis

DAY Timing Arcs and Unateness Studied about Timing Arcs and Unateness
5

DAY Delay Parameters of Combinational Circuits Studied about Delay Parameters of Combinational Circuits
1

DAY Delay Parameters of Sequential Circuit Studied about Delay Parameters of Combinational Circuits
2
WEEK 3

DAY Timing Analysis in Sequential Circuit Studied about Timing Analysis in Sequential Circuit
3

DAY STA in Sequential Circuit with Clock Skew Studied about STA in Sequential Circuit with Clock Skew
4

DAY STA in Sequential Circuit with Clock Skew Studied about STA in Sequential Circuit with Clock Skew
5

DAY STA in Sequential Circuit with Clock Jitter Studied about STA in Sequential Circuit with Clock Jitter
1
 DAY STA in Sequential Circuit with Clock Jitter Studied about STA in Sequential Circuit with Clock Jitter
2
WEEK 4

DAY STA considering OCV and CRPR ( Setup check) analyied STA considering OCV and CRPR ( Setup check)
3

DAY STA considering OCV and CRPR ( Hold check) analyied STA considering OCV and CRPR ( Hold check)
4

DAY STA for Combinational Circuits Studied about STA for Combinational Circuits
5

DAY Partitioning Learnt about Introduction to Partitioning

1 Introduction to Partitioning

DAY Partitioning Algorithms analyied Partitioning Algorithms

2
5

DAY Partitioning Algorithms analyied Partitioning Algorithms

3

DAY Partitioning Algorithms analyied Partitioning Algorithms

4

DAY Kernighan – Lin (KL) Algorithm analyied Kernighan – Lin (KL) Algorithm
WEEK

DAY Kernighan – Lin (KL) Algorithm analyied Kernighan – Lin (KL) Algorithm
1

DAY Fidduccia-Mattheyeses(FM) Algorithm analyied Fidduccia-Mattheyeses(FM) Algorithm

2
WEEK 6

DAY Fidduccia-Mattheyeses(FM) Algorithm c Fidduccia-Mattheyeses(FM) Algorithm

3

DAY Chip Planning Learnt about Introduction to Floorplanning

4 Introduction to Floorplanning

DAY Floorplanning Representations Studied about Floorplanning Representations

5

DAY Floorplanning Algorithms analyied Floorplanning Algorithms

1

DAY Floorplanning Algorithms analyied Floorplanning Algorithms

2
WEEK 7

DAY Floorplanning Algorithms analyied Floorplanning Algorithms

3

DAY Pin Assignment and Power - Ground Routing Studied about Pin Assignment and Power - Ground Routing
4
 DAY Pin Assignment and Power - Ground Routing Studied about Pin Assignment and Power - Ground Routing
5

DAY Placement Learnt about Introduction to Placement

1 Introduction to Placement

DAY Wirelength estimation techniques Studied about Wirelength estimation techniques

2
WEEK 8

DAY Placement Algorithms Analyied Placement Algorithms

3

DAY Placement algorithms and legalization Analyied Placement Algorithms and legalization
4

DAY Placement algorithms and legalization Analyied Placement Algorithms and legalization
5

DAY Clock Routing Learnt about Introduction to Clock Tree Synthesis

1 Introduction to Clock Tree Synthesis

DAY Clock Routing Algorithms Analyied Clock Routing Algorithms

2
WEEK 9

DAY Clock Routing Algorithms Analyied Clock Routing Algorithms

3

DAY Clock Routing Algorithms Analyied Clock Routing Algorithms

4

DAY Clock Routing Algorithms Analyied Clock Routing Algorithms

5

DAY Global Routing Learnt About Introduction and Optimization Goals

1 Introduction and Optimization Goals

DAY Single net routing (Rectilinear routing) Studied About Single net routing (Rectilinear routing)
2
WEEK 10

DAY Global Routing in the connectivity graph Studied About Global Routing in the connectivity graph
3

DAY Finding Shortest Paths with Dijkstra’s Algorithm Analyied Finding Shortest Paths with Dijkstra’s Algorithm
4

DAY Full-Netlist Routing Studied about Full-Netlist Routing

5

DAY Detailed Routing Learnt About Introduction: Detailed Routing

1 Introduction: Detailed Routing
 DAY Channel Routing Algorithms Analyied Channel Routing Algorithms
2
WEEK 11

DAY Channel Routing Algorithms Analyied Channel Routing Algorithms

3

DAY Channel Routing Algorithms Analyied Channel Routing Algorithms

4

DAY Channel Routing Algorithms Analyied Channel Routing Algorithms

5

DAY Switchbox and Over the cell routing Studied About Switchbox and Over the cell routing
1

DAY Advanced Concepts of Timing Analysis Learnt about Timing analysis in latches
2 Timing analysis in latches
WEEK 12

DAY Timing analysis in latches Studied About Timing analysis in latches

3

DAY Time borrowing in latches Studied About Timing analysis in latches

4

DAY Time borrowing in latches Studied About Timing analysis in latches

5

DAY Crosstalk Analysis Studied about Crosstalk Analysis

1

DAY Crosstalk Analysis Studied about Crosstalk Analysis

2
WEEK 13

DAY SSTA - Statistical Static Timing Analysis Studied about SSTA - Statistical Static Timing Analysis
3

DAY SSTA - Statistical Static Timing Analysis Studied about SSTA - Statistical Static Timing Analysis
4

DAY Input files for VLSI physical design flow Learnt about Standard Cell Library
5 Standard Cell Library

DAY Low Power Cells in Standard Cell Library Studied about Low Power Cells in Standard Cell Library
1

DAY Sub-threshold Standard Cell Library Studied about Sub-threshold Standard Cell Library
2
EEK 14

DAY Timing Library for Standard cells Studied about Timing Library for Standard cells
3
 DAY PDK and Other files Studied about PDK and Other files
W 4

DAY Open-source VLSI Physical Design flow Learnt About Open-source VLSI Physical Design flow
5

DAY Open-Source tool installation and Qflow Studied about Open-Source tool installation and Qflow
1

DAY Open-Source tool installation and Qflow Studied about Open-Source tool installation and Qflow
2
WEEK 15

DAY Open-Source tool- YOSYS Studied about Open-Source tool- YOSYS

3

DAY Open-Source tool- YOSYS Studied about Open-Source tool- YOSYS

4

DAY OpenSTA Static Timing Analyzer Studied about OpenSTA Static Timing Analyzer
5

DAY OpenSTA Static Timing Analyzer Studied about OpenSTA Static Timing Analyzer
1

DAY OpenSTA Static Timing Analyzer Studied about OpenSTA Static Timing Analyzer
2
WEEK 16

DAY OpenROAD Physical Synthesis Flow Studied about OpenROAD Physical Synthesis Flow
3

DAY OpenROAD Physical Synthesis Flow Studied about OpenROAD Physical Synthesis Flow
4

DAY OpenROAD Physical Synthesis Flow Studied about OpenROAD Physical Synthesis Flow
5

DAY Interconnect Modeling and Layout Compaction

1 studied Interconnect Modeling and Layout Compaction
DAY Interconnect Modeling and Layout Compaction
2 studied Interconnect Modeling and Layout Compaction
WEEK 17

DAY Introduction to Testing, Fault Modeling and Simulation

3 studied Introduction to Testing, Fault Modeling and Simulation
DAY Design for Testability: Introduction, Testability Analysis
4 studied Design for Testability: Introduction, Testability Analysis
DAY Design for Testability: DFT Basics
5 studied Design for Testability: DFT Basics
 DAY Design for Testability: Scan cell design
1 studied Design for Testability: Scan cell design
DAY Design for Testability: Scan Architecture
2 studied Design for Testability: Scan Architecture
WEEK 18

DAY
3 Design for Testability: Scan design rules studied Design for Testability:Scan design rules
DAY
4 Design for Testability: Scan design flow studied Design for Testability: Scan design flow
DAY
5 Design for Testability: Scan design rules, Scan design flow studied Design for Testability: Scan design rules, Scan design flow

DAY Fault Simulation: Introduction, Simulation models studied Fault Simulation: Introduction, Simulation models
1
DAY Fault Simulation: Logic simulation, Fault simulation studied Fault Simulation: Logic simulation, Fault simulation
2
DAY
WEEK 19

3 Fault Simulation: Logic simulation, Fault simulation studied Fault Simulation: Logic simulation, Fault simulation
DAY
4 Test Generation: Introduction, Exhaustive testing, Boolean difference studied Test Generation: Introduction, Exhaustive testing, Boolean difference
DAY
5 Test Generation: Boolean difference studied Test Generation: Test Generation: Boolean difference

DAY
1 Test Generation:Basic ATPG algorithms studied Test Generation: Basic ATPG algorithms
DAY
Test Generation: ATPG for non stuck-at faults studied Test Generation: ATPG for non stuck-at faults
2
WEEK 20

DAY
3 Test Generation: Other issues in test generation studied Test Generation: Other issues in test generation

DAY
4 Built-In-Self-Test: Introduction, BIST design rules studied Built-In-Self-Test: Introduction, BIST design rules
DAY
5 Built-In-Self-Test: Test pattern generation, studied Built-In-Self-Test: Test pattern generation,

DAY Built-In-Self-Test: Output response analysis studied Built-In-Self-Test: Output response analysis
1
DAY Built-In-Self-Test: Logic BIST architectures studied Built-In-Self-Test: Logic BIST architectures
2
DAY
WEEK 21

3
Test Compression: Introduction studied Test Compression: Introduction
DAY
4
Test Compression: Stimulus compression studied Test Compression: Stimulus compression
DAY
5 Test Compression: Response compression studied Test Compression: Response compression
 DAY
1 Memory Testing: Introduction, RAM fault models studied Memory Testing: Introduction, RAM fault models
DAY
2 Memory Testing: RAM test generation studied Memory Testing: RAM test generation
WEEK 22

DAY
3 Aware Test: Importance, Power models, Low power ATPG studied Aware Test: Importance, Power models, Low power ATPG
DAY
4 Memory Testing: Memory BIST Power and Thermal studied Memory Testing: Memory BIST Power and Thermal
DAY
5 Aware Test: Importance, Power models, Low power ATPG studied Aware Test: Importance, Power models, Low power ATPG

DAY Power and Thermal Aware Test: Low power BIST, Thermal aware studied Power and Thermal Aware Test: Low power BIST, Thermal aware
1
techniques techniques
DAY Power and Thermal Aware Test: Low power BIST, Thermal aware studied Power and Thermal Aware Test: Low power BIST, Thermal aware
2
techniques techniques
DAY Low Power Design Techniques studied Low Power Design Techniques
WEEK 23

3
DAY
4 Low Power Design Techniques studied Low Power Design Techniques

DAY Low Power Design Techniques studied Low Power Design Techniques
5
DAY
1 VLSI Sub Systems: CMOS Transistors, Inverter and characteristics studied VLSI Sub Systems: CMOS Transistors, Inverter and characteristics
DAY VLSI Sub Systems: Noise Margin and Delay of Inverter, RC Delay, studied VLSI Sub Systems: Noise Margin and Delay of Inverter, RC Delay,
2
Delay optimization Delay optimization
WEEK 24

DAY VLSI Sub Systems: Combinatorial Circuit Family, Stick Diagram & studied VLSI Sub Systems: Combinatorial Circuit Family, Stick Diagram &
3
Interconnects Interconnects
DAY VLSI Sub Systems: Power, Static Power, and CMOS Latch and flipflop studied VLSI Sub Systems: Power, Static Power, and CMOS Latch and flipflop
4
design, Static Timing Analysis design, Static Timing Analysis
DAY
5 Adder subsystem design, and Approximate Computing studied Adder subsystem design, and Approximate Computing