III-BCA DIGITAL COMPUTER FUNDAMENTALS UNIT-IV

UNIT – IV

Combinational Logic Circuits

Combinational circuit is a circuit in which we combine the different gates in the circuit, for
example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of
combinational circuits are following −

 The output of combinational circuit at any instant of time, depends only on the levels
present at input terminals.

 The combinational circuit do not use any memory. The previous state of input does not
have any effect on the present state of the circuit.

 A combinational circuit can have an n number of inputs and m number of outputs.

Block diagram

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We're going to elaborate few important combinational circuits as follows.

Adders
An adder is a digital logic circuit in electronics that is extensively used for the addition of
numbers. In many computers and other types of processors, adders are even used to calculate
addresses and related activities and calculate table indices in the ALU and even utilized in other
parts of the processors. These can be built for many numerical representations like excess-3 or
binary coded decimal. Adders are basically classified into two types: Half Adder and Full Adder.

Half Adder
Half adder is a combinational logic circuit with two inputs and two outputs. The half adder
circuit is designed to add two single bit binary number A and B. It is the basic building block
for addition of two single bit numbers. This circuit has two outputs carry and sum.

Block diagram

The sum (S) is a 1 when A and B are different and the A and B are1 then carry(C) is a 1.

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Circuit Diagram

Truth Table

Full Adder
Full adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists
of three inputs and two outputs. Two of the input variables denoted by A and B . The third input
Cin, represents the carry from the previous position.

The two outputs are designated by the symbols S for sum and C o for carry.

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Block diagram

A full adder may be constructed by using two half-adders and an OR gate as shown below.

Note

3-Input Ex-OR gate logic symbol

Truth table of 3 input xor gate

For XOR gates, we can have the HIGH input when odd numbers of inputs are at HIGH level. So
the 3-input OR gate is called as “Odd functioned OR gate”.

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Circuit Diagram

Truth Table

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Binary Subtractor
The Binary Subtractor is another type of combinational arithmetic circuit that produces an output
which is the subtraction of two binary numbers

Half Subtractor

Half subtractor is a combination circuit with two inputs and two outputs (difference and
borrow). It produces the difference between the two binary bits at the input and also produces
an output (Borrow) to indicate if a 1 has been borrowed. In the subtraction (A-B), A is called as
Minuend bit and B is called as Subtrahend bit.

Circuit Diagram

Truth Table

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Full Subtractors
The full subtractor is a combinational circuit with three inputs A,B,C and two output D and C'.
A is the 'minuend', B is 'subtrahend', C is the 'borrow' produced by the previous stage, D is the
difference output and C' is the borrow output.

Block Diagram

Circuit Diagram

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Truth Table

BCD Adder
BCD stand for binary coded decimal. Suppose, we have two 4-bit numbers A and B. The value of
A and B can varies from 0(0000 in binary) to 9(1001 in binary) because we are considering
decimal numbers.

BCD adder A 4-bit binary adder that is capable of adding two 4-bit words having a BCD
(binary-coded decimal) format. The result of the addition is a BCD-format 4-bit output word,
representing the decimal sum of the addend and augend, and a carry that is generated if this sum
exceeds a decimal value of 9. Decimal addition is thus possible using these devices.

To implement BCD adder we require:

• 4-bit binary adder for initial addition

• Logic circuit to detect sum greater than 9

• One more 4-bit adder to add in the sum if sum is greater than 9 or carry is 1
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The logic circuit to detect sum greater than 9 can be determined by simplifying the Boolean
expression of given truth Table.

1. Y=1 indicates sum is greater than 9. We can put one more term, C_out in the above
expression to check whether carry is one.

2. If any one condition is satisfied we add 6(0110) in the sum.

3. With this design information we can draw the block diagram of BCD adder, as shown in
figure below.

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1. As shown in the Fig, the two BCD numbers, together with input carry, are first added in
the top 4-bit binary adder to produce a binary sum.

2. When the output carry is equal to zero (i.e. when sum <= 9 and C_out = 0) nothing (zero)
is added to the binary sum.

When it is equal to one (i.e. when sum > 9 or C_out = 1), binary 0110 is added to the
binary sum through the bottom 4-bit binary adder.

3. The output carry generated from the bottom binary adder can be ignored, since it supplies
information already available at the output carry terminal.

Multiplexers
Multiplexer is a combinational circuit that has maximum of 2 n data inputs, ‘n’ selection lines
and single output line. One of these data inputs will be connected to the output based on the
values of selection lines. Multiplexer is also called as Mux.

4x1 Multiplexer
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y.
The block diagram of 4x1 Multiplexer is shown in the following figure.

One of these 4 inputs will be connected to the output based on the combination of inputs present
at these two selection lines. Truth table of 4x1 Multiplexer is shown below.

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Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

From Truth table, we can directly write the Boolean function for output, Y as

Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3

We can implement this Boolean function using Inverters, AND gates & OR gate. The circuit
diagram of 4x1 multiplexer is shown in the following figure.

We can easily understand the operation of the above circuit. Similarly, you can implement 8x1
Multiplexer and 16x1 multiplexer by following the same procedure.

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Implementation of Higher-order Multiplexers.

Now, let us implement the following two higher-order Multiplexers using lower-order
Multiplexers.

 8x1 Multiplexer

 16x1 Multiplexer

8x1 Multiplexer

In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1 Multiplexer.
We know that 4x1 Multiplexer has 4 data inputs, 2 selection lines and one output. Whereas, 8x1
Multiplexer has 8 data inputs, 3 selection lines and one output.

So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs. Since, each
4x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by
considering the outputs of first stage as inputs and to produce the final output.

Let the 8x1 Multiplexer has eight data inputs I 7 to I0, three selection lines s2, s1 & s0 and one
output Y. The Truth table of 8x1 Multiplexer is shown below.

Selection Inputs Output

S2 S1 S0 Y

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7

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We can implement 8x1 Multiplexer using lower order Multiplexers easily by considering the
above Truth table. The block diagram of 8x1 Multiplexer is shown in the following figure.

The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data inputs of upper
4x1 Multiplexer are I7 to I4 and the data inputs of lower 4x1 Multiplexer are I 3 to I0. Therefore,
each 4x1 Multiplexer produces an output based on the values of selection lines, s 1 & s0.

The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is
present in second stage. The other selection line, s2 is applied to 2x1 Multiplexer.

 If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I 3 to I0 based
on the values of selection lines s1 & s0.

 If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I 7 to I4 based
on the values of selection lines s1 & s0.

Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer performs
as one 8x1 Multiplexer.

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16x1 Multiplexer
In this section, let us implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1 Multiplexer.
We know that 8x1 Multiplexer has 8 data inputs, 3 selection lines and one output. Whereas,
16x1 Multiplexer has 16 data inputs, 4 selection lines and one output.

So, we require two 8x1 Multiplexers in first stage in order to get the 16 data inputs. Since, each
8x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by
considering the outputs of first stage as inputs and to produce the final output.

Let the 16x1 Multiplexer has sixteen data inputs I 15 to I0, four selection lines s3 to s0 and one
output Y. The Truth table of 16x1 Multiplexer is shown below.

Selection Inputs Output

S3 S2 S1 S0 Y

0 0 0 0 I0

0 0 0 1 I1

0 0 1 0 I2

0 0 1 1 I3

0 1 0 0 I4

0 1 0 1 I5

0 1 1 0 I6

0 1 1 1 I7

1 0 0 0 I8

1 0 0 1 I9

1 0 1 0 I10

1 0 1 1 I11

1 1 0 0 I12

1 1 0 1 I13

1 1 1 0 I14

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1 1 1 1 I15

We can implement 16x1 Multiplexer using lower order Multiplexers easily by considering the
above Truth table. The block diagram of 16x1 Multiplexer is shown in the following figure.

The same selection lines, s2, s1 & s0 are applied to both 8x1 Multiplexers. The data inputs of
upper 8x1 Multiplexer are I15 to I8 and the data inputs of lower 8x1 Multiplexer are I 7 to I0.
Therefore, each 8x1 Multiplexer produces an output based on the values of selection lines, s 2,
s1 & s0.

The outputs of first stage 8x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is
present in second stage. The other selection line, s3 is applied to 2x1 Multiplexer.

 If s3 is zero, then the output of 2x1 Multiplexer will be one of the 8 inputs Is 7 to I0 based
on the values of selection lines s2, s1 & s0.

 If s3 is one, then the output of 2x1 Multiplexer will be one of the 8 inputs I 15 to I8 based
on the values of selection lines s2, s1 & s0.

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Therefore, the overall combination of two 8x1 Multiplexers and one 2x1 Multiplexer performs
as one 16x1 Multiplexer.

Demultiplexers
De-Multiplexer is a combinational circuit that performs the reverse operation of Multiplexer. It
has single input, ‘n’ selection lines and maximum of 2n outputs. The input will be connected to
one of these outputs based on the values of selection lines.

Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So,
each combination can select only one output. De-Multiplexer is also called as De-Mux.

1x4 De-Multiplexer
1x4 De-Multiplexer has one input I, two selection lines, s1 & s0 and four outputs Y3, Y2,
Y1 &Y0. The block diagram of 1x4 De-Multiplexer is shown in the following figure.

The single input ‘I’ will be connected to one of the four outputs, Y3 to Y0 based on the values of
selection lines s1 & s0. The Truth table of 1x4 De-Multiplexer is shown below.

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Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

From the above Truth table, we can directly write the Boolean functions for each output as

Y3=s1s0IY3=s1s0I

Y2=s1s0′IY2=s1s0 ′I

Y1=s1′s0IY1=s1 ′s0I

Y0=s1′s0 ′IY0=s1 ′s0′I

We can implement these Boolean functions using Inverters & 3-input AND gates. The circuit
diagram of 1x4 De-Multiplexer is shown in the following figure.

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Decoder
Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2n output lines. One
of these outputs will be active High based on the combination of inputs present, when the
decoder is enabled. That means decoder detects a particular code. The outputs of the decoder
are nothing but the min terms of ‘n’ input variables lineslines, when it is enabled.

2 to 4 Decoder
Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0. The block
diagram of 2 to 4 decoder is shown in the following figure.

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One of these four outputs will be ‘1’ for each combination of inputs when enable, E is ‘1’.
The Truth table of 2 to 4 decoder is shown below.

Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

From Truth table, we can write the Boolean functions for each output as

Y3=E.A1.A0Y3=E.A1.A0

Y2=E.A1.A0′Y2=E.A1.A0 ′

Y1=E.A1′.A0Y1=E.A1 ′.A0

Y0=E.A1′.A0′Y0=E.A1 ′.A0 ′

Each output is having one product term. So, there are four product terms in total. We can
implement these four product terms by using four AND gates having three inputs each & two
inverters. The circuit diagram of 2 to 4 decoder is shown in the following figure.

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Therefore, the outputs of 2 to 4 decoder are nothing but the min terms of two input variables
A1 & A0, when enable, E is equal to one. If enable, E is zero, then all the outputs of decoder will
be equal to zero.

Similarly, 3 to 8 decoder produces eight min terms of three input variables A2, A1 & A0 and 4 to
16 decoder produces sixteen min terms of four input variables A3, A2, A1 & A0.

Implementation of Higher-order Decoders

Now, let us implement the following two higher-order decoders using lower-order decoders.

 3 to 8 decoder

 4 to 16 decoder

3 to 8 Decoder
In this section, let us implement 3 to 8 decoder using 2 to 4 decoders. We know that 2 to 4
Decoder has two inputs, A1 & A0 and four outputs, Y3 to Y0. Whereas, 3 to 8 Decoder has three
inputs A2, A1 & A0 and eight outputs, Y7 to Y0.
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Therefore, we require two 2 to 4 decoders for implementing one 3 to 8 decoder. The block
diagram of 3 to 8 decoder using 2 to 4 decoders is shown in the following figure.

The parallel inputs A1 & A0 are applied to each 2 to 4 decoder. The complement of input A2 is
connected to Enable, E of lower 2 to 4 decoder in order to get the outputs, Y3 to Y0. These are
the lower four min terms. The input, A2 is directly connected to Enable, E of upper 2 to 4
decoder in order to get the outputs, Y7 to Y4. These are the higher four min terms.

4 to 16 Decoder
In this section, let us implement 4 to 16 decoder using 3 to 8 decoders. We know that 3 to 8
Decoder has three inputs A2, A1 & A0 and eight outputs, Y7 to Y0. Whereas, 4 to 16 Decoder
has four inputs A3, A2, A1 & A0 and sixteen outputs, Y15 to Y0

Therefore, we require two 3 to 8 decoders for implementing one 4 to 16 decoder. The block
diagram of 4 to 16 decoder using 3 to 8 decoders is shown in the following figure.

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The parallel inputs A2, A1 & A0 are applied to each 3 to 8 decoder. The complement of input,
A3 is connected to Enable, E of lower 3 to 8 decoder in order to get the outputs, Y 7 to Y0. These
are the lower eight min terms. The input, A3 is directly connected to Enable, E of upper 3 to 8
decoder in order to get the outputs, Y15 to Y8. These are the higher eight min terms.

Encoder
An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has
maximum of 2n input lines and ‘n’ output lines. It will produce a binary code equivalent to the
input, which is active High. Therefore, the encoder encodes 2n input lines with ‘n’ bits. It is
optional to represent the enable signal in encoders.

4 to 2 Encoder
Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. The block
diagram of 4 to 2 Encoder is shown in the following figure.

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At any time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code at
the output. The Truth table of 4 to 2 encoder is shown below.

Inputs Outputs

Y3 Y2 Y1 Y0 A1 A0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

From Truth table, we can write the Boolean functions for each output as
A1=Y3+Y2 A1=Y3+Y2
A0=Y3+Y1 A0=Y3+Y1
We can implement the above two Boolean functions by using two input OR gates. The circuit
diagram of 4 to 2 encoder is shown in the following figure.

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The above circuit diagram contains two OR gates. These OR gates encode the four inputs with
two bits

Octal to Binary Encoder

Octal to binary Encoder has eight inputs, Y7 to Y0 and three outputs A2, A1 & A0. Octal to
binary encoder is nothing but 8 to 3 encoder. The block diagram of octal to binary Encoder is
shown in the following figure.

At any time, only one of these eight inputs can be ‘1’ in order to get the respective binary code.
The Truth table of octal to binary encoder is shown below.

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Inputs Outputs

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

From Truth table, we can write the Boolean functions for each output as

A2=Y7+Y6+Y5+Y4 A2=Y7+Y6+Y5+Y4

A1=Y7+Y6+Y3+Y2 A1=Y7+Y6+Y3+Y2

A0=Y7+Y5+Y3+Y1 A0=Y7+Y5+Y3+Y1

We can implement the above Boolean functions by using four input OR gates. The circuit
diagram of octal to binary encoder is shown in the following figure.

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The above circuit diagram contains three 4-input OR gates. These OR gates encode the eight
inputs with three bits.

Floating Point Number Representations

The number which has both an integer and a fractional part is called as floating point
number.The floating point number can be used to represent large as well as small fraction or
mixed number.

The floating number representation of a number has two part: the first part represents a signed
fixed point number called mantissa. The second part of designates the position of the decimal (or
binary) point and is called the exponent.

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Representation of floating point numbers

Floating point numbers are represented in the form m * re, where m is the mantissa, r is
the radix or base, and e is the exponent.
A binary floating point number can be represented internally in the computer as a binary
sequence with 2 fields as illustrated below:

Exponent
Mantissa (m)
(e)

The radix r is understood to be 2 and the computer doesn't need to store it explicitly.

Example:

1.0110112 * 23 is equivalent to 1011.0112

The mantissa is 1.011011, the radix is 2, and the exponent is 3.

Only the mantissa m and the exponent e are physically represented in the register (including their
sign). A floating-point binary number is represented in a similar manner except that is uses base
2 for the exponent. A floating-point number is said to be normalized if the most significant digit
of the mantissa is 1.

Example
The −53.5 is normalized as -53.5=(-110101.1)2=(-1.101011)x25 , which is represented as
following below,

Where 00000101 is the 8-bit binary value of exponent value +5.

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Range of stored Numbers

A 32 bit word is employed to store numbers, in which the mantissa part is stored in 23 bits and
8 bits are allotted to the exponent part. The sign bit(1bit) is included in both the cases.

Bit No Size Field Name

31 1 bit Sign (S)

23-30 8 bits Exponent (E)

0-22 23 bits Mantissa (M)

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