CNN-BASED SUCCESSIVE CANCELLATION DECODING

ALGORITHM FOR URLLC

Gokul. E, B.E. ECE, AIHT, gokulme2004 2gmail.com
Sivaprasath. R, B.E. ECE, AIHT, [email protected]
Santhosh Kumar. R, B.E. ECE, AIHT, [email protected]
Ms. Gangalakshmi. S, AP/ECE, AIHT, [email protected]

ABSTRACT— Ultra-Reliable Low Latency Communications (URLLC) is essential for 5G and

beyond, supporting real-time applications such as industrial automation and autonomous
vehicles. Ultra-low latency and high reliability over error-prone wireless channels are difficult
to achieve. Polar codes provide capacity-achieving performance, but traditional successive
cancellation (SC) decoding has high complexity and bad short-block performance.

This work suggests a CNN-aided SC decoding algorithm that increases error correction and
lowers latency through learning bit reliability patterns for SC decision dynamics. Experimental
results indicate a 45% reduction in latency and a 30% gain in BER compared to traditional
SC decoding, showcasing the prospects of CNN-aided SC decoding for URLLC in future
wireless networks.

Keywords—Ultra Reliable Low Latency Communications (URLLC), Polar Codes, Successive

Cancellation (SC) Decoding, Convolutional Neural Networks (CNNs), FPGA, Low Latency,
5G, Machine Learning in Wireless Communication, Deep Learning for Error Correction,
Forward Error Correction (FEC), Bit Error Rate (BER)

I. INTRODUCTION
The advent of 5G and beyond has further fueled the necessity of URLLC to enable real-time
applications such as telemedicine, autonomous vehicles, and industrial automation with sub-1
ms latency and 99.999% reliability. Wireless channel impairments render decoding difficult,
but deep learning, especially CNNs, has been promising in improving SC decoding by
estimating bit reliability and reducing error propagation. Through the use of CNNs, the above
approach adaptively improves SC decoding judgments with less latency and higher accuracy.
In addition, FPGA implementation allows efficient parallel computation, which facilitates real-
time processing at low energy cost. This paper introduces a CNN-based SC decoder on FPGA
that exhibits better decoding quality and resilience over traditional SC decoders.

II. EXISTING APPROACH

Error correction coding for URLLC has evolved considerably in the last decade to address the
requirements of high-reliability, low-latency communication in 5G and beyond. Although
successive cancellation (SC) decoding is still basic for polar codes because of its low
complexity, it is plagued by error propagation and latency, particularly for short block lengths.
Improvements like successive cancellation list (SCL) decoding, deep learning-based methods,
and hardware acceleration have been investigated to enhance performance. Deep neural
networks (DNNs), especially CNNs, have been promising in learning error correction patterns
and optimizing decoding. In contrast to RNNs and LSTMs, which suffer from high inference
latency, CNNs extract spatial correlations efficiently, allowing parallel processing for
decoding. But running CNNs on memory- and power-limited systems such as FPGAs is still
challenging to achieve.
 PROPOSED APPROACH
III.
The presented CNN-based successive cancellation (CNN-SC) decoding algorithm can boost
the performance of the traditional SC decoding with the assistance of deep learning
technology to increase the estimation accuracy of bits and suppress error propagation.
Incorporating the application of CNN models into SC decoding results in considerable
reduction of latency while promoting decoding efficiency, making it a good fit for URLLC.

A. CNN MODEL ARCHITECTURE FOR SUCCESSIVE CANCELLATION DECODING

The fundamental concept of the CNN-SC decoder is to learn the mapping between received
log-likelihood ratios (LLRs) and transmitted bits, allowing for more precise decoding decisions
than traditional SC decoding. The CNN model has a structured pipeline:

INPUT LAYER – The input to the CNN is LLR values associated with received polar codewords.
These values indicate the probability of each transmitted bit being 0 or 1.

CONVOLUTIONAL LAYERS – Multiple convolutional layers are employed to extract spatial

features from the LLR sequences. Each layer applies learnable filters that detect patterns in
noisy input signals, improving bit prediction accuracy.

BATCH NORMALIZATION AND ACTIVATION – Batch normalization is applied after each

convolutional layer to stabilize training and accelerate convergence. ReLU (Rectified Linear
Unit) activation is used to introduce non linearity into the model, ensuring better learning of
complex patterns.

POOLING LAYERS – Pooling techniques are utilized in order to lower dimensionality with
maintaining key information. Max pooling is utilized to highlight the most robust bit reliability
characteristics.

OUTPUT LAYER – The output is in the form of the estimated binary sequence, which again
utilizes SC logic to guarantee proper decoding choices.

B. TRAINING METHODOLOGY
The CNN model is trained from synthetically produced datasets that include encoded polar
codewords transmitted through a noisy channel.

CHANNEL MODEL – Transmitted polar-coded bits go through an Additive White Gaussian

Noise (AWGN) channel with different Signal-to-Noise (SNRs).

LLR COMPUTATION – The LLR values are calculated from the received noisy signals at the
receiver side. LLR values serve as the input to the CNN model, whereas the matched
transmitted bits are used as the ground truth labels.

C. FPGA-BASED IMPLEMENTATION AND ACCELERATION

For real-time execution, the suggested CNN-SC decoder is deployed on an FPGA to take
advantage of its parallel processing capability to accelerate inference.
FIXED-POINT QUANTIZATION – As floating-point calculations are costly on FPGA, the
learned CNN weights are mapped to fixed-point representations, lowering computational
complexity.

PIPELINE EXECUTION – The FPGA implementation is based on a pipeline structure, where

various CNN operations (convolution, pooling, activation) are executed in parallel, lowering
processing time.

MEMORY OPTIMIZATION – On-chip memory resources like Block RAM (BRAM) are used
for effective storage of intermediate computations, lowering latency.
IV. RESULT AND PERFORMANCE EVALUATION
The CNN-based successive cancellation (CNN-SC) decoding algorithm is assessed in terms of
bit error rate (BER), decoding delay, and power efficiency. In comparison with traditional SC
decoding, it exhibits better performance at different levels of SNR. The CNN-SC decoder is
confirmed through software simulation and FPGA-based real-time implementation with better
error correction, computational rate, and energy efficiency.

Figure 1: Python Model Output for CNN-SC Decoding

A. BIT ERROR RATE (BER) PERFORMANCE

Bit error rate (BER) is a key measure of decoding reliability. The CNN-SC decoder, evaluated
in an AWGN channel, significantly outperforms standard SC decoding, especially at low SNRs
where noise impact is high.
SNR (dB) Traditional SC BER Proposed CNN SC Improvement
BER (%)

0dB 15.30% 9.20% 39.90%

2dB 8.70% 4.50% 48.30%

4dB 2.90% 12.% 58.60%

6db 1.10% 0.40% 63.60%

Table I: BER Comparison of SC and CNN-SC Decoders

B. ANALYSIS OF DECODING LATENCY

Low latency is crucial for real-time URLLC. Traditional SC decoding suffers from sequential
delays, hindering sub-millisecond performance. The CNN-SC decoder, with parallelized
decision-making and FPGA acceleration, significantly reduces latency, as shown in Table II.

Decoding Method Latency per Codeword (ms) Reduction (

)

Traditional SC (Software) 2.2 ms —

CNN-SC (Software) 1.6 ms 27.30%

CNN-SC (FPGA) 1.2 ms 45.50%

Table II: Decoding Latency Comparison

Figure 2: MATLAB Model Output for CNN-SC Decoding

C. POWER EFFICIENCY

Conventional software-oriented SC decoding is based on power-hungry CPU computations,

while the CNN-SC decoder on FPGA enjoys hardware-optimized execution.
 Figure 3: MATLAB Model Output for CNN-SC Decoding

Implementation Power Consumption (W) Reduction (%)

SC Decoding (Software) 2.8 W —

CNN-SC Decoding (Software) 2.4 W 14.30%

CNN-SC Decoding (FPGA) 1.9 W 32.10%

Table III: Power Consumption Comparison

D. COMPARATIVE ANALYSIS WITH EXISTING DECODERS

In order to further establish the efficacy of the CNN-SC decoder, a comparison with other state-
of-the-art decoders, like Successive Cancellation List (SCL) decoding, is made. Although SCL
decoding enhances reliability, at the cost of increased complexity and latency, hence less
suitable for URLLC. The CNN-SC decoder strikes a good balance between minimal
complexity and enhanced reliability, as presented in Table IV.

Decoder BER Improvement (%) Latency (ms) Power Efficiency

Traditional SC — 2.2 ms Baseline

SCL Decoding 70% 5.5 ms High Power Consumption

CNN-SC (FPGA) 60% 1.2 ms 32% Power Reduction

Table IV: Comparison of Decoding Methods

 V. CONCLUSION
The work introduces a CNN-based successive cancellation (CNN-SC) decoding algorithm
optimized for URLLC in 5G and beyond. SC decoding is optimal for polar codes, but its latency
and error propagation prevent real-time performance. To overcome this, a CNN-aided method
improves bit reliability estimation, minimizing errors and delays. Trained from AWGN channel
data, the CNN enhances SC decisions, whereas FPGA acceleration achieves low-power and
real-time capabilities through fixed-point quantization and parallel processing. The result
depicts a 30% reduced BER and 45% lower latency compared to the conventional SC decoding.
This effort closes the loop between AI-powered and traditional decoding, providing a low
latency, efficient solution for future wireless network. Subsequent efforts wil target hybrid
architecture, quantization-aware training and over-the-air testing.

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