RF Transceiver Design

Module 9 Lecture 58
Basic of Phase Locked Loop

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Phase-Locked Loops
➢ Order and Type
• Basic Concepts
• Type-I PLLs
• Type-II PLLs
➢ Frequency Ranges
➢ Loop Bandwidth
➢ Phase Noise
➢ Transient response
➢ Steady-state errors
➢ Basic Parameters: Power, supply, amplitude
➢ Spectrum Purity at Output

2
Phase Detector

Phase
Detector

• A PD is a circuit that senses two periodic inputs and produces an output whose average
value is proportional to the difference between the phases of the inputs
• The input/output characteristic of the PD is ideally a straight line,
• with a slope called the “gain” and denoted by KPD

3
Example of Phase Detector
Must the two periodic inputs to a PD have equal frequencies?

4
 𝑋1(𝑡)
𝑋1(𝑡)
𝑋2(𝑡)
𝑋𝑜𝑢𝑡(𝑡) ∆∅
𝑋2(𝑡)

𝑋𝑜𝑢𝑡(𝑡)

• We seek a circuit whose average output is

proportional to the input phase difference.
• An Exclusive-OR (XOR) gate can serve this
purpose. It generates pulses whose width is
equal to Δϕ

5
Type-I PLLs: Alignment of a VCO’s Phase

(1)change the frequency of the VCO

(2)allow the VCO to accumulate phase faster(or more slowly) than
the reference so that the phase error vanishes
(3)change the frequency back to its initial value

6
Simple PLL and Loop Filter

PD VCO PD LPF VCO

➢ Negative feedback loop: if the “loop gain” is sufficiently high, the circuit minimizes the
input error.
➢ The PD produces repetitive pulses at its output, modulating the VCO frequency and
generating large sidebands.
➢ Interpose a low-pass filter between the PD and
the VCO to suppress these pulses.

7
A student reasons that the negative feedback loop must force the phase error to zero, in
which case the PD generates no pulses and the VCO is not disturbed. Thus, a low-pass filter is
not necessary.

As explained later, this feedback system suffers from a finite loop gain, exhibiting a finite
phase error in the steady state. Even PLLs having an infinite loop gain contain nonidealities
that disturb Vcont

8
Simple PLL: Phase Locking

+
PLL
-

∅𝑜𝑢𝑡 − ∅𝑖𝑛 = 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡

𝑑∅𝑜𝑢𝑡 𝑑∅𝑖𝑛
=
𝑑𝑡 𝑑𝑡
➢ We say the loop is “locked” if ϕout(t)-ϕin(t) is constant with
time.
➢ An important and unique consequence of phase locking is
that the input and output frequencies of the PLL are exactly
equal.
9
Analysis of Simple PLLs

➢ If the loop is locked, the input and output frequencies are equal,
the PD generates repetitive pulses, the loop filter extracts the
average level , and the VCO senses this level so as to operate at
required frequency

10
Example of Phase Error
• If the input frequency changes by Δω, how much is the change in the phase error? Assume the loop
remains locked.

• Depicted in the figure above, such a change requires Vcont change by

Δω/KVCO. This in turn necessitates a phase error change of
∆𝜔
∆∅2 − ∆∅1 =
𝐾𝑉𝐶𝑂 𝐾𝑃𝐷
• The key observation here is that the phase error varies with the frequency.
• To minimize this variation, KPDKVCO must be maximized.
• This quantity is sometimes called the “loop gain” even though it is not dimensionless.
11
Response of PLL to Input Frequency Step

PD VCO

➢ The loop locks only after two conditions are satisfied:

(1)ωout becomes equal to ωin
(2)the difference between ϕin and ϕout settles to its proper value

12
Example of FSK Input Applied to PLL
An FSK waveform is applied to a PLL. Sketch the control voltage as a function of time.

Vcont
t
The input frequency toggles between two values and so does the output
frequency. The control voltage must also toggle between two values.
The control voltage waveform therefore appears as shown in figure above,
providing the original bit stream. That is, a PLL can serve as an
FSK (and, more generally, FM) demodulator if Vcont is considered the output.
13
PLL No Better than a Wire?
Having carefully followed our studies thus far, a student reasons that, except for the FSK
demodulator application, a PLL is no better than a wire since it attempts to make the input
and output frequencies and phases equal! What is the flaw in the student’s argument?

• Nonetheless, we can observe that the dynamics of the loop can yield interesting and useful properties.
• Suppose in the previous example, the input frequency toggles at a relatively high rate, leaving little time for the PLL
to “keep up.”
• As illustrated in figure, at each input frequency jump, the control voltage begins to change in the opposite direction
but does not have enough time to settle.
• In other words, the output frequency excursions are smaller than the input
frequency jumps.
• The loop thus performs low-pass filtering on the input frequency variations—just as
the unity-gain buffer performs low-pass filtering on the input voltage variations if
the op amp has a limited bandwidth.
• In fact, many applications incorporate PLLs to reduce the frequency or phase noise
of a signal by means of this low-pass filtering property.

14
Loop Dynamics: the Meaning of Transfer Function in Phase
Domain +
-

PLL

➢ The transfer function of a voltage-domain circuit signifies how a

sinusoidal input voltage propagates to the output.
➢ The transfer function of a PLL must reveal how a slow or a fast
change in the input (excess) phase propagates to the output.

15
 𝐾𝑉𝐶𝑂
𝑠

The open-loop transfer function 𝐾𝑃𝐷 Τ(𝑅1 𝐶1 𝑠 + 1) 𝐾𝑉𝐶𝑂 /𝑠

Overall closed-loop transfer function
∅ 𝐾𝑃𝐷 𝐾𝑉𝐶𝑂
H(s)= ∅𝑜𝑢𝑡 𝑠 = 𝑅 2
𝑖𝑛 1 𝐶1 𝑠 +𝑠+𝐾𝑃𝐷 𝐾𝑉𝐶𝑂

the open-loop transfer function contains one pole at the origin

-> This system is called “type-I PLL.”
-> slow input phase variations (s ≈ 0), H(s) ≈ 1

16
Damping Factor and Natural Frequency
➢ The damping factor ≈ 𝜔𝑛2
𝐻 𝑆 = 2
2 /2 be or larger so as to 𝑠 + 2ζ𝜔𝑛 𝑠 + 𝜔𝑛2
provide a well-behaved
1 𝜔𝐿𝑃𝐹
(critical damped or ζζType
= equation here.
overdamped) response. 2 𝐾𝑃𝐷 𝐾𝑉𝐶𝑂
➢ ωLPF=1/(R1C1)
𝜔𝑛 = 𝐾𝑃𝐷 𝐾𝑉𝐶𝑂 𝜔𝐿𝑃𝐹

• ζ is inversely proportional to KVCO.

• The behavior of the open-loop transfer function, Hopen, for two

different values of KVCO. As KVCO increases, the unity-gain frequency
rises, thus reducing the phase margin (PM).

17
Two Additions for Loop Dynamics
➢ Since a linear, time-invariant operation relates phase and frequency, the equation below
applies to frequency quantities.
𝜔𝑛2
𝐻 𝑆 = 2
𝑠 + 2ζ𝜔𝑛 𝑠 + 𝜔𝑛2

How do we ensure the feedback of previous simple PLL implementation is negative?

• The phase detector provides both negative and positive gains. Thus, the loop automatically
locks with negative feedback.

18
Frequency Multiplication
+
PD VCO
-

÷2

➢ The output frequency of a PLL can be divided and then fed back.
➢ The ÷M circuit is a counter that generates one output pulse
for every M input pulses.
➢ The divide ratio, M, is called the “modulus”.

19
Drawbacks of Simple PLL
➢ First, a tight relation between the loop stability and the corner frequency of the low-pass
filter. Ripple on the control line modulates the VCO frequency and must be suppressed by
choosing a low value for ωLPF, leading to a less stable loop
1 𝜔𝐿𝑃𝐹
ζ=
2 𝐾𝑃𝐷 𝐾𝑉𝐶𝑂
➢ Second, the simple PLL suffers from a limited “acquisition range”. If the VCO frequency and
the input frequency are very different at the start-up, the loop may never “acquire” lock.

➢ In addition, the finite static phase error and its variation with the
input frequency also prove undesirable in some applications.

20
 RF Transceiver Design
Module 9 Lecture 59
Basic of Phase Locked Loop

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

21
Type-II PLLs: Phase/Frequency Detectors
PFD

➢ A rising edge on A yields a rising edge on QA (if QA is low)

➢ A rising edge on B resets QA (if QA is high)
➢ The circuit is symmetric with respect to A and B (and QA and QB)

22
Operation of PFD: State Diagram

𝑄𝐴 = 0 𝑄𝐴 = 0 𝑄𝐴 = 1
𝑄𝐵 = 1 𝑄𝐵 = 0 𝑄𝐵 = 0

➢ At least three logical states are necessary: QA=QB=0; QA=0, QB=1;

and QA=1, QB=0
➢ To avoid dependence of the output upon the duty cycle of the
inputs, the circuit should be realized as an edge-triggered
sequential machine

23
Use of a PFD in PLL
D
Q
CK

D
Q
CK

➢ QA and QB are simultaneously high for a duration given by the

total delay through the AND gate and the reset path of the flipflops.
➢ The width of the narrow reset pulses on QA and QB is equal to
three gate delays plus the delay of the AND gate

24
PFD: Logical Implementation

+
PFD 𝐴 VCO
- 1

➢ Using a PFD in a phase-locked loop resolves the issue of the limited acquisition range.
➢ At the beginning of a transient, the PFD acts as a frequency
detector, pushing the VCO frequency toward the input frequency.
After the two are sufficiently close, the PFD operates as a phase

25
Charge Pumps: an Overview
➢ Switches S1 and S2 are controlled by the
inputs “UP” and “Down”, respectively.
➢ A pulse of width ΔT on Up turns S1 on for
ΔT seconds, allowing I1 to charge C1. Vout
goes up by ΔT · I1/C1
➢ Similarly, a pulse on Down yields a drop in
Vout.
➢ If Up and Down are asserted
simultaneously, I1 simply flows through S1
and S2 to I2, creating no change in Vout.

26
Computation of the Transfer Function ➢ Infinite Gain: An arbitrarily
small (constant) phase
difference between A and B still
turns one switch on, thereby
PFD
charging or discharging C1 and
driving Vout toward +∞ or -∞

We can approximate the PFD/CP circuit of figure above as a current source of some average
value driving C1. Calculate the average value of the current source and the output slope for an
input period of Tin.

For an input phase difference of ΔΦ rad = [ΔΦ /(2π)] × Tin

seconds, the average current is equal to Ip ΔΦ /(2π) and
the average slope, Ip ΔΦ /(2π) /C1.

27
Charge-Pump PLL
𝐼𝑃 𝐾𝑉𝐶𝑂
2𝜋𝐶1 𝑠 . 𝑠
𝐻𝑆 =
𝐼𝑃 𝐾𝑉𝐶𝑂
PDF VCO 1 + 2𝜋𝐶 𝑠 . 𝑠
1
𝐼𝑃 𝐾𝑉𝐶𝑂
=
2𝜋𝐶1 𝑠 2 + 𝐼𝑃 𝐾𝑉𝐶𝑂

➢ Such a loop ideally forces the input phase error to zero because a finite
error would lead to an unbounded value fro Vcont.
➢ We will first derive the transfer function of the PFD/CP/C1 cascade.
➢ Called Type-II PLL because its open-loop transfer function contains two
poles at the origin

28
Charge Pump PLLs: First Attempt

PDF

We can approximate this waveform by a ramp --- as if the charge pump continuously injected
current into C1
∆∅𝑜 𝐼𝑝
∆𝑉𝑐𝑜𝑛𝑡 = 𝑇
2𝜋 𝑖𝑛 𝐶1
∆∅𝑜 𝐼𝑝
𝑉𝑐𝑜𝑛𝑡 (t)≈ tu(t)
2𝜋 𝐶1
𝑉𝑐𝑜𝑛𝑡 𝐼
(s) =2𝜋𝐶𝑃 𝑠
∆∅ 1

29
Charge-Pump PLL

PDF VCO

➢ If one of the integrators becomes lossy, the system can be stabilized.

➢ This can be accomplished by inserting a resistor in series with C1. The
resulting circuit is called a “charge pump PLL” (CPPLL)

30
Approximate the pulse sequence by a step of height (IpR1)[ΔΦ0/(2π)]:
∆∅𝑜 𝐼𝑝 ∆∅𝑜 𝐼𝑝
𝑉𝑐𝑜𝑛𝑡 (t)= tu(t)+ 𝑅 u(t)
2𝜋 𝐶1 2𝜋 𝐶1 1 𝐼𝑃 𝐾𝑉𝐶𝑂
𝑅1 𝐶1 𝑠 + 1
𝑉𝑐𝑜𝑛𝑡 𝐼 1
2𝜋𝐶1
(s) = 𝑃 + 𝑅1 𝐻𝑆 =
𝐼 𝐼 𝐾
∆∅ 2𝜋 𝐶1 𝑠 𝑠 2 + 𝑃 𝐾𝑉𝐶𝑂 𝑅1 𝑠 + 𝑃 𝑉𝐶𝑂
2𝜋 2𝜋𝐶1

31
Stability of Charge-Pump PLL
Write the denominator as 𝑠 2 + 2ζωns + ω2𝑛

𝑅 𝐼𝑃 𝐾𝑉𝐶𝑂 𝐶1
ζ= 21 2𝜋

𝐼𝑃 𝐾𝑉𝐶𝑂
𝜔𝑛 =
2𝜋𝐶1
Closed-loop poles are given by
𝜔𝑝1,2 = −ζ ± ζ2 − 1 𝜔𝑛

a closed-loop zero at –ωn / 2ζ

𝑉𝑐𝑜𝑛𝑡 𝐼𝑃 1
(s) = + 𝑅1
∆∅ 2𝜋 𝐶1 𝑠
32
Integer-N Frequency Synthesizers
• Why do we need frequency synthesizers?
÷𝐾 PFD ➢ The VCO frequency High (GHz Range)
/CP ➢ The practical references (MHz Range) -> the limitation of
crystals.
➢ The VCO frequency → Tunable; Reference is not
÷𝑁
𝑁𝑓𝑅𝐸𝐹
𝑓𝑂𝑈𝑇 = = 𝑁𝑓𝐶ℎ𝑎𝑛𝑛𝑒𝑙
𝐾

Required channel spacing

33
The Bode plot of the open-loop gain G(s) as well as the PLL closed-loop transfer function H(s)

ωz ωu
34
Noise Sources in Synthesizer

35
 Phase Noise
Assuming a simple RC loop filter, the transfer function follows
as
𝑁𝜔𝑛 2 1+𝑅𝐶𝑠
2
𝑆 2 +2𝜁𝜔𝑛 𝑠+𝜔𝑛

and the two poles of the transfer function (assuming

overdamped function) are given by
𝜔𝑃1,2 = 𝜔𝑛 𝜁 ± 𝜁 2 − 1

Synthesizer typical noise contributors Frequency Offset

36
Fractional-N Frequency Synthesizers PFD
/CP
• The integer-N synthesizers have a major drawback: the reference frequency
cannot be higher than the channel spacing.
• This, in turn, sets the upper bound of the loop bandwidth, which causes several
implications: ÷N/N+1
– The size of the loop filter capacitors and resistors
– Synthesizer settling time
– Close-in and far-out phase noise
𝑀𝑜𝑑𝑢𝑙𝑢𝑠
– Ability to work with any arbitrary crystal frequency
Control
– Reference spurs, and the amount of filtering they could be subject to

37
 • The main drawback of the simple approach outlined in Figure is
÷N the creation of fractional spurs.
• Hypothetical example of dividing by N for three cycles, and by N+1
for the fourth cycle.
REF • Now, assume the PLL feedback loop forces the output steady-
state frequency to be
DIV 1
𝑓𝑂𝑈𝑇 = 𝑓𝑅𝐸𝐹 𝑁 +
𝐾
U
• Where fREF is the reference frequency and K=4.
D • For the first three cycles of dividing by N, the divider frequency is

1
𝑓𝑅𝐸𝐹 𝑁 + 𝐾
VCTRL 𝑓𝐷𝐼𝑉 = > 𝑓𝑅𝐸𝐹
𝑁

• Thus, the PFD starts to generate down pulses to slow down the VCO, which in turn causes the
control voltage to reduce
• On the 4th cycle, the VCO is divided by N+1, resulting in the divider output to be slower than the
reference, and hence, an up signal is created that raises the control voltage.
• This pattern repeats every K = 4 cycles, leading to the VCO being modulated by a periodic signal
with a period of fREF/K =α.fREF, creating sidebands at α.fREF, and its harmonics.

38
Noise Shaping
• One very common and elegant technique to deal with fractional spurs is exploiting the noise shaping
concept widely used in data converters.
• The periodicity of the control voltage could be broken if the divider modulus is randomly selected
between N and N+1, but still maintains the desired average value.
• The deterministic fractional spurs appearing as tones will be converted to noise spreading around the
VCO signal, with the total energy remaining the same.
• relation between the divider and output frequencies as
𝑓𝑜𝑢𝑡
𝑓𝑂𝑈𝑇 = where b(t) is a random stream of 0s and 1s with an average value of α.
𝑁+𝑏 𝑡 q(t) additive quantization noise

𝑏 𝑡 = α+q(t)

𝑓𝑜𝑢𝑡 𝑓𝑜𝑢𝑡 /(𝑁 + α ) 𝑞 𝑡

𝑓𝐷𝐼𝑉 = = ≅ 𝑓𝐷𝐼𝑉,𝑛𝑜𝑟𝑚 1 −
𝑁 + α+ q(t) 𝑞 𝑡 𝑁𝑛𝑜𝑟𝑚
1+
𝑁+α

39
40
Frequency Dividers
• common circuit ideas to realize these dividers: Latches and D Flip-Flops

Analog current-mode latch

Schematic of a static CMOS latch Dynamic CMOS latch

41
D flip-flop formed with two back-to-back latches Dynamic CMOS flip-flop

42
Divide by 2 using a toggle flip-flop (flip-flop in a feedback loop)

Speed concerns in a divide-by-2 circuit IN

Clk L1 OUT
CK
L2 OUT
L1 OUT
L2 OUT

• For the divider to function properly, the delay of one latch must be less
than half the input signal period as depicted in the above Figure
• Once the input goes high, the first latch is transparent, and its input is
expected to go up, but with some delay in practice (Δ1 in the figure). This
signal must be ready before the second latch becomes transparent, which
is when the input goes back low, or else the divider fails

43
Dual-mode Dividers
• With the D flip-flops used as the main building block, and with a few simple gates, we can construct the
dual- or multi-modulus dividers needed in the synthesizer design.
• As a simple rule of thumb, to create a certain divide ratio, n, the number of latches needed is usually
chosen such that 2n is the closest integer larger than the desired divide ratio, e.g., two latches for a
divide-by-3, or three latches for a divide-by-5, or 6.
An example of a divide-by-2/3 circuit and the corresponding timing
diagram

IN
Q1
A1
Q2

44
Multi-mode Dividers
• The dual-modulus dividers presented
÷2/3 ÷2/3 ÷2/3 earlier are not directly usable in integer or
MOD MOD MOD fractional synthesizers, given that typically
much larger divide ratios are needed.
• They can, however, be used to create
programmable multi-modulus dividers.

IN IN
Q1 Q3
Q2 Out
Q3

• Programmable multi-modulus divider (MMD) consisting of several divide-

by-2/3 stages presented earlier. By choosing the 3-bit programming word,
M2M1M0, a programmable divide ratio of 8 to 15 can be achieved.

45
Introduction to Digital PLLs
• Limitations of the analog PLLs
– Depending on the noise requirements and the reference frequency, the loop filter size can become large.
– While the capacitors scale with technology, their size still does not reduce as favourably as the digital gates.
– A large charge pump current is often required to achieve a low in-band phase noise.
– PFD/CP linearity could be a concern for certain applications.
– There is an important trade-off between the noise contribution of the PLL building blocks, particularly the VCO
and the ΔΣ modulator.

Digital
PFD/CP TDC LF

MMD MMD

46
Time-to-Digital Converters
• The TDC may be thought of an
ADC except for its input is time
rather than voltage. As such, the
TDC creates some quantization
noise that will ultimately limit the
overall PLL phase noise.
Decoder

A
A1
A2
A3
B

47
DPLL Linear Analysis
• The DPLL linear transfer function and noise analysis may be carried out much the same
way as the analog PLLs
• Replacing KPFD with KTDC, and KVCO with KDCO, the same equations as before may be used
with the PLL closed-loop transfer function expressed as

𝑁𝜔𝑛2 1 + 𝑅𝐶𝑠
𝐻 𝑠 = 2
𝑆 + 2𝜁𝜔𝑛 𝑠 + 𝜔𝑛2

𝐾𝑇𝐷𝐶 𝐾𝐷𝐶𝑂 𝑅𝐶𝜔𝑛

𝑤ℎ𝑒𝑟𝑒 𝜔𝑛 = 𝑎𝑛𝑑 𝜁 =
𝐶𝑁 2

48
49