AN INDUSTRY ORIENTED MINI PROJECT ON

“ SUBWAY AUTOMATIC TICKET BOOKING SYSTEM

USING VERILOG HDL”

Submitted in partial fulfilment of the requirement for the award of the Degree of
BACHELOR OF TECHNOLOGY
Submitted to

Jawaharlal Nehru Technological University Hyderabad, Hyderabad

Submitted
By
B. SWATHIKA 236B5A0402
TAMKEEN 226B1A04B3
T. AKSHARA 226B1A04B4
V.RISHITHA 226B1A04C2
P. SANTHOSHI 236B5A0411
Under the Esteemed Guidance of
Mrs. K. UMADEVI
M. Tech
Asst. Prof.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

KAKATIYA INSTITUTE OF TECHNOLOGY AND SCIENCE FOR WOMEN
MANIKBHANDAR, NIZAMABAD, 503003
Approved by AICTE and Affiliated to JNTUH.
(2022-2026)
 KAKATIYA INSTITUTE OF TECHNOLOGY & SCIENCE FOR WOMEN
Approved by AICTE and affiliated to JNTUH-Hyderabad.

Manikbhandar, Nizamabad-503003. Ph:08462-281077

Date:

CERTIFICATE

This is to certify that the Industry Oriented Mini Project entitled

“SUBWAY AUTOMATIC TICKET BOOKING SYSTEM USING
VERILOG HDL ’’ is a record of bonafied work carried out by B.
SWATHIKA (236B5A0402), TAMKEEN (226B1A04B3) , T. AKSHARA
(226B1A04B4) ,V. RISHITHA (226B1A04C2) , P. SANTHOSHI
(236B51A0411) students of B. Tech, under our supervision and guidance in
partial fulfilment for the award of Bachelor of Technology in Electronics and
Communication Engineering during the academic year 2024-2025.

PROJECT GUIDE HEAD OF THE DEPARTMENT

Mrs. K. UMADEVI, Mr. M.MAHIPAL,

M. Tech M. Tech
Asst. Prof. Dept. of ECE.

PRINCIPAL

Dr. S. SELVAKUMAR RAJA

M.E, Ph. D
EXAMINERS:
1.
2.
 ACKNOWLEDGEMENT
We would like to express our sincere gratitude to our guide Mrs. K. UMADEVI , of
Electronics and Communication Engineering. KITSW who extended her unconditional
support and spared her valuable time with her patience and valuable suggestions during the
project. We also extend our special thanks for the encouragement and constant supervision
throughout the project.

We would like to wish to give special vote of thanks to HOD, Mr. M. MAHIPAL ,
M. Tech, ECE Dept. KITSW, for his unique way of inspiring students through clarity of
thoughts, Enthusiasm and care. His constant encouragement and assistance were very helpful
and made our effort a success.

We also grateful to Dr. S. SELVAKUMAR RAJA, M.E., Ph.D. Principal, KITSW,

for providing us with the facilities and resources required for the successful completion of our
industry oriented mini project. We even thank him for his valuable suggestions at that time of
seminars which encouraged us to give our best in industry oriented mini project.

We would also like to thank our faculty and supporting staff of Electronics and
Communications Engineering Department and all other departments for their kind
cooperation directly or indirectly in making the industry oriented mini project successful.

Finally, we want to deeply acknowledge all our friends and family members who
have encouraged us during the preparation of our Industry Oriented Mini Project.

By

B. SWATHIKA (236B5A0402)

TAMKEEN (226B1A04B3)

T. AKSHARA (226B1A04B4)

V.RISHITHA (226B1A04C2)

P. SANTHOSHI (236B5A0411)
 DECLARATION

We B.SWATHIKA (236B5A0402),TAMKEEN (226B1A04B3) ,T.AKSHARA

(226B1A04B4) ,V.RISHITHA (226B1A04C2) ,P.SANTHOSHI (236B5A0411) there by
declare that is industry oriented mini project as been carried out entirely under the esteemed
guidance of Mrs. K. UMADEVI ,for all partial fulfilment of the award of the degree of B.
Tech in Electronics And Communication Engineering at Kakatiya Institute of Technology
and Science For Women, Manikbhandar, Nizamabad, Affiliated to JNTU and further it has
not been submitted to any other university or institutions for the award of any other degree.

By

B. SWATHIKA 236B5A0402
TAMKEEN 226B1A04B3
T. AKSHARA 226B1A04B4
V.RISHITHA 226B1A04C2
P. SANTHOSHI 236B5A0411
 ABSTRACT

In modern urban transport systems, efficiency, security, and automation are crucial for
improving commuter experience and reducing human dependency. Traditional ticketing
systems often face challenges like long queues, manual errors, and limited scalability. To
address these issues, an automated and intelligent solution is required that ensures fast, reliable,
and secure ticket processing.

This project presents the design and implementation of a Subway Automatic Ticket
Booking System using Verilog HDL, targeted for deployment on an FPGA using Xilinx
Vivado. The system is designed for efficiency, automation, and real-time performance in
intelligent transport environments.

Key features of the system include:

• Simulated smart card (RFID) input for user identification and balance retrieval

• Dynamic fare calculation based on source/destination and peak-hour detection

• Top-up capability for low-balance scenarios

• FSM-based transaction control with modular Verilog design

• Simulation of real-time behaviour with clear visual output through waveform monitoring

The FSM ensures reliable transitions across all operating conditions such as
valid/invalid cards, balance sufficiency, and top-up interaction. The system is entirely written
in synthesizable Verilog, structured for VLSI implementation, and tested through waveform
analysis to confirm correct ticket generation and logic behaviour.

This hardware-driven approach demonstrates how FSMs and HDL design can
efficiently replace traditional software ticketing methods in embedded transit systems, with a
strong focus on speed, security, and scalability.
 INDEX

CONTENTS PAGE NO
LIST OF FIGURES i
LIST OF ABBREVATIONS ii
CHAPTER-1
INTRODUCTION TO PROJECT 1
CHAPTER-2
LITERATURE SURVEY 2
CHAPTER-3
PROJECT DESCRIPTION 3-9
3.1 EXISTING SYSTEM 3-4
3.2 PROPOSED SYSTEM 4-7
3.2.1 SYSTEM OVERVIEW 4
3.2.2 FLOW DIAGRAM EXPLANATION 5
3.2.3 STATE DIAGRAM 5-7

CHAPTER-4
VLSI 8-9
4.1 INTRODUCTION 8
4.2 STRUCTURED DESIGN 8
4.3 CHALLENGES 9

CHAPTER-5
SOFTWARE AND LANGUAGE DESCRIPTION 10-22
5.1 DESIGN FLOW USING VIVADO IDE 10-21
5.2 VERILOG 22
CHAPTER-6
RESULTS 23-26
6.1 SIMULATION RESULT 23-24
6.2 RTL SCHEMATIC 24-25
6.3 AREA REPORT 25
6.4 POWER REPORT 26

CHAPTER-7
ADVANTAGES & APPLICATIONS 27-28
7.1 ADVANTAGES 27
7.2 DISADVANTAGES 27

7.3 APPLICATIONS 28

CHAPTER-8
CONCLUSION AND FUTURE SCOPE 29-30
8.1 CONCLUSION 29
8.2 FUTURE SCOPE 30

BIBILOGRAPHY 31
5.2 LIST OF FIGURES

Fig no. Name of the figure Pag no.

3.1 Block Diagram 5
3.2 State Diagram 6
6.1 Simulation Result Subway Automatic Ticket
Booking Showing Ticket No top-up required 23

6.2 Simulation Result Subway Automatic Ticket

Booking insufficient balance top-up done
ticket issued 23
6.3 Simulation Result Subway Automatic Ticket
Booking Showing invalid card Ticket
not issued 24
6.4 Schematic Subway Automatic Ticket System 24
6.5 Schematic Balance Checking Module 24
6.6 Schematic Balance Fare Calculation 25
6.7 Schematic Balance Control 25
6.8 Utilization Report Subway Automatic Ticket
system Timing Report 25
6.9 Max Delay path Subway Automatic Ticket
System 26
6.10 Power Summary 27
 LIST OF ABBREVATIONS

1. FPGA : Field Programmable Gate Array

2. FSM : Finite State Machine
3. RFID : Radio Frequency Identification
4. VLSI : Very Large Scale Integration
5. Verilog HDL : Verilog Hardware Description Language
6. RTL : Register Transfer Level

7. IC : Integrated Circuit

8. CMOS : Complementary Metal-Oxide-Semiconductor

9. EDA : Electronic Design Automation
10. DFT : Discrete Fourier Transform
11. GUT : Graphical User Interface
12. SDC : Software Development life Cycle
13. XDC : XinFin Digital Contract
14. TCI : Transport Corporation of India
15. DRC : Design Rule Checks
16. IOT : Internet Of Things
17. JNAO : Journal of Non-linear Analysis and Optimization
18. JARSCT : Journal of Advanced Research Science Communication

And Technology

19. IJATES : International journal of Advanced Technology in

Engineering and Science

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SUBWAY AUTOMATIC TICKET BOOKING SYSTEM USING VERILOG HDL

CHAPTER-1
INTRODUCTION
Urban transportation systems play a vital role in maintaining the pace and efficiency of modern cities.
Among various modes of public transit, the subway is one of the most widely used due to its speed, cost-
effectiveness, and capacity to move large volumes of passengers efficiently. However, the process of
purchasing subway tickets often involves manual operations, software based terminals, or outdated hardware
systems, which may introduce delays, errors, or user inconvenience—particularly during peak hours. To
overcome these issues, automation in the ticketing process has become an essential requirement for modern
smart cities.

This project presents the design and implementation of a Subway Automatic Ticket Booking System
using Verilog Hardware Description Language (HDL), targeted on an FPGA platform using Xilinx
Vivado. The goal is to create a fully hardware-based system that performs essential ticketing operations such
as user identification, fare calculation, balance checking, top-up processing, and ticket issuance—all handled
by a dedicated Finite State Machine (FSM). Unlike software-based approaches that may be prone to lags or
hacking vulnerabilities, a hardware-centric design offers faster processing, reduced latency, and improved
security, making it ideal for embedded transit systems.

The proposed system simulates smart card functionality using RFID input via switches, allowing
passengers to initiate transactions by presenting a 4-bit card ID. Based on the selected source and destination
stations, the system calculates the travel distance and computes the fare dynamically. A notable feature of the
design is the integration of peak hour logic, which automatically adds a surcharge during defined busy hours
(8–11 AM and 5–8 PM).

The FSM manages all transaction states in a sequential, reliable manner. Starting from card reading,
the system transitions to fare evaluation, then checks whether the balance is sufficient. If not, it enters a top-
up state, allowing users to recharge and proceed. Upon success, the FSM triggers a single-cycle ticket
issuance pulse, which ensures that only one ticket is generated per transaction, avoiding duplicate issuance.
This is controlled by precise state-transition logic, demonstrating a fundamental concept of digital system
design—state-controlled hardware flow.The design is fully coded in synthesizable Verilog HDL, following
modular and hierarchical principles suitable for VLSI implementation. Simulation and testing were carried
out using Vivado’ behavioural and waveform analysis tools, confirming the correctness and efficiency of the
system.

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CHAPTER-2

LITERATURE SURVEY
By analysing the below-mentioned previous works, it is evident that while several designs of vending
machines, ticketing systems, and other automated embedded platforms have been proposed, there is still
scope for improvement in areas such as real-time fare calculation, smart card integration, state-driven top-up
handling, peak-hour logic, and precise one-cycle control signalling. The proposed project addresses these
aspects by introducing an FSM-based Subway Automatic Ticket Booking System designed using Verilog
HDL, focusing on sequential state logic, secure single-pulse ticket generation, top-up handling, time-sensitive
pricing, and RTL simulation for FPGA-based deployment.

1. Paper Title: "Finite State Machine Based Vending Machine Controller with Auto-Billing
Features" (2012) -- Authors: Ana Monga, Balwinder Singh

o Summary: This paper presents a vending machine design using FSM principles to support

automatic billing. While it emphasizes FSM structure and basic vending flow, it lacks advanced
timing-based pricing logic and does not explore FPGA synthesis or secure transaction features.

2. Paper Title: "RFID-Based Ticketing for Public Transport System: Perspective Megacity Dhaka"
(2010) -- Authors: Md. Foisal Mahedi Hasan et al.

o Summary: Focuses on the concept of RFID-based ticketing in mass transit systems. It discusses

RFID authentication and system-level design but does not detail the FSM or hardware-level
implementation. Verilog and FPGA design aspects are not explained.

3.Paper Title: "Bus Management System Using RFID in WSN"(2010) –

Authors: Ben Ammar, Hatem Hamam, Habib

o Summary: This work proposes a wireless RFID and sensor network for bus ticketing and

management. It is conceptually aligned with user tracking and ticket validation but doesn't
address fare logic or hardware-based FSM design for automation.

4. Paper Title: "Implementation of an Intelligent Vending Machine using Verilog on

FPGA" -- Authors: Journal of Embedded Systems and Applications

o Summary: Describes a vending machine using Verilog HDL simulated on FPGA. It includes

FSM control for multiple products, but doesn't include external timing based variables .

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CHAPTER-3

PROJECT DESCRIPTION
3.1 EXISTING SYSTEM:
In most metropolitan cities, subway ticketing systems are traditionally based on software-driven
architectures running on embedded processors, microcontrollers, or general-purpose computing platforms.
These systems commonly utilize graphical user interfaces (GUIs), touchscreen kiosks, or mobile applications
for user interaction. While such solutions are flexible and user friendly, they rely heavily on operating systems,
backend databases, and networking infrastructure to manage real-time ticket transactions, fare calculations,
and account-based payments.

The most widely deployed existing subway ticketing systems are contactless smart card systems
(e.g., Metro Cards, RFID/NFC-based cards) that interact with centralized servers. These systems validate user
credentials, check balance, deduct fare, and issue a receipt—all in real time. However, these rely on complex
software stacks, cloud-based databases, and sometimes even internet connectivity for fare rules, peak hour
surcharges, or travel zone validations. Additionally, most software-based systems lack true real-time
hardware control, leading to potential delays, system crashes, or vulnerability to tampering.

From a hardware design standpoint, existing ticketing terminals are often treated as black-box
devices, meaning the core logic (such as FSM transitions, fare logic, and ticket verification) is abstracted
away in proprietary code, making it harder to debug or reconfigure. This makes such systems less optimized
in terms of speed, power consumption, and determinism, especially under high user load (e.g., during peak
hours).

Moreover, handling conditions like insufficient balance, top-up requests, and peak-hour fare
differentiation is typically managed via software logic and UI feedback. These systems do not fully utilize
the deterministic benefits of FSM based hardware design, where state transitions can be optimized for real-
time operation. As a result, there is often an overhead of decision-making latency, and the complexity of
managing asynchronous software events can introduce bugs or errors in user transactions.

Finally, many existing systems lack hardware-level simulation and testing at the RTL (Register
Transfer Level). Changes in fare structure or user interface typically require software updates, which may
be costly or time-consuming for public transport agencies to deploy at scale.

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Limitations of the Existing System:

 Heavy reliance on software and central databases
 Slower response time compared to FSM-driven hardware
 Less predictable and potentially less secure in embedded use cases
 No hardware-based fare calculation or state tracking

3.2 PROPOSED SYSTEM:

This project implements an automated subway ticketing system using Verilog HDL, simulating the
functionality of a real-world smart card-based fare collection system. The system uses an RFID-based login
mechanism, fare calculation, balance verification, ticket dispensing, and top-up logic — all orchestrated using
an FSM-based control module.

3.2.1 SYSTEM OVERVIEW:

The system operates around a smart card (RFID) model, where users “tap in” their cards. The RFID
logic identifies the user, verifies card validity, and communicates with the balance check and fare calculation
modules. If sufficient funds are present, the ticket is issued and the fare is deducted; if not, the top-up module
is activated. The ticket_fsm module handles all transitions using a finite state machine.

Key Functional Modules:

1. RFID Logic (rfid_logic.v) – Reads the card ID.
2. Balance Checker (balance_check.v) – Fetches the current card balance.
3. Fare Calculator (fare_calculation.v) – Calculates fare based on destination input.
4. Ticket FSM (ticket_fsm.v) – Manages all system states (select, verify, issue, error).
5. Top-Up Module (topup_module.v) – Allows balance recharging.
6. Main Wrapper (ticket_system.v) – Integrates all submodules.

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Figure 3.1-Block Diagram

3.2.2 FLOW DIAGRAM EXPLANATION

The Flow Diagram represents the sequential operation of the system:

1. Start/Idle o System awaits card tap via RFID.
2. Card Detection o Once a valid RFID is detected, the card ID is passed on for balance
checking.
3. Destination Input o The user selects a destination; the fare is calculated using the
fare_calculation module.
4. Balance Check o The fare is compared against the user’s balance via balance_check.
o If balance ≥ fare → proceed to issue ticket.
o Else → activate top-up module.
5. Top-Up (Optional) o User can top up balance. Once updated, the system retries the
transaction.
6. Ticket Issuance o Ticket is issued, fare is deducted, and user is allowed entry.
7. End/Reset o System resets for the next user.

This modular flow ensures reusability and makes the system scalable for future upgrades like multi-
zone fares or QR code support.

3.2.3 STATE DIAGRAM

The State Diagram represents the sequence of operational states that the subway ticketing system
transitions through during a ticket booking transaction. It is governed by a Finite State Machine (FSM),

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which ensures that the system behaves predictably and logically based on user inputs and internal conditions
(like card balance and fare). The FSM consists of the following major states:

Figure 3.2- State Diagram

1. IDLE
Purpose: The system starts in this state or returns here after completing a transaction.
Behaviour: It waits for an RFID card to be tapped.
Transition Condition: On detecting a valid RFID input, the FSM moves to the READ_CARD state.

2. READ_CARD
Purpose: Reads and verifies the card data from the RFID module.
Behaviour: Captures the user ID and checks for validity.
Transition Condition: If the card is valid, transitions to SELECT_DEST. If not, may return to IDLE
or display an error.

3. SELECT_DEST
Purpose: Waits for the user to select their destination.
Behaviour: Stores the destination input and triggers fare calculation.
Transition Condition: On valid selection, moves to VERIFY_BALANCE.

4. VERIFY_BALANCE
Purpose: Compares the calculated fare with the user’s card balance.
Behaviour: If the balance is enough, the FSM proceeds to issue the ticket.
Transition Conditions:
o Balance ≥ Fare → transition to ISSUE_TICKET. o Balance <
Fare → transition to TOP_UP.

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5. TOP_UP
Purpose: Enables the user to add balance to their card.
Behaviour: Waits for a top-up input. Once the balance is increased, the
System recheck the fair.
Transition Condition: After successful top-up, loops back to VERIFY_BALANCE.

6. ISSUE_TICKET
Purpose: Dispenses the ticket and deducts the fare from the card.

Behaviour: Triggers output signals for ticket generation and updates the stored balance.

Transition Condition: After issuing the ticket, proceeds to DONE.

7. DONE
Purpose: Indicates that the transaction is complete.

Behaviour: Displays confirmation and resets temporary values.

Transition Condition: After a brief delay or reset signal, returns to IDLE to await the next user

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CHAPTER-4
VLSI
4.1 INTRODUCTION TO VLSI:
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining
thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and
communication technologies were being developed. The microprocessor is a VLSI device. Before the
introduction of VLSI technology most ICs had a limited set of functions they could perform. An electronic
circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of these into
one chip.

Digital VLSI circuits are predominantly CMOS based. The way normal blocks like latches and gates
are implemented is different from what students have seen so far, but the behaviour remains the same. All the
miniaturisation involves new things to consider. A lot of thought has to go into actual implementations as well
as design. Let us look at some of the factors involved ...

1. Circuit Delays. Large complicated circuits running at very high frequencies have one big problem to tackle
- the problem of delays in propagation of signals through gates and wires ... even for areas a few micrometers
across! The operation speed is so large that as the delays add up, they can actually become comparable to the
clockspeeds.
2. Power. Another effect of high operation frequencies is increased consumption of power. This has two-fold
effect - devices consume batteries faster, and heat dissipation increases. Coupled with the fact that surface
areas have decreased, heat poses a major threat to the stability of the circuit itself.

3. Layout. Laying out the circuit components is task common to all branches of electronics. What so special
in our case is that there are many possible ways to do this; there can be multiple layers of different materials
on the same silicon, there can be different arrangements of the smaller parts for the same component and so
on.

4.2 STRUCTURED DESIGN:

Structured VLSI design is a modular methodology originated by Carver Mead and Lynn Conway for
saving microchip area by minimizing the interconnect fabrics area. This is obtained by repetitive arrangement
of rectangular macro blocks which can be interconnected using wiring by abutment. An example is

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partitioning the layout of an adder into a row of equal bit slices cells. In complex designs this structuring may
be achieved by hierarchical nesting.

Structured VLSI design had been popular in the early 1980s, but lost its popularity later because of
the advent of placement and routing tools wasting a lot of area by routing, which is tolerated because of the
progress of Moore's Law. When introducing the hardware description language KARL in the mid' 1970s,
Reiner Hartenstein coined the term "structured VLSI design" (originally as "structured LSI design"), echoing
Edger Dijkstra's structured programming approach by procedure nesting to avoid chaotic spaghetti-structured
programs.

4.3 CHALLENGES:

As microprocessors become more complex due to technology scaling, microprocessor designers

have encountered several challenges which force them to think beyond the design plane, and look ahead to
post-silicon:

 Process variation – As photolithography techniques tend closer to the fundamental laws of optics,
achieving high accuracy in doping concentrations and etched wires is becoming more difficult and
prone to errors due to variation. Designers now must simulate across multiple fabrication process
corners before a chip is certified ready for production.

 Stricter design rules – Due to lithography and etch issues with scaling, design rules for layout have
become increasingly stringent. Designers must keep ever more of these rules in mind while laying
out custom circuits. The overhead for custom design is now reaching a tipping point, with many
design houses opting to switch to electronic design automation (EDA) tools to automate their design
process.

 Timing/design closure – As clock frequencies tend to scale up, designers are finding it more
difficult to distribute and maintain low clock skew between these high frequency clocks across the
entire chip. This has led to a rising interest in multicore and multiprocessor architectures, since an
overall speedup can be obtained by lowering the clock frequency and distributing processing.

 First-pass success – As die sizes shrink (due to scaling), and wafer sizes go up (due to lower
manufacturing costs), the number of dies per wafer increases, and the complexity of making suitable
photo masks goes up rapidly. A mask set for a modern technology can cost several million dollars.

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CHAPTER-5
SOFTWARE AND HARDWARE DESCRIPTION
5.1 DESIGN FLOW USING VIVADO® IDE:

Step 1: Creating a Project

Launch Vivado:

1. To launch Vivado, do the following: On Linux:

a. Change to the directory where the lab materials are stored. cd

<Extract_Dir>/Vivado_Tutorial

b. Launch the Vivado IDE.

vivado

On Windows:
a. Before clicking the desktop icon to launch the Vivado tool, configure the icon to
indicate where to write the vivado.log and vivado.jou files.
b. Right-click the Vivado <version> Desktop icon and select Properties from the popup
menu.
c. Under the Shortcut tab, set the Start in value to the extracted Vivado Tutorial directory,
as shown in the following figure:

<Extract_Dir>/Vivado_Tutorial/
d. Click OK to close the Properties dialog box.

e. Double-click the Vivado <version> Desktop icon to start the Vivado IDE.

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Create a New Project:

1. After Vivado opens, select Create Project on the Getting Started page.
2. Click Next in the New Project wizard.
3. Specify the Project Name and Location:

Project name project_bft

Project Location
<Extract_Dir>/Vivado_Tutorial/Tutorial_Created_Data
4. Click Next.

5. Select RTL Project as the Project Type and click Next.

6. Click the button and select Add Files.

a. Browse to <Extract_Dir>/Vivado_Tutorial/Sources/hdl/
b. Press and hold the Ctrl key, and click to select the following files, async_fifo.v, bft.vhdl,
FifoBuffer.v.
c. Click OK to close the File Browser.

7. Click the button and select Add Directories.

a. Select the <Extract_Dir>/Vivado_Tutorial/Sources/hdl/bftLib directory.
b. Click Select.
8. Click the HDL Sources For column for the bft_tb.v file and change Synthesis and Simulation to
Simulation only, as shown in the following figure.

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9. Click in the Library column for the bftLib, and manually edit the value to change it from
xil_defaultlib (or work) to bftLib, as shown in the following figure.
10. Enable the check boxes for Copy sources into project, and Add sources from subdirectories.
11. Set the Target Language to Verilog to define the language of the netlist generated by Vivado
synthesis.
12. Set the Simulator Language to Verilog to define the language required by the logic simulator.
13. Click Next.
14. On the Add Constrai
15. nts Page, click Add Files.
16. Browse to and select <Extract_Dir>/Vivado_Tutorial/Sources/bft_full_kintex7.xdc.
17. Click OK to close the File Browser.
18. Enable the check box for Copy constraints files into project.

19. Click Next to move to the Default Part page.

20. On the Default Part page, click the Family filter and select the Kintex-7 family.

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21. Scroll to the top of the list and select the xc7k70tfbg484-2 part, and click Next.

22. Click Finish to close the New Project Summary page, and create the project.

The Vivado IDE opens project_bft in the default layout.

Step 2: Using the Sources Window and Text Editor

The Vivado tool lets you add different design sources including Verilog, VHDL, EDIF, NGC format
cores, SDC, XDC, DCP design checkpoints, TCI constraints files, and simulation test benches. These files
can be sorted in a variety of ways using the tabs at the bottom of the Sources window (Hierarchy, Libraries,
or Compile Order).

Important: NGC format files are not supported in the Vivado Design Suite for Ultra Scale™ devices.
It is recommended that you regenerate the IP using the Vivado Design Suite IP customization tools with native
output products. Alternatively, you can use the NGC2EDIF command to migrate the NGC file to EDIF format

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for importing. However, Xilinx recommends using native Vivado IP rather than XST-generated NGC format
files going forward.

The Vivado IDE includes a context sensitive text editor to create and develop RTL sources, constraints
files, and TCI scripts. You can also configure the Vivado IDE to use third party text editors. Refer to the
Vivado Design Suite User Guide: Using the Vivado IDE (UG893) for information on configuring the Vivado
tool.

 Explore the Sources Window and Project Summary

1. Examine the information in the Project Summary. More detailed information is presented as the design
progresses through the design flow.
2. Examine the Sources window and expand the Design Sources, Constraints and Simulation Sources
folders.

The Design Sources folder helps keep track of VHDL and Verilog source files and libraries. Notice
the Hierarchy tab displays by default.

3. Select the Libraries tab and the Compile Order tabs in the Sources window and notice the different
ways that sources are listed.

The Libraries tab groups source files by file type. The Compile Order tab shows the file order used
for synthesis.

4. Expand the various folders to view the design source information.

5. Select the Hierarchy tab.

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 Explore the Text Editor

1. Select one of the VHDL sources in the Sources window.

2. Right-click to review the commands available in the popup menu.
3. Select Open File, and use the scroll bar to browse the file contents in the Text Editor.

You can also double-click source files in the Sources window to open them in the Text Editor.

Notice that the Text Editor displays the RTL code with context sensitive colouring of keywords
and comments. The Fonts and Colours used to display reserved words can be configured using the
Tools > Settings command. Refer to Vivado Design Suite User Guide: Using the Vivado IDE (UG893)
for more information.

4. With the cursor in the Text Editor, right-click and select Find in Files. Note the Replace in Files
command as well.

The Find in Files dialog box opens with various search options.

5. Enter clock in the Find what: field, and click Find.

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The Find in Files window displays in the messaging area at the bottom of the Vivado IDE.

6. In the Find in Files window, expand one of the displayed files, and select an occurrence of clock in
the file.

Notice that the Text Editor opens the selected file and displays the selected occurrence of clock in
the file.

7. Close the Find in Files – Occurrences window.

8. Close the open Text Editor windows.

The next few steps highlight some of the design configuration and analysis features available prior
to running synthesis.

Step 3: Elaborating the RTL Design

The Vivado IDE includes an RTL analysis and IP customizing environment. There are also several
RTL Design Rule Checks (DRCs) to examine ways to improve performance or power on the RTL design.

1. Select Open Elaborated Design in the Flow Navigator to elaborate the design.

Tip: A dialog box appears informing you that your current settings will slow down netlist
elaboration. You can click OK to continue or Cancel to return to your project and edit your
Elaboration Settings, available in the Flow Navigator.

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2. Ensure that the Layout Selector pull down menu in the main Toolbar has Default Layout selected.

The Elaborated Design enables various analysis views including an RTL Netlist, Schematic, and
Graphical Hierarchy. The views have a cross-select feature, which helps you to debug and optimize the RTL.

3. Explore the logic hierarchy in the RTL Netlist window and examine the Schematic.

You can traverse the schematic by double-clicking on cells to push into the hierarchy, or by using
commands like the Expand Cone or Expand/Collapse from the Schematic popup menu. Refer to the
Vivado Design Suite User Guide: Using the Vivado IDE (UG893) for more information on using the
Schematic window.

4. Select any logic instance in the Schematic and right-click to select the Go to Source or Go to Definition
commands.

The Text Editor opens the RTL source file for the selected cell with the logic instance highlighted. In
the case of the Go to Definition command, the RTL source file containing the module definition is
opened. With Go to Source, the RTL source containing the instance of the selected cell is opened.

5. Click the Messages window at the bottom of the Vivado IDE, and examine the messages.
6. Click the Collapse All button in the Messages toolbar.
7. Expand the Elaborated Design and the synth_design -rtl -name rtl_1 messages.

Notice there are links in the messages to open the RTL source files associated with a message.
8. Click one of the links and the Text Editor opens the RTL source file with the relevant line
highlighted.
9. Close the Text Editor windows.
10. Close the Elaborated Design by clicking on the X on the right side of the Elaborated Design window
banner, and click OK to confirm.

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Step 4: Using the IP Catalog

The Xilinx IP Catalog provides access to the Vivado IP configuration and generation features. You
can sort and search the Catalog in a variety of ways. IP can be customized, generated, and instantiated.

1. Click the IP Catalog button in the Flow Navigator, under Project Manager.
2. Browse the IP Catalog to examine the various categories and IP filtering capabilities.
3. Click the Group by taxonomy and repository icon and notice the selection to Group by taxonomy and
Group by repository.
4. Expand the Basic Elements folder.
5. Double-click DSP48 Macro.Click Cancel to close the Customize IP dialog without adding the IP to
the current design.

6. Close the IP Catalog tab by clicking on the X on the window tab.

Step 5: Running Behavioural Simulation

The Vivado IDE integrates the Vivado Simulator, which enables you to add and manage simulation
sources in the project. You can configure simulation options, and create and manage simulation source sets.
You can run behavioral simulation on RTL sources, prior to synthesis.

1. In the Flow Navigator, under Project Manager, click the Settings command. The Settings dialog box
opens with Project Settings at the top, and Tool Settings below that.

2. Examine the settings available on the Simulation page, then click Cancel to close the dialog box.

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3. Click the Run Simulation command in the Flow Navigator, then click the Run Behavioral
Simulation in the sub-menu.
4. Examine and explore the Simulation environment. Simulation is covered in detail in the Vivado Design
Suite User Guide: Logic Simulation (UG900) and the Vivado Design Suite Tutorial: Logic Simulation
(UG937).
5. Close the simulation by clicking the X icon on the Behavioral Simulation view banner.
6. Click OK to close the Simulation window and click No if prompted to save changes.

Step 6: Reviewing Design Run Settings

One of the main differences between the Non-Project mode you used in Lab #1 and the Project mode,
which you are now using, is the support of design runs for synthesis and implementation. Non-Project mode
does not support design runs.
Design runs are a way of configuring and storing the many options available in the different steps of
the synthesis and implementation process. You can configure these options and save the configurations as
strategies to be used in future runs. Before launching the synthesis and implementation runs you will review
the settings and strategies for these runs.

In the Flow Navigator, under Project Manager, click the Settings command. The Settings dialog box opens.

1. Select the Synthesis page under Project Settings.

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2. The Synthesis Settings provide you access to the many options available for configuring Vivado
synthesis. For a complete description of these options, see the Vivado Design Suite User Guide:
Synthesis (UG901).

3. After reviewing the various synthesis options, select the Implementation page on the left side of the
Settings dialog box, as shown in the following figure.

The Settings change to reflect the Implementation settings. You can view the available options for
implementation runs. For a complete description of these options, see the Vivado Design Suite User
Guide: Implementation (UG904).

4. Click Cancel to close the Settings dialog box.

You are now ready to launch Vivado synthesis and implementation.

Step 7: Synthesizing and Implementing the Design

After configuring the synthesis and implementation run options, you can:
Use the Run Synthesis command to run only synthesis.
Use the Run Implementation command, which will first run synthesis if it has not been run and then
run implementation.

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Use the Generate Bitstream command, which will first run synthesis, then run implementation if they
have not been run, and then write the bitstream for programming the Xilinx device.

For this tutorial, run these steps one at a time.

1. In the Flow Navigator, click the Run Synthesis button.

2. Click OK to launch Synthesis with the default options and wait for the task to complete.

Notice the progress bar in the upper-right corner of the Vivado IDE, indicating the run is in progress.
While the synthesis process is running in the background, you can continue browsing Vivado IDE
windows, run reports, and further evaluate the design.After synthesis has completed, the Synthesis
Completed dialog box prompts you to choose the next step.

3. Select Run Implementation, and click OK.

4. Click OK to launch Implementation with the default options and wait for the task to complete.

5. The implementation process is launched, and placed into a background process after some
initialization. The next step in this tutorial shows you how to perform design analysis of the
synthesized design while waiting for implementation to complete.

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5.2 VERILOG
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model
electronic systems. It is most commonly used in the design and verification of digital circuits at the register-
transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits.

Hardware description languages such as Verilog differ from software programming languages because
they include ways of describing the propagation time and signal strengths (sensitivity). There are two types
of assignment operators; a blocking assignment (=), and a non-blocking (<=) assignment. The non-blocking
assignment allows designers to describe a state-machine update without needing to declare and use temporary
storage variables. Since these concepts are part of Verilog's language semantics, designers could quickly write
descriptions of large circuits in a relatively compact and concise form. At the time of Verilog's introduction
(1984), Verilog represented a tremendous productivity improvement for circuit designers who were already
using graphical schematic capture software and specially written software programs to document and simulate
electronic circuits.

A Verilog design consists of a hierarchy of modules. Modules encapsulate design hierarchy, and
communicate with other modules through a set of declared input, output, and bidirectional ports. Internally, a
module can contain any combination of the following: net/variable declarations (wire, reg, integer, etc.),
concurrent and sequential statement blocks, and instances of other modules (sub-hierarchies). Sequential
statements are placed inside a begin/end block and executed in sequential order within the block. However,
the blocks themselves are executed concurrently, making Verilog a dataflow language.

The module is the basic unit of hierarchy in Verilog

 Modules describe:
o boundaries [module, end module]
o inputs and outputs [ports]
o how it works [behavioral or RTL code]
 Can be a single element or collection of lower level modules
 Module can describe a hierarchical design (a module of modules)
 A module should be contained within one file
 Module name should match the file name
 Module fadder resides in file named fadder.sv
 Multiple modules can reside within one file (not recommended)
 Correct partitioning a design into modules is critical.

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CHAPTER-6

RESULTS
6.1 SIMULATION RESULTS:

Figure 6.1- Simulation Result Subway Automatic Ticket Booking Showing Ticket

Issuance no top-up required

Figure6.2- Simulation Result Subway Automatic Ticket Booking Showing Insufficient balance,

top up done Ticket Issued

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Figure 6.3- Simulation Result Subway Automatic Ticket Booking Showing Invalid card
Ticket not Issued
6.2 RTL SCHEMATIC:
SSCHEMATIC

Figure 6.4- Schematic Subway Automatic Ticket System

Figure 6.5- Schematic Balance Checking Module

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Figure 6.6- Schematic Balance fare calculation

Figure 6.7- Schematic Balance Control

FSM
6.3 AREA REPORT:

Figure 6.8- Utilization Report Subway Automatic Ticket System Timing Report

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Figure 6.9- Max Delay Path Subway Automatic Ticket System

6.4 POWER REPORTS:

Figure 6.10- Power Summary

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CHAPTER-7
ADVANTAGES & APPLICATIONS
7.1 ADVANTAGES:

1.Deterministic and Sequential Ticket Processing: By leveraging a Finite State Machine (FSM)
architecture, the system ensures clearly defined and deterministic transitions across stages such as smart card
input, fare evaluation, balance verification, top-up handling, and ticket generation.

2.Hardware-Based Real-Time Performance : Implementing the entire ticketing system using Verilog HDL
enables synthesis onto FPGA hardware, offering a significant performance boost over traditional software
based solutions. User inputs, fare calculations, and ticket issuance are handled with real-time responsiveness,
eliminating delays associated with operating systems or software queues.

3.Dynamic Fare Calculation with Peak-Hour Handling: A key feature of the system is its ability to
dynamically compute fare based on source and destination stations, while also accounting for peak-hour
surcharges.

4.Smart Card Simulation and Balance Management: The design integrates simulated RFID smart card
functionality, allowing balance retrieval, fare deduction, and top-up features.

5.Single-Cycle Ticket Issuance Control: The system introduces a refined logic mechanism that ensures
Ticket_issued is pulsed for exactly one clock cycle per transaction. This prevents duplicate ticket printing and
represents best practices in control signal timing and FSM synchronization, improving reliability in hardware-
based systems.

7.2 DISADVANTAGES:
1. Not Suited for High-Level Logic or User Interfaces: Verilog is low-level and lacks native support for
high-level programming features (e.g., GUIs, databases, networking).

2. Poor Scalability and Maintainability: Making changes or adding features (like route updates, payment
options) in Verilog is cumbersome compared to high-level languages. Debugging and maintaining such
systems would require specialized knowledge in digital logic design.

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7.3 APPLICATIONS:
1. Smart Public Transport Automation: By implementing FSM-driven logic in Verilog HDL, the
system offers a structured and real-time solution for automated subway ticketing. It ensures accurate
fare handling, balance validation, and single-ticket issuance, making it ideal for metro stations, urban
rail networks, and airport shuttle systems that require quick, autonomous ticket processing.

2. Cost-Effective Embedded Ticketing Solutions: The Verilog-based design can be synthesized on

low-cost FPGA hardware, reducing dependency on complex software stacks and expensive controller
systems. This makes it a highly affordable ticketing alternative for small-city metros, local train
services, or private shuttle operations with limited budgets.

3. Peak-Hour Pricing and Dynamic Fare Modelling: The hardware design supports time-sensitive fare
adjustment (peak vs non-peak hours), which can be applied in metropolitan ticketing systems to
implement real world pricing strategies. This makes the project adaptable for zone-based travel cost
schemes, crowd management, and incentive-driven transport models.

4. Educational Tool for Digital Design and FSM Training: This project provides a real-world
embedded system case study suitable for digital design, Verilog HDL, and FSM-based control logic
training. It is ideal for academic labs, engineering coursework, and VLSI/FPGA training programs to
demonstrate the application of HDL in solving practical urban infrastructure problems.

5. Reprogrammable Smart Card-Based Kiosk Systems: The project’s architecture supports simulated
RFID-based input and can be extended to integrate actual smart card readers. This makes it suitable
for use in smart kiosk systems in subways, buses, or even in university campuses, where
reprogrammable, autonomous ticketing solutions are required.

In summary, this project provides a robust, programmable, and adaptable solution for modern ticketing
automation using Verilog HDL. Its application spans both academic and practical domains—enabling low-
cost public infrastructure enhancement, while also offering a strong platform for learning, simulation, and
real-world implementation of hardware-based control systems in urban transport.

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CHAPTER-8

CONCLUSION AND FUTURE SCOPE

8.1 CONCLUSION:
The project “Subway Automatic Ticket Booking System using Verilog HDL” successfully
demonstrates the design and simulation of a fully functional, hardware-based ticketing system for
public transportation, using Verilog HDL and FSM-based architecture. By implementing key modules
such as smart card simulation, dynamic fare calculation, peak-hour pricing, balance verification, and
top-up logic, the system reflects the core requirements of a real-world metro ticketing solution.

The use of a Finite State Machine (FSM) enabled the design to maintain clear state transitions
and deterministic behaviour across all user interactions. The incorporation of a single-cycle ticket
issuance signal ensured that ticket generation was precise and non-repetitive—an essential
requirement for real-time embedded systems. The modular nature of the Verilog code allowed for
isolated simulation, testing, and verification of each functional block, reinforcing good digital design
practices.

Simulation was performed using Xilinx Vivado, validating various scenarios such as valid and
invalid card IDs, sufficient and insufficient balances, and both peak and off-peak fare conditions.
Through waveform analysis, it was confirmed that the system performed accurately in each of these
scenarios. The design also ensured that users with low balances could enter a top-up mode before
continuing with the transaction, reflecting real-world usability.

In conclusion, the project successfully meets its objectives by delivering a cost-effective,

reprogrammable, and scalable embedded system for subway ticket booking. It paves the way for future
enhancements such as actual RFID reader integration, multilingual user interfaces, touchscreen
support, mobile payment options, or IoT-based monitoring—all of which can be incrementally added
to the existing Verilog HDL framework. This work stands as a compelling demonstration of how
digital design and FSM logic can be harnessed to build smart, real-time urban solutions.

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8.2 FUTURE SCOPE:

The future scope of the project “Subway Automatic Ticket Booking System using Verilog HDL” opens
up multiple avenues for enhancement, real-time deployment, and advanced integration in the domains of
intelligent transport systems, embedded control, and digital fare automation.

1. Integration with IoT for Remote Ticketing and Monitoring

Future versions of the system can be enhanced with Internet of Things (IoT) technology to allow centralized
monitoring of ticket sales, system status, and peak-time usage patterns. Operators could remotely update fare
rules, access transaction logs, and monitor card usage statistics from a web dashboard or cloud-based control
center.

2. Support for Actual RFID Smart Cards and Secure Payment Gateways

The current RFID logic can be extended to support real-world RFID/NFC smart cards, allowing authenticated
user access and secure fare deductions. Integration with cashless payment platforms (e.g., UPI, QR codes,
mobile wallets) would enable contactless transactions and align the system with modern transit standards.

3. Zone-Based Fare and Route Planning Extensions

The FSM logic can be scaled to support multi-zone pricing, line interchanges, and real-time route planning.
This would allow users to calculate and pay fares for complex journeys involving transfers, zones, or multiple
transit modes, just like advanced metro systems in global cities.

4. Deployment on FPGA Hardware for Real-Time Implementation

While the current project is simulated in Vivado, a key next step is full FPGA implementation and testing on
real hardware. This will validate the system’s behaviour under real-world timing conditions and assess power
consumption, I/O performance, and hardware robustness before deployment in kiosks.

5. Integration with Central Ticketing Servers and Smart City Platforms

The system can be made compatible with backend transport management servers, enabling synchronization
with mobile apps, ticket history, travel passes, or loyalty systems. This would support seamless travel across
bus, rail, and metro networks as part of smart city infrastructure.

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BIBLIOGRAPHY
1. R. Mahalaxmi, D. Lochana, K. Sai, D. Sri Durga Devi, & G. Sai Arjun Chowdary, “Design and Implement
Subway Automatic Ticketing System with Enhanced Display Features,” Journal of Nonlinear Analysis
and Optimization (JNAO), vol. 15, no. 1, pp. 2121–2123, 2024.

2. Authors not specified, “Subway Automatic Ticket Booking System using Verilog,” International Journal
of Advanced Research in Science, Communication and Technology (IJARSCT), vol. 3, no. 2, pp. 606–
610, December 2023.

3. Authors not specified, “Design and Implementation of Subway Automatic Ticketing System Based on
Verilog HDL,” Take off Projects, Project Code: TVMAFE520, 2023.

4. Authors not specified, “Design and Simulation of an Automated Subway Ticketing System,” Eudoxus
Press, vol. 1, no. 1, pp. 1–5, 2024.

5. Basavaraj Police Patil D, Mahesh B Shetkar, & Rajesh C, “Design of Electronic Ticketing Machine Using
Verilog,” International Journal of Advanced Technology in Engineering and Science (IJATES), vol. 5, no.
3, pp. 222–224, 2017.

6. Authors not specified, “Design and Implementation of Bus Ticketing System Using Verilog HDL,”
ResearchGate, 2024.

7. Authors not specified, “Verilog-Based Automatic Bus Ticketing System: Abstract,” Scribd, 2024.

8. Authors not specified, “SUBWAY Final Index 1,” Scribd, 2024.

9. Authors not specified, “System Verilog-FSM/ticket-machine/verilog/TicketMachine.v,” GitHub

Repository, 2024.

10. Authors not specified, “Design of Electronic Ticketing Machine Using Verilog,” Conference World,
pp.516–520, 2024.

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