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Analog System Design (ELE 2151) RCS

This document outlines the exam structure and questions for the III Semester B.Tech in Electrical & Electronics Engineering, specifically for the Analog System Design course. It includes various technical problems related to MOS fabrication, amplifier design, and circuit analysis, requiring calculations and circuit diagrams. The exam is scheduled for December 16, 2022, with a total of 50 marks and specific instructions for candidates.

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Abhinand K
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23 views3 pages

Analog System Design (ELE 2151) RCS

This document outlines the exam structure and questions for the III Semester B.Tech in Electrical & Electronics Engineering, specifically for the Analog System Design course. It includes various technical problems related to MOS fabrication, amplifier design, and circuit analysis, requiring calculations and circuit diagrams. The exam is scheduled for December 16, 2022, with a total of 50 marks and specific instructions for candidates.

Uploaded by

Abhinand K
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Reg. No.

III SEMESTER B.TECH (ELECTRICAL & ELECTRONICS ENGINEERING)

END SEMESTER EXAMINATIONS, DECEMBER 2022


ANALOG SYSTEM DESIGN [ELE2151]
REVISED CREDIT SYSTEM

Time: 3 Hours Date: 16 December 2022 Max. Marks: 50


Instructions to Candidates:
❖ Answer ALL the questions.
❖ Missing data may be suitably assumed.
❖ Steps must be clearly shown

Q1A A MOS is being fabricated with, tox=8 nm, 𝞵n= 450 cm2/V ox=34.53*10-12, (W/L) = 8 𝞵m/0.8
𝞵m and Vth = 0.7 V
i. Find Oxide capacitance(Cox), process transconducance parameter (kn’)
ii. Calculate the values of overdrive voltage (Vov,) and VGS needed to operate the
transistor in the saturation region with a DC bias current of 100 𝞵A.
iii. Determine the gate to source voltage (VGS) required to operate the MOSFET as 1 kΩ
voltage dependent resistor.
5
Q1B An IC chip with several amplifier stages, a constant DC current (reference current) is to be
generated at one location and is to be replicated at other location. This DC replicated
current will be used for biasing amplifiers. Using the methodology of current steering
(mirror), how can you achieve this? Justify your reasoning with circuit diagram and
equations. 3
Q1C Determine the bandwidth of 3 cascaded identical amplifier with each of them having 1 KHz
as lower cut off frequency and 15 KHz as higher cutoff frequency.
2
Q2A Determine the bandwidth of RC coupled amplifier shown in the below Fig. Q2A. Also draw
the small signal model of the same. 4

2B Develop the small signal model hence determine the voltage gain of source follower
(voltage Buffer) circuit. The source follower parameters are Vth =1 V, IDQ=10 mA, VG=7.46 V
and RS=500 Ω. 3
2C Design a 555 timer negative edge triggered monostable multivibrator to produce a pulse 1
ms, hence draw the relavent circuit schematic. Draw the voltage waveforms at pin 6 and 3
when the monostable circuit is triggered by a 500 Hz square wave. Assume C=0.1 µF 3
Q3A Derive an expression for the output voltage Vout of the amplifier circuit shown in Fig. Q3A.
Hence find the value of VR required to get, 0 ≤Vout ≤ 3. 3 V for -5V ≤(V2-V1)≤+5 V.

4
3B Using Op-amps, design a 1 kHz, 6 V (peak to peak) triangular wave generator. Assume
C=0.01µF 3
3C With a neat circuit schematic design a second order Butterworth low pass filter to filter the
harmonics with frequency greater than 10 KHz. Assume C=0.01 µF and ±VDD=±12 V. 3
Q4A For the cascaded amplifier shown in Fig.Q4A, ID1=5 mA, VG1=3.33 V, ID2=10 mA, and
threshold voltages of M1& M2 is Vth=0.2 V.
i. Draw the small signal equivalent circuit.
ii. Determine individual stage gains and overall gain.

5
Q4B With neat diagram explain the working of an all-pass filter
2
Q4C A MOS differential pair operated at a bias current of 5 mA employs transistors with (W/L)
=10 and µnCox=10 mA/V2, using RD=1 kΩ and RSS= 50 kΩ.
i. Find the differential gain, the common mode gain if the output is taken as single-
ended and the circuit is perfectly matched.
ii. If we supply differential input voltage vid=500 mV assess OPAMP’s mode of
operation (linear mode or non- linear mode). 3
Q5A From the fundamental determine the conversion efficiency of a class A power amplifier.
4
Q5B A class B power amplifier providing 22 V peak signal to a 5 Ω load (speaker) and a power
supply of |VDD|=|VSS|=24 V, determine the input power, output power, and circuit efficiency. 3
Q5C Small signal equivalent circuit of an amplifier is as shown in the Fig.Q5C. Calculate the mid-
band gain, input and output miller capacitances and evaluate its effect on amplifier band
width.

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