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VWV - ESE - Study

The document provides VHDL implementations for various digital logic components including AND, OR, NAND, NOR, XOR gates, half adder, half subtractor, D flip-flop, T flip-flop, 4:1 multiplexer, and 1:4 demultiplexer. Each component is presented in both behavioral and dataflow architectures, along with test benches for the half adder and half subtractor. The document serves as a comprehensive guide for designing and testing these fundamental digital circuits.

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Aams Khan
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11 views17 pages

VWV - ESE - Study

The document provides VHDL implementations for various digital logic components including AND, OR, NAND, NOR, XOR gates, half adder, half subtractor, D flip-flop, T flip-flop, 4:1 multiplexer, and 1:4 demultiplexer. Each component is presented in both behavioral and dataflow architectures, along with test benches for the half adder and half subtractor. The document serves as a comprehensive guide for designing and testing these fundamental digital circuits.

Uploaded by

Aams Khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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-- AND Gate Implementations

-- Behavioral Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity and_gate_behavioral is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end and_gate_behavioral;

architecture Behavioral of and_gate_behavioral is


begin
process(A, B)
begin
if (A = '1' and B = '1') then
Y <= '1';
else
Y <= '0';
end if;
end process;
end Behavioral;

-- Dataflow Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity and_gate_dataflow is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end and_gate_dataflow;

architecture Dataflow of and_gate_dataflow is


begin
Y <= A and B;
end Dataflow;

-- TestBench for AND gate


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity and_gate_tb is
end and_gate_tb;
architecture testbench of and_gate_tb is
signal A_tb, B_tb, Y_tb : STD_LOGIC;

component and_gate_behavioral
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end component;
begin
UUT: and_gate_behavioral port map (A => A_tb, B => B_tb, Y => Y_tb);

process
begin
-- Test all possible combinations
A_tb <= '0'; B_tb <= '0'; wait for 10 ns;
A_tb <= '0'; B_tb <= '1'; wait for 10 ns;
A_tb <= '1'; B_tb <= '0'; wait for 10 ns;
A_tb <= '1'; B_tb <= '1'; wait for 10 ns;
wait;
end process;
end testbench;
-- OR Gate Implementations
-- Behavioral Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity or_gate_behavioral is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end or_gate_behavioral;

architecture Behavioral of or_gate_behavioral is


begin
process(A, B)
begin
if (A = '1' or B = '1') then
Y <= '1';
else
Y <= '0';
end if;
end process;
end Behavioral;

-- Dataflow Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity or_gate_dataflow is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end or_gate_dataflow;

architecture Dataflow of or_gate_dataflow is


begin
Y <= A or B;
end Dataflow;
-- NAND Gate Implementations
-- Behavioral Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity nand_gate_behavioral is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end nand_gate_behavioral;

architecture Behavioral of nand_gate_behavioral is


begin
process(A, B)
begin
if (A = '1' and B = '1') then
Y <= '0';
else
Y <= '1';
end if;
end process;
end Behavioral;

-- Dataflow Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity nand_gate_dataflow is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end nand_gate_dataflow;

architecture Dataflow of nand_gate_dataflow is


begin
Y <= A nand B;
end Dataflow;
-- NOR Gate Implementations
-- Behavioral Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity nor_gate_behavioral is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end nor_gate_behavioral;

architecture Behavioral of nor_gate_behavioral is


begin
process(A, B)
begin
if (A = '0' and B = '0') then
Y <= '1';
else
Y <= '0';
end if;
end process;
end Behavioral;

-- Dataflow Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity nor_gate_dataflow is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end nor_gate_dataflow;

architecture Dataflow of nor_gate_dataflow is


begin
Y <= A nor B;
end Dataflow;
-- XOR Gate Implementations
-- Behavioral Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity xor_gate_behavioral is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end xor_gate_behavioral;

architecture Behavioral of xor_gate_behavioral is


begin
process(A, B)
begin
if ((A = '1' and B = '0') or (A = '0' and B = '1')) then
Y <= '1';
else
Y <= '0';
end if;
end process;
end Behavioral;

-- Dataflow Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity xor_gate_dataflow is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end xor_gate_dataflow;

architecture Dataflow of xor_gate_dataflow is


begin
Y <= A xor B;
end Dataflow;
-- Half Adder Implementations
-- Dataflow Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity half_adder_dataflow is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Sum : out STD_LOGIC;
Carry : out STD_LOGIC);
end half_adder_dataflow;

architecture Dataflow of half_adder_dataflow is


begin
Sum <= A xor B;
Carry <= A and B;
end Dataflow;

-- TestBench for Half Adder


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity half_adder_tb is
end half_adder_tb;

architecture testbench of half_adder_tb is


signal A_tb, B_tb, Sum_tb, Carry_tb : STD_LOGIC;

component half_adder_behavioral
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Sum : out STD_LOGIC;
Carry : out STD_LOGIC);
end component;
begin
UUT: half_adder_behavioral port map (A => A_tb, B => B_tb, Sum => Sum_tb, Carry => Carry_tb);

process
begin
-- Test all possible combinations
A_tb <= '0'; B_tb <= '0'; wait for 10 ns;
A_tb <= '0'; B_tb <= '1'; wait for 10 ns;
A_tb <= '1'; B_tb <= '0'; wait for 10 ns;
A_tb <= '1'; B_tb <= '1'; wait for 10 ns;
wait;
end process;
end testbench;
-- Half Subtractor Implementations
-- Dataflow Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity half_subtractor_dataflow is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Diff : out STD_LOGIC;
Borrow : out STD_LOGIC);
end half_subtractor_dataflow;

architecture Dataflow of half_subtractor_dataflow is


begin
Diff <= A xor B;
Borrow <= (not A) and B;
end Dataflow;
-- D-FLIP FLOP
-- Behavioral Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_FF_Behavioral is
Port ( D : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC;
QN : out STD_LOGIC);
end D_FF_Behavioral;

architecture Behavioral of D_FF_Behavioral is


begin
process(CLK, RST)
begin
if RST = '1' then
Q <= '0';
QN <= '1';
elsif rising_edge(CLK) then
Q <= D;
QN <= not D;
end if;
end process;
end Behavioral;

-- Structural Architecture (using basic gates)


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_FF_Structural is
Port ( D : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC;
QN : out STD_LOGIC);
end D_FF_Structural;

architecture Structural of D_FF_Structural is


component master_slave_latch is
Port ( D : in STD_LOGIC;
EN : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC);
end component;

signal clk_inv, master_q, slave_q : STD_LOGIC;


begin
clk_inv <= not CLK;

-- Master latch
master: master_slave_latch
port map (D => D, EN => clk_inv, RST => RST, Q => master_q);

-- Slave latch
slave: master_slave_latch
port map (D => master_q, EN => CLK, RST => RST, Q => slave_q);

Q <= slave_q;
QN <= not slave_q;
end Structural;
-- =========================================
-- T-FLIP FLOP
-- =========================================

-- Behavioral Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity T_FF_Behavioral is
Port ( T : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC;
QN : out STD_LOGIC);
end T_FF_Behavioral;

architecture Behavioral of T_FF_Behavioral is


signal temp_q : STD_LOGIC := '0';
begin
process(CLK, RST)
begin
if RST = '1' then
temp_q <= '0';
elsif rising_edge(CLK) then
if T = '1' then
temp_q <= not temp_q;
end if;
end if;
end process;

Q <= temp_q;
QN <= not temp_q;
end Behavioral;

-- Structural Architecture (using D-FF)


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity T_FF_Structural is
Port ( T : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC;
QN : out STD_LOGIC);
end T_FF_Structural;

architecture Structural of T_FF_Structural is


component D_FF_Behavioral is
Port ( D : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC;
QN : out STD_LOGIC);
end component;

signal q_int, d_int : STD_LOGIC;


begin
-- T-FF logic: D = T XOR Q
d_int <= T xor q_int;

DFF: D_FF_Behavioral
port map (D => d_int, CLK => CLK, RST => RST, Q => q_int, QN => QN);

Q <= q_int;
end Structural;
-- =========================================
-- 4:1 MULTIPLEXER
-- =========================================

-- Behavioral Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX_4to1_Behavioral is
Port ( I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR(1 downto 0);
Y : out STD_LOGIC);
end MUX_4to1_Behavioral;

architecture Behavioral of MUX_4to1_Behavioral is


begin
process(I0, I1, I2, I3, SEL)
begin
case SEL is
when "00" => Y <= I0;
when "01" => Y <= I1;
when "10" => Y <= I2;
when "11" => Y <= I3;
when others => Y <= '0';
end case;
end process;
end Behavioral;

-- Dataflow Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX_4to1_Dataflow is
Port ( I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR(1 downto 0);
Y : out STD_LOGIC);
end MUX_4to1_Dataflow;
architecture Dataflow of MUX_4to1_Dataflow is
begin
Y <= I0 when SEL = "00" else
I1 when SEL = "01" else
I2 when SEL = "10" else
I3 when SEL = "11" else
'0';
end Dataflow;
-- =========================================
-- 1:4 DEMULTIPLEXER
-- =========================================

-- Behavioral Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DEMUX_1to4_Behavioral is
Port ( I : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR(1 downto 0);
Y0 : out STD_LOGIC;
Y1 : out STD_LOGIC;
Y2 : out STD_LOGIC;
Y3 : out STD_LOGIC);
end DEMUX_1to4_Behavioral;

architecture Behavioral of DEMUX_1to4_Behavioral is


begin
process(I, SEL)
begin
Y0 <= '0';
Y1 <= '0';
Y2 <= '0';
Y3 <= '0';

case SEL is
when "00" => Y0 <= I;
when "01" => Y1 <= I;
when "10" => Y2 <= I;
when "11" => Y3 <= I;
when others => null;
end case;
end process;
end Behavioral;

-- Dataflow Architecture
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DEMUX_1to4_Dataflow is
Port ( I : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR(1 downto 0);
Y0 : out STD_LOGIC;
Y1 : out STD_LOGIC;
Y2 : out STD_LOGIC;
Y3 : out STD_LOGIC);
end DEMUX_1to4_Dataflow;

architecture Dataflow of DEMUX_1to4_Dataflow is


begin
Y0 <= I when SEL = "00" else '0';
Y1 <= I when SEL = "01" else '0';
Y2 <= I when SEL = "10" else '0';
Y3 <= I when SEL = "11" else '0';
end Dataflow;

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