Singnal and System

Analog Electronics (Vol-3)

Analog Electronics
Questions
Type 1 – Diode Basics and Diode Circuit Analysis ................................................................................................. 2
Type 2 – Rectifiers and Filters Circuits, ....................................................................................................................... 9
Type 3 – Voltage Regulators & Wave shaping Circuits...................................................................................... 11
Type 4 – DC Analysis and Biasing Circuits of BJT ................................................................................................. 16
Type 5 – Small Signal Analysis of BJT and Single Stage BJT Amplifier ......................................................... 20
Type 6 – DC Analysis and Biasing Circuits of MOSFET ...................................................................................... 26
Type 7 – Small Signal Analysis of MOSFET and Single Stage MOSFET Amplifier .................................... 29
Type 8 – Frequency Response of BJT & MOSFET Amplifier [ECE] .................................................................. 33
Type 9 – Multistage and Differential Amplifier [ECE] .......................................................................................... 36
Type 10 – Feedback Amplifier...................................................................................................................................... 38
Type 11 – Power Amplifier [ECE]................................................................................................................................. 41
Type 12 – Operational Amplifier [Op-Amp] ........................................................................................................... 44
Type 13 – Op-Amp Applications................................................................................................................................. 48
Type 14 – Sinusoidal Oscillator Circuits & 555 timers ........................................................................................ 52
Solutions .............................................................................................................................................................................. 58

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 Analog Electronics (Vol-3)

Kuestions

Type 1 – Diode Basics and Diode Circuit Analysis

For Concepts, please refer to Analog Electronics K-Notes, Diodes

 Common Mistake / Point to remember

• Remember to check the state of other diode after assuming state of one diode to verify the initial
hypothesis.
• In open circuit analysis, the diode having maximum voltage across it will conduct first & in short circuit
analysis the diode with positive current will be ON & the one with negative current will be OFF.
• Usually, short circuit test is easier as composed to open circuit test.

Sample Problem

In the figure, D1 is a real silicon pn junction diode with a drop of 0.7 V under forward bias condition and D 2 is a Zener diode
()
with breakdown voltage of – 6.8 V. The input Vin t is a periodic square wave of period T, whose one period is shown in the
figure.

Assuming 10  T , where  is the time constant of the circuit, the maximum and minimum values of the output waveform
are respectively.
(A) 7.5 V and – 20.5 V (B) 6.1 V and – 21.9 V
(C) 7.5 V and – 21.2 V (D) 6.1 V and – 22.6 V

Solution: (A) is correct option

()
When, Vin t = +14V

Diode D 1 will be ON

Diode D 2 will be in break down

Vovt = 6.8 + 0.7 = 7.5V

During this Period,
Capacitor charges to a voltage of,
VC = 14 − 7.5 = 6.5V

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 Analog Electronics (Vol-3)

When, Vin (t) = – 14 V

Diode D 1 will be OFF

Diode D 2 will be ON

KVL in the outer loop gives.

Vovt = −14 − 6.5
Vovt = −20.5V

Sample Problem

A voltage signal 10 sinωt is applied to the circuit with ideal diodes, as shown in figure, the maximum, and minimum values
of the output waveform Vout of the circuit are respectively

(A) +10 V and −10 V (B) +4 V and −4 V

(C) +7 V and −4 V (D) +4 V and −7 V

Solution: (D) is correct option

In the positive half cycle (when Vin > 4 V) diode D2 conducts and D1 will be off so the Vout = + 4 Volt
In the negative half cycle diode D1 conducts and D2 will be off so the circuit is,

Applying KVL

Vin − 10I + 4 − 10I = 0

Vin + 4
=I
20
Vin =− 10 V (Maximum value in negative half cycle)

−10 + 4 3
So, I = =− mA
20 10

Vin − Vout
=I
10
−10 − Vout 3
=−  −(10 − 3)  −7 volt
10 10

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 Analog Electronics (Vol-3)

Sample Problem

The current through the Zener diode in figure is

(A) 33 mA (B) 3.3 mA

(C) 2 mA (D) 0 mA

Solution: (C) is correct option

Given circuit
In the circuit
V1 = 3.5 V (given)
Current in zener is.
V1 − Vz 3.5 − 3.3
Iz = = = 2 mA
Rz 0.1  103

Problems

01. Assume that each diode has V = 0.7V for the circuit shown below. The current passing through the diode D1 is

(A) 0 (B) 0.86 mA

(C) 1 mA (D) 1.86 mA

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 Analog Electronics (Vol-3)

02. For the circuit shown below, the Zener diode has VZ = 5V and the V = 0.7V when it is forward biased. The transfer
characteristic curve is

(A) (B)

(C) (D)

03. Two identical junction diodes where VI characteristics is Is = 0.1 A; VT = 26 mV and = 2 are connected as shown in fig.
The voltage across diode 2 (D2) will be

(A) 0.034 V

(B) 0.010 V

(C) 14.95 V

(D) 15.00 V

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 Analog Electronics (Vol-3)

04. The transfer characteristics of the circuit shown in fig. for an input of 30 sinωt is

(A) (B)

(C) (D)

05. In the circuit shown, D and D are ideal diodes. The current i and i respectively is
1 2 1 2

(A) 0, 4mA (B) 4mA, 0

(C) 0, 8mA (D) 8mA, 0

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 Analog Electronics (Vol-3)

06. For the circuit shown in figure, each diode has V = 0.7V . The output voltage V is ______________(V).
T 0

(A) 4.7V (B) 4.3V

(C) 3.3V (D) 2.7V

07. For the ideal diode circuit shown in figure, V0 is __________________.

(A 4.3 V (B) 5.7 V

(C) 3.8 V (D)1.9 V

08. A sinusoidal voltage source VAB = 10sin t Volts, is applied across the terminal A and B. Here both the diodes are ideal.
The impedance offered by the circuit across the terminal A and B is __________kΩ.

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 Analog Electronics (Vol-3)

( )
09. For the circuit shown below, the incremental resistance [when switch s is closed] circuit would be ________ 

Assuming initially Vo = 3V when S is open and  = 2, Rf = 0, VT = 0.026V

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 Analog Electronics (Vol-3)

Type 2 – Rectifiers and Filters Circuits,

For Concepts, please refer to Analog Electronics K-Notes, Diodes and Filter Circuits

 Common Mistake / Point to remember

• In rectifiers, factors like PIV. TUF, Rectification efficiency are important. In a full wave center tapped rectifier
the TUF can be computed by taking average of primary & secondary TUF.
• If in filters RC >> T, Then we can assume linear discharging of C filter instead of exponential

Sample Problem

In a full-wave rectifier using two ideal diodes, Vdc and Vm are the dc and peak values of the voltage respectively across a
resistive load. If PIV is the peak inverse voltage of the diode, then the appropriate relationships for this rectifier are
Vm Vm
(A) Vdc = , PIV = 2Vm (B) Vdc = 2 , PIV = 2Vm
 
V Vm
(C) Vdc = 2 m , PIV = Vm (D) Vdc = , PIV = Vm
 

Solution: (B) is correct option

Consider a full wave rectifier using two diodes

Now as we know for this circuit

2Im 2 VmRL 2V R
VDC = IDC  RLoad = RL =   m L
  RL + RF  RL
2Vm
VDC =

PIV: Peak inverse voltage is the maximum possible voltage across a diode, when it is reverse biased.
Let us consider that diode D1 : FB and D2 : RB.

Applying KVL in the highlighted loop.

VPIV + Vm + V0 = 0  VPIV = Vm + V0
Now, PIV = V0max = Vm + V0max = Vm + Vm
PIV = 2Vm
Hence option (B) is correct.

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 Analog Electronics (Vol-3)

Problems

01. Which of the following statements are true about the given circuit?

(A) The circuit is that of a bridge rectifier

(B) The PIV of the diode D1 must be greater than v0 for the circuit to function as a bridge rectifier
(C) For silicon diodes, the value of v0=(vi-1.4) V
(D) All of the mentioned

02. In the given circuit, what will be the nature of the output waveform?

(A) Half rectified (B) Full rectified

(C) Sinusoidal (D) DC

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 Analog Electronics (Vol-3)

Type 3 – Voltage Regulators & Wave shaping Circuits

For Concepts, please refer to Analog Electronics K-Notes, Voltage Regulators & Wave shaping circuits

 Common Mistake / Point to remember

• For Zener diode to operate in breakdown region, the Thevenin voltage across the diode should be more
than breakdown voltage.
• In clipper circuit, it is easier to analyze by determining Thevenin equivalent across diode branch.

Sample Problem

In the voltage regulator shown in Figure, the load current can vary from 100mA to 500mA. Assuming that the Zener diode
is ideal (i.e., the Zener knee current is negligibly small and Zener resistance is zero in the breakdown region), the value of R
is

(A) 7 (B) 70

70
(C)  (D) 14
3

Solution: (D) is correct option

Given IZk = 0 , Vz = 5V
I: varies from 100 to 500 mA
For proper working of the voltage regulator.
I1 = Izk + Imax
12 − 5
= 0 + 500mA
R
R = 14 

Sample Problem

(a) For figure, Plot v o under steady state conditions, with and without C. Assume that the diode is ideal.

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 Analog Electronics (Vol-3)

(b) Design a circuit using two ideal diodes, one resistor and two voltage sources that would convert the input voltage to the
output voltage which is shown below. The resistor value need not be specified.

Solution:
(a) With capacitor : Envelope detector and Without Capacitor : Clipper
With capacitor:

Considering positive half cycle: Diode is ON

( )
The capacitor starts charging with time constant C where c = RF  C  0  C = 0
Hence the charging is very fast.
The capacitor charges up to Vm (maximum amplitude of the input) and after this instant as the voltage across the capacitor
is more than Vin , hence the Diode gets into OFF state and the capacitor starts discharging through R with time constant
d = RC

Where d  c j therefore the discharge is slow.

( )
In the next positive cycle when Vin becomes greater than VC decayed value , then the diode gets into ON state and the

capacitor again charges to Vm and the cycle continues

Without capacitor:

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 Analog Electronics (Vol-3)

+ve half cycle – ve half cycle

V0 = Vin V0 = 0

V ; Vin  0
V0 =  in
 0 ; Vin  0

(b) The output becomes 5V (constant); if input is more than 5V. For their
purpose we can use the following biased clipper circuit.

The output becomes –5V (constant), If Vi decease less than -5V. For this
purpose we can use the following clipper circuit.

Combining both the circuit we get

Problems

01. The Zener diode in the circuit shown has Vz = 6.2 V and Zener knee current is 5 mA. The maximum load current drawn
from this circuit ensuring proper functioning over input range (40 – 50V) is

(A) 43.8 mA (B) 38.8 mA

(C) 33.8 mA (D) 28.8 mA

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 Analog Electronics (Vol-3)

02. In the zener voltage regulator circuit shown in fig. the 5V zener diode requires IZK of 10mA for obtaining a regulated out-
put of 5V. The maximum permissible load current in the circuit and minimum power rating of zener diode respectively are

(A) 10mA, 0.25 watts

(B) 50mA, 0.25 watts

(C) 40mA,0.25 watts

(D) 40mA, 2.5 watts

03. For an input of VS = 5 sint, (assuming ideal diode), the circuit shown in fig. will behave as?

(A) Clipper, sine wave clipped at – 2V

(B) Clamper, sine wave clamped at – 2V

(C) Clamper, sine wave clamped at 0 volt

(D) Clipper, sine wave clipped at 2V

04. The function of the following circuit if the input is a sine wave

(A) Transmits that part of sine wave, which is above + 8V and below + 4V.
(B) Transmits that part of sine wave, which lies between + 4V and + 8V.
(C) Transmits that part of sine wave, which lies above – 4V and below + 8V
(D) Transmits that part of sine wave, which lies below + 4V and above – 8V

05. For the clipper circuit shown in the Fig. the first break point occurs when Vi is at

(A) 2.5 V (B) 5 V

(C) 10 V (D) 7.5 V

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 Analog Electronics (Vol-3)

06. The output waveform for the circuit given below is

(A) (B)

(C) (D)

07. The circuit shown below is a Zener regulated dc power supply. The minimum value of R L for which the output voltage
remains constant is _________kΩ.

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 Analog Electronics (Vol-3)

Type 4 – DC Analysis and Biasing Circuits of BJT

For Concept, refer to Analog Electronics K-Notes, Transistor Biasing and Transistor Amplifiers

 Common Mistake / Point to remember

• Verify the region of operation of Transistor before calculating the Transistor parameters. While calculating
IC,VCE,VC,IB,IE, open circuit all capacitors and disable AC sources.
• For pnp transistor, the analysis remains same as npn transistor but polarity of voltage & direction of currents
are reversed.

Sample Problem

The transistor used in the circuit shown below has a β of 30 and ICBO is negligible. If the forward voltage drop of diode is 0.7
V, then the current through collector will be

(A) 168 mA (B) 108 mA

(C) 20.54 mA (D) 5.36 mA4

Solution: (D) is correct option

Assume that the transistor operated in active region then apply KVL to base-emitter loop.
5-103IB-0.7-0.7+12=0
IB=15.6 mA
IC=0.468 A
Apply KVL to collector-emitter loop
0-2.2K IC - VCE+12=0
VCE=-2200 IC+12=-1017.6 V
As 0<VCE<VCC Not satisfying this condition. Transistor operating in saturation region.
V+(sat)=0.2 V
Apply KVL, 0-2.2IC-0.2+12=0
IC=5.36 mA

Problems

01. For the circuit shown in the given figure, the quiescent point is

(A) 12V, 5mA

(B) 12V, 2mA
(C) 11V, 2mA
(D) 10V, 5mA

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 Analog Electronics (Vol-3)

02. Assertion (A): A self-biased BJT Circuit is more stable as compared to a fixed biased one
Reason(R): A self-biased BJT circuit uses more components as compared to a fixed biased one

(A) Both A and R are true and R is the correct explanation of A

(B) Both A and R are true but R is NOT the correct explanation of A
(C) A is true but R is false
(D) A is false but R is true

03. For the transistor circuit shown below, the value of the output voltage V o is

(A) 0.2 V (B) 2.5 V

(C) 4 V (D) 5 V

04. For the transistor circuit shown below hfe =  = 100, hie = 1 k. The DC voltage between the collector and emitter
terminals is

(A) 2.52 Volts (B) 5 Volts

(C) 6.207 Volts (D) 7.48 Volts

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 Analog Electronics (Vol-3)

05. In the transistor circuit given that  = 100, VBE = 0.7 The value of Quiescent collector current & voltage are

(A) (0.589 mA, 18.22 V) (B) (0.917 mA, 11.56 V)

(C) (11.56 V, 0.589 mA) (D) (18.22 V, 0.917 mA)

06. In the Series voltage regulator circuit. Given that VZ = 10 V, VBE = 0.7 V, =50. The value of VCE = ……………….

(A) 20 V (B) 10 V
(C) 9.3 V (D) 10.7 V

07. In the amplifier circuit shown in the figure, the values of R1 and R2 are such that the transistor is operating at
V = 3V and I = 1.5mA when it’s  is 150. If the  of the transistor is 200, then the operating voltage V (in volts)
CE C CE
is

(A) 2 V (B) 3 V
(C) 4 V (D) 5 V

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 Analog Electronics (Vol-3)

08. For the transistor in figure, value of voltage V is __________________ (V).  = 50

EC

(A) 5.025V (B) 6.074V

(C) 4.125V (D) None

09. In the circuit shown in figure, the transistor has current gain of 100 and V BE = 0.7V. The current flowing through 5 k
load (in mA) is _________________.

10. Consider the circuit shown in figure. If the β of the transistor is 30 and ICBO is 20nA and the input voltage is +5V, the
transistor would be operating in

(A) Saturation region (B) Active region

(C) Breakdown region (D) Cut-off region

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 Analog Electronics (Vol-3)

Type 5 – Small Signal Analysis of BJT and Single Stage BJT Amplifier
For Concept, refer to Analog Electronics K-Notes, BJT Amplifier & MOSFET Amplifier

 Common Mistake / Point to remember

In small signal model prepare βre model or gm model as both are identical & try to analyze amplifier as a
network rather than memorizing expression of gain for different configurations parameters like input
impedance, output impedance, gain are important.

Sample Problem

For the DC analysis of the Common-Emitter amplifier shown, neglect the base current and assume that the emitter and
collector currents are equal. Given that VT = 25mV, VBE = 0.7V, and the BJT output resistance r0 is practically infinite. Under
these conditions, the midband voltage gain magnitude, A v = v 0 /v i V/V , is ____________.

Solution: 128
Neglect base current
 IB = 0   = 
IE = IC
12  47
VB = = 4.7V
 47 + 73
VE = VB − VBE = 4.7 − 0.7 = 4V
VE 4V
IE = = = 2mA = IC
2k 2k
1 I 2mA
gm = = E = = 0.08
re VT 25mV
Small signal equivalent circuit

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 Analog Electronics (Vol-3)

V = Vi
Vout = −gmV 2k || 8k 
Vout = −gmV1.6k
i

Vout
= −0.08  1.6  103 = −128
Vi
V0
= 128
Vi

Sample Problem

For the amplifier shown in the figure, The BJT parameters are VBE = 0.7V,  = 200 and thermal voltage VT = 25mV The
 V0 
voltage gain of amplifier is  =?
 Vi 

Solution: -228
R TH = 33k || 11k
33  11
R TH = = 8.25k
44
12  11
VTH = = 3V
44
1
( )
DC Analysis:- f = 0 X C =
2fc
=   Capacitor open circuit

Equivalent circuit
KVL in loop I:-
IB ( 8.25k ) + VBE + IE (1.01k ) = 3
IB ( 8.25k ) + 0.7 + ( IB + IC )(1.01k ) = 3
IC = IB
IB ( 8.25k ) + 0.7 + 201 IB (1.01k ) = 3
I = 0.01094mA
B
IC = IB = 2.88mA

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 Analog Electronics (Vol-3)

AC Analysis:-
C=Short circuit: DC voltage=0 (Ground)

Equivalent  model:-
IC
gm = = 0.0841
VT

r = 
gm
r = 2376.5

V0 = ( −5k )  ( 2.188mA ) = −10.94

Vi = IB (r ) + IE (10 )
Vi = ( 0.01094  2.376 ) + 2.2  10 −3  10
Vi = 0.040
V0
AV = = −227.9 −228
Vi

Problems

01. The below figure shows a BJT amplifier circuit has ; r0  20k ; VT = 26mV;  = 60

Determine the voltage gain of the circuit?

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 Analog Electronics (Vol-3)

02. For the CB amplifier shown below, r0 = 250k,gm = 2m . Find the Thevenin’s voltage faced by load resistance R L .
The Thevenin voltage VTh is ______________ Vi( )

03. A BJT amplifier is shown in fig. Assume that the current Ibias is ideal, and the transistor has very large, rπ = 0 and r0 → .
The small signal ac mid band gain of the amplifier is (approximately) [Assume C1 & C2 are very large]

(A) 100 (B) 50

(C) 20 (D) 1

1
04. For the BJT amplifier configuration h = 1k, h = 2.5  10−4 ,h = 150 and = 40k Determine current gain
ie re fe h
oe
A. [Rg=100KΩ]

(A) -100 (B) 100

(C) -150 (D) 150

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 Analog Electronics (Vol-3)

05. What will be the resistance (kΩ) seen between base and ground in the following figure
( = 100 )

(A) 110 kΩ (B) 102 kΩ

(C) 115 kΩ (D) 120 kΩ

06. Consider following BJT amplifier circuit.

(a) Find DC collector current and DC collector to emitter voltage drop

(A) 0.01mA,12V (B) 1mA,6V
(C) 1mA,5V (D) Not

( ) ( )
(b) Find trance conductance gm and base to emitter diffusion resistance r

(A) 26mA s ,38.5k (B) 38.5mA s,26

(C) 2.6mA s ,38.5k (D) 38.5mA s ,2.6k

V0
(c) Find the small signal voltage gain =?
Vi
(A) -11.4 (B) +11.4
(C) -231 (D) +231

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 Analog Electronics (Vol-3)

V0
07. The amplifier circuit shown uses a transistor with hie = 1 k, hfe = 100 . Then the magnitude of voltage gain A =
Vi
is ___________________.

(A) 16 (B) 20
(C) 30 (D) None

08. In the amplifier circuit shown in figure, a silicon transistor with V BE = 0.7V, and  = 200 at a thermal voltage of 25 mV is
used. The approximate voltage gain of the amplifier is

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 Analog Electronics (Vol-3)

Type 6 – DC Analysis and Biasing Circuits of MOSFET

For Concept, refer to Analog Electronics K-Notes, BJT Amplifier & MOSFET Amplifier

 Common Mistake / Point to remember

• Verify the region of operation of MOSFET before calculating the MOSFET parameters. While calculating IDS,
VGD and VDS , open circuit all capacitors and disable AC sources.
• In DC biasing of MOSFET, start from assumption that MOSFET is operating in saturation region & verify the
assumption after computing drain current.
• CMOS circuits are important from ECE GATE point of view & you must remember that MOSFET will be fully
ON when it is in linear region.

Sample Problem

For the n-channel enhancement MOSFET shown in figure, the threshold voltage Vth = 2 V. The drain current ID of the MOSFET
is 4 mA when the drain resistance RD is 1 kΩ. If the value of RD is increased to 4 kΩ, drain current ID will become

(A) 2.8 mA (B) 2.0 mA

(C) 1.4 mA (D) 1.0 mA

Solution: (A) is correct option

For a n-channel enhancement mode MOSFET transition point is given by,
VDS(sat) = VGS − VTH ( VTH = 2 volt)
VDS(sat) = VGS − 2
From the circuit,
VDS = VGS
So VDS(sat) = VDS − 2 & VDS = VDS(sat)+ 2
VDS > VDS(sat)
Therefore transistor is in saturation region and current equation is given by.
ID = K(VGS- VTH)2
4 = K(VGS- 2)2
VGS is given by
VGS = VDS = 10 − IDRD= 10 − 4 *1 = 6 Volt
So, 4 = K(6 − 2)2
K=1/4
Now RD is increased to 4 kΩ, Let current is I'D and voltages are V'DS= V'GS
Applying current equation.

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 Analog Electronics (Vol-3)

1
ID = K(VGS
 − VTH )2 = (V  − 2)2
4 GS
V'DS = V 'GS = 10 − ID  RD = 10 − 4ID
So,
4ID = (10 − 4ID − 2)2  4ID = (8 − 4ID )2
4ID = 16(2 − ID )2
4ID 2 − 17ID + 16 = 0  ID = 2.84 mA

Problems

01. Match the following:

List – 1 List – 2
P. JFET 1. Amplifier
Q. BJT 2. Operated in depletion mode only
R. D-MOSFET 3. Operated in enhancement mode only
S. E-MOSFET 4. Operated in both depletion and enhancement modes

Codes:
(A) P-2, Q-1, R-3, S-4
(B) P-3, Q-1, R-2, S-4
(C) P-4, Q-1, R-3, S-2
(D) P-2, Q-1, R-4, S-3

02. The drain of an n-channel MOSFET is directly connected to Gate so that VGS = VDS . The threshold voltage of it is 2 V. The
drain Current is 2mA, when VGS = 3V . Then for VDS = 4V , the value of ID is
(A) 8 mA (B) 4 mA
(C) 2.67 mA (D) 1.5 mA

03. The amplifier stage shown uses an n – channel MOSFET(FET) having IDSS = 1mA, VP = -1V. If the quiescent to ground
voltage is 10V. Find ID?

(A) 0.35mA (B) 0.25mA

(C) 0.40mA (D) 0.45mA

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 Analog Electronics (Vol-3)

04. What is the value of Rs required to self bias an N channel JFET with VP = –10V, IDSS = 40 mA and VGSQ = –5V?
(A) 250  (B) 500 
(C) 750  (D) 1500 

05. Given that | Vt |= 1V, nCox = 50A / V2 ,L = 1m and W = 100m . What should be the value of V2 and I 2 ?

(A) 2.5V, 5.625mA (B) 0.5V, 562.5  A

(C) 2V, 56.25 mA (D) 5V, 56.25  A

06. Two identical MOISFETs having IDSS = 10 mA and VP = −4V are used in the amplifier circuit shown in figure. The values
of IDS and VGS respectively are
Q1 Q1

(A) 3 mA, − 3V (B) 1 mA, − 2.45V

(C) 2 mA, − 4V (D) 0 mA, −4V

07. Consider the MOSFET circuit shown in the figure below, the circuit is biased such that MOSFET is in saturation and the
drop across the MOSFET is nearly equal to zero. (Assume VT = 2V )

Then the value of i to reach the given condition would be ________mA.

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 Analog Electronics (Vol-3)

Type 7 – Small Signal Analysis of MOSFET and Single Stage MOSFET

Amplifier
For Concept, refer to Analog Electronics K-Notes, BJT Amplifier & MOSFET Amplifier

 Common Mistake / Point to remember

The only small signal model in MOSFET analysis gm model & again make an effort to design the model &
then gain can be computed by analyze it as a network.

Sample Problem

Two identical. MMOS transistors M1 and M2 are connected as shown below. The circuit is used as an amplifier with the
input connected between G and S terminals and the output taken between D and S terminals, Vbias , and VD are so adjusted
iD
that both transistors are in saturation. The trans-conductance of this combination is defined as gm = while the output
v GS
v GS
resistance is r0 = , where iD is the current flowing into the drain of M2 . Let gm1 , gm2 , be the trans-conductances and
iD
r01 , r02 be the output resistances of transistors M1 and M2 , respectively.
Which of the following statements about estimates for gm and r0 is correct?

(A) gm  gm1 .gm2 .r02 and r0  r01 + r02

(B) gm  gm1 + gm2 and r0  r01 + r02
(C) gm  gm1 and r0  r01 .gm12 .r02
(D) gm  gm1 and r0  r02

Solution: (C) is correct option

MOS cascade is used to provide current buffering for the output of a common source amplifying transistor.
Earlier we saw that Common Gate configuration is used as current buffer. As the transistor Q2 is in CG configuration with
biasing voltage VG2 it acts as current buffer
In Common Gate configuration we know that output resistance increases by a factor and the input resistance decrease by a
factor.
Let say factor is K
R0 = r01  K = Kr02

To find R 0 set Vi = 0
Small signal model for the given circuit for output resistance

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 Analog Electronics (Vol-3)

− Vgs2 = ix  r01

(
Vx = ix − gm2 Vgs2 r02 )
Vx = ixr02 + 1 + gm2r01  r02ix
Vx
= r01 + r02 + r01r02gm2 
ix

R 0 = r01 + r02 + r01r02 gm2 

R 0  r0 1r0 2 gm2

R 0 = ( gm2r02 ) r01
gm2r02  A0 = Intrinsic gain of Common Gate Amplifier
R0 = A02r01
i0
gm =
Vi
As the Q2 is current buffer only
gm2 Vgs2 = gm1 Vi
The overall trans-conductance would be
i0
gm = = gm1
Vi

Problems

01. Calculate the voltage gain Av for the FET Amp shown below. Assume IDSS = 8mA, rd=90k, VP=-6V.

(A) -3.65

(B) -9.11

(C) -1.07

(D) -10.74

02. In the circuit shown: K p = 0.25mA V 2 , VTP = −0.5V,d = 0,IDQ = 0.20mA . Find small signal voltage gain

(A) -2.3

(B) -3.5

(C) -1.91

(D) -6.2

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 Analog Electronics (Vol-3)

03. What will small signal voltage gain of NMOS amplifier with depletion load?
Given,
VTND = 0.8V VTNL = −1.5V D = L = 0.01 / V
K nD = 1mA V 2 K nL = 0.2mA V 2 IDQ = 0.2mA

(A) -224 (B) -630

(C) -450 (D) -520

04. For the circuit shown the parameter are VTN = 0.8V , Kn = 1mA V2 ,  = 0 . Find the voltage gain

(A) -2.2 (B) -9.9

(C) -6.36 (D) -5.5

05. Which one of the following gain equations is correct for a MOSFET common-source amplifier?(gm is mutual conductance,
and RD is load resistance at the drain)
(A) AV = gm/RD (B) AV = gm RD
(C) AV = gm/(1 + RD) (D)AV = RD/gm.

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 Analog Electronics (Vol-3)

06. A MOSFET circuit is biased with a constant current source and a source bypass capacitor as shown in figure below.

Assume the transistor parameters are

nCox W
VTN = 0.8V , . = 1mA V 2 and  = 0 and the transistor is biased in saturation region.
2 L
The small signal voltage gain of the circuit is ________.

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 Analog Electronics (Vol-3)

Type 8 – Frequency Response of BJT & MOSFET Amplifier [ECE]

For Concept, refer to Analog Electronics K-Notes, BJT Amplifier & MOSFET Amplifier

 Common Mistake / Point to remember

• To find out mid frequency gain, Ri, R0, AI large capacitors [CE, CC, CB] must be short circuited
• The lower cut off frequency, can be computed by determining Thevenin resistance across coupling by pass
capacitor.
• The upper cut-off frequency can be computed by miller’s theorem across parasitic capacitance.

Sample Problem

Consider the following CE amplifier shown below

 = 100,gm = 0.3861A V ,r0 = ,r = 259
RS = 1k,RB = 93k,RC = 250,RL = 1k,C1 = ,C2 = 4.7F

(1) Resistance seen by source VS is

(A) 250 (B) 1258
(C) 93k (D) 

(2) Lowest Cut-off frequency due to C 2 is

(A) 33.9Hz (B) 27.1Hz
(C) 13.6Hz (D) 16.9Hz

Solution: (B) and (B) are correct options

AC Analysis:-

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 Analog Electronics (Vol-3)

R i = R S + (RB || r ) = 1k + 93k || 259

Ri = 1258
Lowest cut-off frequency due to C 2
1
f = = 27.1Hz
2  (R C + R L ) C 2

Problems

01. Given  = 100, VA =  , VBE( ON) = 0.7V, gm = 10.5mA V ,r = 9.5k

(1) Input AC resistance looking into base terminal is

(A) 10.92k (B) 50k
(C) 7.143k (D) 8.33k

(2) The coupling capacitor offers a ______ Cut-off frequency of ______ Hz.
(A) Upper. 2.198Hz (B) Lower, 2.198Hz
(C) Upper, 13.81Hz (D) Lower, 13.81Hz

02. Consider following PMOS circuit:

Given: VTP = −2V,K p = 0.25mA V 2 ,  = 0,gm = 0.707mA V

The _________ 3dB cut-off frequency offered by CL is______.

(A) Upper, 2.39MHz (B) Lower, 2.39MHz
(C) Upper, 15MHz (D) Lower, 15MHz

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 Analog Electronics (Vol-3)

03. Find the  cut-off frequency and unity short circuit CE current gain bandwidth a BJT biased with
IC = 1mA,C = 3pF,C = 0.5pF,  = 100
(A) f = 3.9MHz (B) f = 3.9MHz

fT = 2.45MHz fT = 0.39GHz
(C) f = 24.5MHz (D) f = 24.5MHz

fT = 2.45GHz fT = 0.39GHz

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 Analog Electronics (Vol-3)

Type 9 – Multistage and Differential Amplifier [ECE]

For Concept, refer to Analog Electronics K-Notes, Multistage Amplifier

 Common Mistake / Point to remember

While calculating overall gain for multistage amplifiers don’t multiply individual gains itself. First draw small
signal equivalent model for each stage and cascaded all stages.

Sample Problem
A cascade connection of 2 voltage amplifier A 1 and A 2 is shown in the figure. The open loop gain AV0 input resistance R in
and output resistance R 0 for A1 & A2 are
A1 : AV0 = 10 ,Rin = 10k ,R0 = 1k
A2 : AV0 = 5 ,Rin = 5k ,R0 = 200k
Vout
Overall voltage gain =?
Vin
Solution: 34.7
5Vx  1000 V0
V0 = = = 4.1
1200 VX
10Vin  5 VX
Vx =  = 8.3
6 Vin
V0
= 4.1  8.3 = 34.7
Vin

Problems

01. Three identical amplifier with each one having voltage gain=50, input resistance of 1k and output resistance of 250
are cascaded. The open circuit voltage gain of combined amplifier is:-
(A) 49dB (B) 51dB
(C) 98dB (D) 102dB

02. Consider a transfer function with poles at 1MHz and 2MHz. assume all other and zero are larger than 2MHz. calculate
the high 3dB frequency ____MHZ
(A) 0.52 (B) 0.81
(C) 0.69 (D) 0.32

03. Calculate the percentage tilt in the output if the input current I is a 100Hz square wave.

(A) 20

(B) 15

(C) 25

(D) 10

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 Analog Electronics (Vol-3)

04. Three identical cascade stages have an overall upper 3dB frequency of 20KHz and lower 3dB frequency of 20Hz. What is
the fL and fH of each stage. Assume non interacting stages
(A) 10.2 kHz, 12.16 kHz (B) 39.23kHz, 26.32 kHz
(C) 10.2 kHz, 39.23 kHz (D) 12.16kHz, 46.52 kHz

05. Consider a pulse input with 0 rise time of 10 s . What must be the high 3dB frequency of on amplifier used to amplify
the given signal without excessive distortion?
(A) 30kHz (B) 35kHz
(C) 40kHz (D) 20kHz

06. A multi-storage amplifier has a lower 3-db cut-off frequency of 2 KHz. What is the highest frequency square wave which
can amplified with less than 20 percent tilt/sog?
(A) 10kHz (B) 15kHz
(C) 20kHz (D) 25kHz

07. Consider a multistage amplifier with three stages whose rise time are 0.5 s , 1 s , 2 s when in isolated condition, for
an input wave form rise of 0.1 s . What is the output his waveform rise time of the multi-stage amplifier for some input? (in
s )
(A) 1.25 (B) 2.10
(C) 1.63 (D) 1.52

 V0 
08. Find the differential gain A =   if VT = 25 mV
V
 i 

(A) −120 (B) −160

(C) −80 (D) −40

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 Analog Electronics (Vol-3)

Type 10 – Feedback Amplifier

For Concept, refer to Analog Electronics K-Notes, Feedback Amplifier

 Common Mistake / Point to remember

• To determine the nature of mixing check if KCL or KVL equation at input of amplifier depends on feedback.
To determine nature of sampling.
• ( ) or I = f ( I )
In current mixing, make v i = 0 & determine whether I f = f V0 f 0

• In voltage mixing, make Ii = 0 & determine whether Vf = f ( V ) or V = f ( I )

0 f 0

Sample Problem

An amplifier with open loop voltage gain AV = 1000  100 is available. It is necessary to have an amplifier whose voltage
gain varies by number more than 0.1%
(a) Find reverse transmission factor 
(b) Find the gain with feedback

Solution: 0.099, 10
A
Af =
1 + A

( A ) .............. 1
dA
dA f
Af
=
1 + A
()
dA f 0.1 dA 100
=  10−3 = = 0.1
Af 100 A 1000
From (1)
10−1
10−3 =
1 + A
1 + A = 100
99
= = 0.099
1000
A 1000
(b) A f = =
1 + A 1 + 1000  0.099
Af = 10

Problems

01. Desirable characteristics of a Trans conductance amplifier is

(A) High input resistance and high output resistance
(B) High input resistance and Low output resistance
(C) Low input resistance and high output resistance
(D) Low input resistance and Low output resistance

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 Analog Electronics (Vol-3)

02. An amplifier without feedback gives a fundamental output of 36V with 7 percent second harmonic distortion when the
input is 0.026V
(a) If 1.2% of the output is feedback into the input in a negative voltage series feedback circuit what is output voltage

(b) If the fundamental output is maintained at 36V but the second harmonic distortion is reduced to 1% what is input voltage

(A) 3.16V, 0.21V (B) 2.19V, 0.196V

(C) 2.19V, 0.21V (D) 3.16V, 0.196V

03. The Amplifier circuit shown in the figure example of

(A) Voltage series feedback (B) Voltage shunt feedback

(C) Current series feedback (D) Current shunt feedback

04. It is desired to reduce total harmonic distortion of an amplifier from 8% to 2% by use of 5% feedback. What is the gain
of the amplifier with original distortion and with reduced distortion?
(A) 60, 15 (B) 15, 90
(C) 6, 1.5 (D) 1.5, 6

05. Three Amplifiers each of gain (A0/2) and producing a phase of 600 are connected in cascaded configuration. The feedback
loop is closed through a positive gain of 0.008. What should be the value of A0 for the system to be oscillatory?
(A) + 10 (B) – 10
(C) + 250 (B) + 83.3

06. Consider the amplifier shown below. The amplifier has overall trans conductance gain of −1m A , Voltage gain of -4
V
and de-sensitivity of 50. If RS = 1k , hfe = 150 . The quiescent collector current and type of feedback is _________ (mA) to
_________.

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 Analog Electronics (Vol-3)

(A) 5.1, Current series (B) 3.9, Voltage series

(C) 3.9, Current series (D) 5.1, Voltage series

07. 10mV input to an amplifier gives 20 V output without feedback. With negative feedback, 400 mV input is required to get
the same output. The feedback factor (β) is ______________ %.

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 Analog Electronics (Vol-3)

Type 11 – Power Amplifier [ECE]

For Concept, refer to Analog Electronics K-Notes, Power Amplifier

 Common Mistake / Point to remember

• In power amplifier, transistor acts as a non-linear element so that it can be analyzed with graphical method
but not small signal equivalent model.
• In power amplifier, instead of solving many numerical focus more on studying types of amplifier & analyze
energy conversion efficiency of each type of amplifies

Sample Problem

( )
For ideal Class-B amplifier with complimentary symmetry shown below VCC = 15V,RL = 10k the input is sinusoidal.
Calculate conversion efficiency

Solution: 78.5%
P0 ( ac )
=
Pin ( dc )
2
I  V
P0 ( ac ) =  m   RL and Im = CC = 1.5A
 2 RL
2
 1.5 
P0 ( ac ) =    10 = 11.25watt
 2
 2I  15  2  1.5
Pin ( dc ) = VCC  m  = = 14.32
 A  
11.25
= = 78.5%
14.32

Problems

01. A power amplifier delivers 50W output art 50% efficiency. The ambient temperature is 250 C . If the maximum allowable
function temperature is 1500 C , then the maximum thermal resistance is ______ 0 C / W
(A) 3.6 (B) 2.5
(C) 1.2 (D) 5.1

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 Analog Electronics (Vol-3)

02. What is the maximum power rating of power BJT?

(A) 18 W (B) 15 W
(C) 25 W (D) 10 W

03. An amplifier has a d.c. power supply of 15V and draws a current of 10mA. It produces an output of 5V peak across a
load resistance of 600  for a signal frequency of 1 kHz. What will be it’s a.c. power output?
(A) 260 mW (B) 20.8 mW
(C) 520 mW (D) 40.6 mW

04. Match List – I (Type of Amplifier) with List – II (Property) and select the current answer using the code given below the
lists:

List – I
A. Single ended Class A
B. Class AB push pull
C. Class B push pull
D. Class C.
List – II(efficiency)
1. Medium efficiency with minimum distortion.
2. High efficiency with crossover distortion.
3. Harmonic generator with highest possible conversion efficiency.
4. Poor conversion efficiency with minimum distortion.

A B C D
(A) 2 3 4 1
(B) 4 1 2 3
(C) 2 1 4 3
(D) 4 3 2 1

05. Where does the operating point of a Class –B power amplifier lie?
(a) At the middle of A.C load line
(b) Approximately at collector-cut off on both the d.c and a.c load lines.
(c) Inside the collector cut –off region on a.c load line.
(d) At the middle point of d.c load line

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 Analog Electronics (Vol-3)

06. Consider a emitter follower shown in the figure below. The output signal is 4sin  t volts the power dissipated by the
transistor M. Is ________ mw

(A) 20 (B) 30
(C) 40 (D) 50

07. Consider the push pull stage shown in the figure

Calculate the power dissipated in transistor M1. (in mw)

(A) 368 (B) 452
(C) 512 (D) 364

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 Analog Electronics (Vol-3)

Type 12 – Operational Amplifier [Op-Amp]

For Concept, refer to Analog Electronics K-Notes, Op-Amp

 Common Mistake / Point to remember

• In op-amp negative feedback application, we can analyze the network using virtual ground so try & use
basics such as KVL & KCL to analyze such networks.
• For non-linear applications, precision diode & active rectifiers should be analyzed.

Sample Problem

Given that the op-amps in the figure are ideal, the output voltage V0 is

(A) (V1- V2) (B) 2(V1- V2)

(C) (V1- V2)/2 (D) (V1+V2)

Solution: (B) is correct option

Voltage at “-” terminals of OP-Amp are also V1 & V2 by virtual ground concept.

I=
( V1 − V2 )
2R

V− = V2 − IR = V2 −
( V1 − V2 )  R = (3V2 − V1 )
2R 2

V+ = V1 + IR = V+ = V1 +
( V1 − V2 )  R = (3V1 − V2 )
2R 2
Apply super position theorem
If only V+ is present

Va =
V+
=
(3V1 − V2 )
2 4
(3V1 − V2 )
(
V0 = 1 + 1
1 )V
+ =
2
If only V− is present

V0 = −1  V− = −
(3V2 − V1 )
1 2

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 Analog Electronics (Vol-3)

 V0 =
(3V1 − V2 ) − (3V2 − V1 )
2 2
V0 = 2 ( V1 − V2 )

Problems

01. If the differential voltage gain and common mode voltage gain of a differential amplifier are 100 dB and 10 respectively,
then its common mode rejection ratio is
(A) 110 dB (B) 90 dB
(C) 80 dB (D) 10 dB

02. For the op-amp circuit shown below, the value of Io is

(A) 0 mA (B) 2 mA
(C) 10 mA (D) 12 mA

03. For the OP-amp shown below, the gain

(A) -8 (B) 13
(C) 5 (D) -10

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 Analog Electronics (Vol-3)

04. The output (V0) in the circuit shown in fig, assuming the op–amps as ideal

(A) 3 V (B) 6 V
(C) 9 V (D) 12 V

05. In the given circuit, if the voltage inputs V- and V+ are to be amplified by the same amplification factor, the value of R
should be

(A) R=33k (B) R=12k

(C) R=58k (D) R=22k

06. The circuit below is at steady state before the switch opens at t = 0. The V
C
( t ) , for t > 0 is

(A) 10 − 5e
− 12.5t V (B) 5 + 5e
− 12.5t V

(C) 5 + 5e
−t 12.5t V (D) 10 + 5e
−t 12.5t V

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 Analog Electronics (Vol-3)

07. An op – amp has a slew rate 5V s . The largest sine wave output voltage possible at a frequency of 1 MHz is
(A) 10 Volts (B) 5 Volts
5 5
(C) Volts (D) Volts
 2

08. The value of V , for op – amp circuit shown below is

0

(A) -2 V (B) -1 V
(C) -0.5 V (D) 0.5 V

09. An op-amp with input voltage Vi1 = 150V, Vi2 = 140V and if the differential amplifier has a differential gain of
Ad = 4000 and the value of CMRR is 100. Then the output voltage of op-amp is ______________ (mV)

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 Analog Electronics (Vol-3)

Type 13 – Op-Amp Applications

For Concept, refer to Analog Electronics K-Notes, Op-Amp

 Common Mistake / Point to remember

Remember virtual ground should not be applied with positive feedback.

Sample Problem

In the given figure, if the input is a sinusoidal signal, the output will appear as shown

Solution: (C) is correct option

Since there is no feedback in the circuit and ideally op-amp has a very high value of open loop gain, so it goes into saturation
(output is either +V or −V) for small values of input. The input is applied to negative terminal of op-amp, so in positive half
cycle it saturates to −V and in negative half cycle it goes to +V

Sample Problem

For the voltage regulator circuit shown, the input voltage (Vin) is 20 V ± 20% and the regulated output voltage (Vout) is 10 V.
Assume the op-amp to be ideal. For a load RL drawing 200mA, the maximum power dissipation in Q1 (in Watts) is ________.

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 Analog Electronics (Vol-3)

Ans: 2.8056
Solution:
Given Vin : range from 16V to 24V and V0 = 10V
PD = VCE  IC
PD = ( VC − VE )  IC

(
PDmax = VCmax − VE  IC )
( VC = Vi and VE = V0 )

( )
PDmax = Vinmax − V0  IC …………(1)

from virtual ground

V1 = 4V
Since no current will flow in op-amp terminals
V1 4
I1 = = = 0.4mA
R 2 10k
IC = I1 + IL
IC = 0.4mA + 200mA = 200.4mA
IC = 200.4mA
Putting I C in equation (1)

( )
PDmax = Vinmax − V0  IC = ( 24 − 10 )  200.4m
PDmax = 2.8056watt

Problems

01. The op-amp circuit shown below behaves as a

(A) High Pass filter

(B) Band Pass filter

(C) Integrator

(D) All Pass filter

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 Analog Electronics (Vol-3)

02. In the Op – Amp circuit shown in fig, If R1 = R2 = RA & R3 = R4 = RB, the circuit acts as

(A) Sub tractor (B) Integrator

(C) High pass filter (D) Narrow band pass filter

03. The O/P voltage for the circuit shown in Fig.

(A) 1 V (B) 6 V
(C) 11 V (D) 2 V

04. The circuit connections of OP AMP given in figures (i) and (ii) represent

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 Analog Electronics (Vol-3)

(A) Logarithmic amplifiers for both figures (i) and (ii)

(B) Detectors for both figures (i) and (ii)
(C) Detector for figure (i) and logarithmic amplifier for figure (ii)
(D) Logarithmic amplifier for figure (i) and detector for figure (ii)

05. In the circuit shown, the switch, S is closed when input voltage is positive and open otherwise. The circuit is a

(A) Voltage Follower (B) Half wave Rectifier

(C) Full wave Rectifier (D Level Shifter

06. Consider the following circuit.

If the op-amp is ideal and V0 = −12V , then the value of n will be __________.

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 Analog Electronics (Vol-3)

Type 14 – Sinusoidal Oscillator Circuits & 555 timers

For Concept, refer to Analog Electronics K-Notes, Oscillator Circuits

 Common Mistake / Point to remember

Instead of memorizing formulas for Schmitt Trigger better solve Oscillator circuit from scratch. Oscillators
must satisfy the Barkhausen criteria.

Sample Problem

An ideal op-amp circuit and its input wave form as shown in the figures. The output waveform of this circuit will be

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 Analog Electronics (Vol-3)

Solution: (D) is correct option

Given that Vsat=6V, and - Vsat=-3V
Where V0=+6V, the potential at non-inverting terminal is
 R2  1
VUTP = + Vsat   = 6   = 2V
 R1 + R 2  3
At instantaneous value of Vi=2V, V0=+6V
VUTP  Vi  V0 = +6V
If
VUTP  Vi  V0 = −3V
When V0=-3V, the potential at non-inverting terminal is
1
VLTP = −3   = −1V
3
when
VLTP  Vi  V0 = −3V
VLTP  Vi  V0 = +6V

Sample Problem

The oscillation frequency and the condition to sustain the oscillations are:-

Solution:
It is Wein bridge oscillator
1 1 1
Oscillation frequency  = = =
RR'CC' R ( 2R ) C ( 2C ) 2RC

1
Loop Gain:- A  1 and  =
2RC
R
=
R + 2R + 2R
1
Z1 = 2R + = 2 (R − jR ) C = 1 
jC  2R 

R+ 1 R2
2 jC j
Z2 = =
R+ 1 R − jR
2 jC
Z2 1
= =
Z1 + Z 2 5

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 Analog Electronics (Vol-3)

A  1
A 5
R1
1+  5; R1  4R2
R2

Problems

01. For the Schmitt trigger circuit shown below, assume that op-amp and diodes are ideal. Then the values of the input
voltage for positive going and negative going of hysteresis loop are

(A) − 5.5 V and 1.385V (B) 5.5 V and −1.385 V

(C) −1.2 V and 10.67 V (D) 1.2 V and −10.67 V

02. In a Schmitt trigger the output v0 is limited by Zener diodes. Signal vS is connected to the negative input terminal (v_)
and v+ =  v0. The Hysteresis voltage is 1 volt. Triggering takes place for signals going through
(A) zero volt (B) 0 volt and + 1 volt
(C) 0 volt and – 1 volt (D) + 0.5 volt and – 0.5 volt

03 In a Schmitt trigger using OP amplifiers the output is limited by Zener diode clipper to v 0 =  8 volts. The positive
input terminal voltage v+ =  v0, where  = 1/8. The signal vs is applied v_. The following statements (1) to (4) are made
regarding vs and v+.
1. For vS negative and rising v+ = + 1
2. For vS positive and decreasing v+ = + 1
3. For vS decreasing through zero value v+ = +1
4. For vS increasing through zero v+ = +1
Of these statements, the true statements are
(A) 1 and 3 (B) 2 and 3
(C) 1 and 4 (D) none of these statements

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 Analog Electronics (Vol-3)

04. The circuit of Schmitt trigger of fig., the hysteresis VH is Assume if Vi < V1, V0 = + 5V.

(A) 0.10V (B) 0.25V

(C) 0.15V (D) 0V

05. Figure shows an oscillator circuit designed to generate a frequency f = 40KHZ; operation amplifier with a supply of =
±10V and 100mH inductor are used. Determine the value of C2 for C1 = 10C2.

(A) 177PF (B) 182PF

(C) 147PF (D) 132PF

06. The value of C required for sinusoidal output of 1KHz is

1
(A) F
2
(B) 2F

1
(C) F
2 6
(D) 2 6F

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 Analog Electronics (Vol-3)

07. A crystal has the following parameters L = 0.33H,C = 0.065pF,C = 1pF,R = 5.5k
(1) By what percent does the parallel resonant frequency exceed the series resonant frequency?
(A) 2.3 (B) 3.3
(C) 4.5` (D) 1.3

(2) Q to Crystal
(A) 451 (B) 560
(C) 410 (D) 201

08. For a given circuit L1 = L2 = 10F,C = 2pF , identify the oscillator and find out the oscillation frequency

(A) Hartley Oscillator, f=25.18MHz (B) Hartley Oscillator, f=158MHz

(C) Colpitt Oscillator, f=25.18MHz (D) Colpitt Oscillator, f=358MHz

09. A phase shift oscillator operates at a frequency of 5KHz. The phase shift oscillator will have produce value of RC as
(A) 11.9 sec (B) 12.9 sec
(C) 13.9 sec (D) 14.9 sec

10. The given figure shown the application of 555 timer circuit as an astable multi-vibrator. The charging and discharging,
time constants are respectively

(A) R1 C and R2 C (B) R1 C and (R1+R2) C

(C) (R1+R2) C and R1C (D) R2 C and R1 C

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 Analog Electronics (Vol-3)

11. Assertion (A): A monostable multivibrator can be used to alter the pulse width of a repetitive pulse train.
Reason (R): Monostable multivibrator has a single stable state.

(A) Both A and R are true and R is the correct explanation of A

(B) Both A and R are true but R is NOT the correct explanation of A
(C) A is true but R is false
(D) A is false but R is true

12. The function of the diode D in the timer circuit shown above is to

(A) Increase the charging time of C (B) Decrease the charging time of C
(C) Increase the discharging time of C (D) Decrease the discharging time of C

13. A Schmitt trigger circuit is shown below. The upper and lower threshold voltages are respectively

(A) 2V, -4V (B) 2V, -2V

(C) 4V, -4V (D) 4V, -2V

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 Analog Electronics (Vol-3)

Solutions

Type 1 – Diode Basics and Diode Circuit Analysis

01. Ans: (B)
Solution: Given Vr = 0.7V

Assume both D1 & D2 are ON, thus in this condition we must end up with I1  I2

Now,
10 − 0.7
I1 = = 1.86mA...................(A)
5K
And in 2nd loop, Applying KVL
−0.7 + 0.7 + 10K  I2 − 10 = 0

I2 = 1mA...................(B)
From (A) and (B) it is clear that I1  I2 . i.e. our assumption is true, thus

ID1 = I1 − I2 = 0.86mA

02. Ans: (B)

Solution: This problem is based on the concept of back to back zener diode application when diode D2 will be effective, it
will result total O/P at the level
V0 = VZ D2 + VD1 = 5 + 0.7 = 5.7
f.b

Similarly when D1 will be effective, it will result total O/P at the level
V0 = − ( VZD1 + VZD2 ) = − (5 + 0.7 ) = −5.7V

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 Analog Electronics (Vol-3)

Thus, transfer characteristics curve will look like

The line segment between -5.7V & 5.7V is straight line, because in this range of i/p zener diode will be out of breakdown
region, hence will act like a simple reverse diode and will be open circuited.

03. Ans: (C)

Solution: Given IS = 0.1A,VT = 36mV,  = 2
Applying KVL, we will have
−15 + VD1 + VD2 + IS  100k = 0

VD2 = 15 − VD1 − IS  100k...............(A)

Also VD1 can be calculate using forward bias diode current equation, i.e.
 VD1 
ID1 = IS  e T − 1 
V

 
 
VD1
VT
 ID1 = IS  1 = e −1

VD1 = VT ln2 = 2  26ln2 = 36.043mV

Putting VD1 in equation (A)

( ) ( )
VD2 = 15 − 36.043  10 −3 − 0.1  10 −6  100  103 = 15 − 0.036043 − 0.01 = 14.953Volt

04. Ans: (B)

Solution: For Vi  0 , D1 & D2 will be off thus V0 = 0...................(1)
For Vi  0 , D1 will be on, status of D2 will depend on the I/P voltage level.
i.e. D2 will be off if VA  10V i.e.

10 V
VA = Vi  = i  10
10 + 10 2
Vi  20
Vi
Thus V0 = for 0  Vi  20..............(2)
2

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 Analog Electronics (Vol-3)

For Vi  20 both D1 and D2 will be on, thus

V0 = 10V

Vi = 5V

05. Ans: (A)

Solution: The voltage across the anode terminal of diode D 1 , is less than the voltage across diode D 1 is less than the
voltage across cathode terminal.

Therefore, V  V
c A
Diode D 1 reverse biased i1 = 0
5−3
Therefore D 2 is forward biased, and i2 = = 4mA
500

06. Ans: (B)

Solution: Assume D 2 is on other diodes are off
10 − 0.7
Then ID = = 0.93mA
2
10K
V0 = 10 − 9.5  0.93 = 1.165V
Since voltage across D is positive then it is also on,
3
So assume both D & D are on then
2 3
5 − 0.7 − 0.7
ID = = 7.2mA
2
0.5K
V0 = 5 − 0.7 = 4.3V

Since voltage across D is negative then it is off,

1

Diodes D & D are ON. As D ON and so D is OFF.

2 3 3 1

Hence V = 5 − 0.7 = 4.3V

0

07. Ans: (A)

Solution:
In given configuration Apply OC test
For D1 ; VA<VC hence D1 is OFF
And For D2 ; VA>VC hence D2 is ON

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 Analog Electronics (Vol-3)

The given circuit is redrawn as

Req = 2.2k + 6.8k || 2.2k = 3.86k

10
I= = 2.59 mA
3.86k
V0 = I  ( 6.8k || 2.2k ) = 4.3V

08. Ans: 10
Solution:
For +Ve half cycle 0  t  
Apply OC test
For D1 ; VA>VC hence D1 is ON
And For D2 ; VA<VC hence D2 is OFF
10
 I AB1 = sin t
10k
IAB1 = sin t mA
For –Ve half cycle   t  2
For D2 ; VA>VC hence D2 is ON
And For D1 ; VA<VC hence D1 is OFF
10
 I AB2 = sin t
10k
IAB2 = sin t mA
For here I AB = sin t mA For all t
VAB 10sin t
R AB = = = 10k
I AB sin t  10 −3

09. Ans: 13.42

Solution:
When S is open, Vo = 3V which gives cut in voltage (V), of the diode is 0.75V and when S is closed output voltage will not
be effected because Vo = 3V but current flowing through diodes will be effected

when S is open
20 − 3
I= = 17mA
1k
when S is closed

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 Analog Electronics (Vol-3)

20 − 3 3
I= − = 15.5mA
1k 2k
We need to compute dynamic resistance under S is closed hence

VT 2  26mV
rd = = = 3.35
I 15.5mA

The incremental resistance = 4rd = 13.42

Type 2 – Rectifiers and Filters Circuits

01. Ans: (D)
Solution: The circuit is that of a bridge rectifier. For proper functioning, the PIV of diodes must be at least greater than v 0
and since, the current through any path flows through 2 diodes. There is a drop of 1.4 V.

02. Ans: (B)

Solution: The right diode conducts during the positive half of the input cycle and the left diode conducts during the negative
half of the input cycle. Hence, the output will be a fully rectified wave.

Type 3 – Voltage Regulators and Wave Shaping Circuits

01. Ans: (B)
Solution: For the given range of Vi (40-50)V, I 0 will be maximum for Vi = 50V

Vi − Vz 50 − 6.2
i.e. I0 = = = 43.8mA
1K 1K
also, I0 = I z + IL

IL = I0 − I z
for maximum IL ,I z should be minimum & IZmin = 5mA

ILMax = 43.8 − 5 = 38.8mA

02. Ans: (C)

10 − Vz 10 − 5
Solution: Is = = = 50mA
100 100
also, IS = IL + I Z

IL = IS − I Z
Thus for maximum IL ,I Z should be minimum

i.e. IZ = I ZK = 10mA

 ILMax = 40mA
Now, to calculate minimum power rating of zener diode 1st we will have to find the maximum current that can flow through
the zener diode, in the given circuit, maximum current will be when IL = 0 i.e. No load

 I ZMax = IS − IL No Load = IS − 0 = IS = 50mA

 Pmin = VZ I Z max = 0.25W

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 Analog Electronics (Vol-3)

03. Ans: (B)

Solution:

The circuit shown is a clamper circuit. Now at steady state the diode D must be open and for diode to be open, voltage at A
should not go above -2V. Thus O/P wave form will look like V0 = VA

04. Ans: (B)

Solution: Both D1 & D2 will be off if

VA  8 and VA  4

i.e. for 4  VA  8 V0 = Vi

now if Vi  4 i.e. V0 = 4V

and if Vi  8 i.e V0 = 8V

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 Analog Electronics (Vol-3)

05. Ans: (B)

Solution:

Case 1:- Assuming D1 is off thus D2 must be ON

Thus using voltage divider rule
10  10 + 20  2.5
V0 = VA = = 5V............(A)
10 + 20

Case 2:-
Now, let’s finding the condition on Vi up to which D1 is off, i.e. as Vi will increase above that level D1 starts conducting

Thus D1 to just start conduction, I1 → 0 now applying KVL we have

Vi = 2.5 + 10 ( I1 + I 2 ) ................(1)

Also Vi = 10 − 20I2 ...........(2)

(1)  2 + (2) we get

3Vi = 15 + 20I1

15
Now, as I1 → 0 Vi → = 5V
3
i.e. D1 will become ON as Vi will go above 5V and hence in this case

V0 = V.............(ii)
i
Vi  5V
Case 3:-As of case (2) V0 = Vi for Vi above 5V, but this will be true for all Vi above 5V. as the diode D2 will go off if Vi will

increase above 10V. thus case 2 is valid to 5  Vi  10 and for Vi  10 V0 = 10V.............(iii)

Thus, transfer characteristics will look like

From fig. it is clear that, 1st break point occurs at

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06. Ans: (B)

Solution: It is a Two level clipper
During the positive half cycle of the sinusoidal input voltage, the diode D 2 is OFF and D 1 is also OFF until Vi is greater
than 6 Volt.
When Vi  6 volt, the diode D 1 conducts, So then at the output the upper portion of 6 volt will be clipped off.
Similarly during negative half cycle the diode D 2 is ON when Vi  −4V
So in a similar way the portion below -4 volt will be clipped off and the output voltage waveform will be similar as presented
in the alternative.

07. Ans: 0.5

Solution: Source current
24 − 15 100
IS = = mA
270 3
15
IL =
RL
IS = I Z + I L
When R L is minimum, IL will be maximum, I Z will be minimum
15 100
+ ILmin = m
RLmin 3
15  100 10 
= −  mA = 30mA
RLmin  3 3 
15
RLmin = k = 0.5k
30

Type 4 – DC Analysis & Biasing Circuits of BJT

01. Ans: (C)
Solution:
Let transistor is active region
Assume VBE = 0.7V
30 − 0.7
IE = = 1.95mA
15
IE = IC (If  large)
Apply KVL
20-5IC – VCE – 15IC+30=0
VCE= 50-20  1.955 = 10.9V

02. Ans: (B)

Solution:
For fixed bias stability (S) =  + 1
 +1
For self bias stability (S) =
 RE
1+
RB + RE
 (S) self bias < (S) fixed bias
 S  1 always

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 Analog Electronics (Vol-3)

03. Ans: (C)

  
Solution: Ic   IE
 +1
Ic IE = 1mA

Thus,
5 − V0 = Ic  1K

 V0 = 5 − 1 = 4V

04. Ans: (C)

Solution: Given β=100
2
Vx  10 2V..............(i)
2+8
 VE = Vx − 0.7 = 1.3V
VE
Thus, IE = = 1.3mA
1K
Since β=100
IC IE = 1.3mA
Now, we can write
10 = 2  IC + VCE + 1  IE

VCE  10 − 3Ic  6.1V

DC equivalent circuit
05. Ans: (B)
Solution: Drawing Thevenin’s equivalent circuit,
−10  10 + 20  5 10
Vth = = 0V and R th = (10 || 5 ) k = k
10 + 10 3
Applying KVL,
10 = 0.7 + R thIb + (  + 1 ) Ib  10K

9.3 = (R th + 101  10K ) Ib

100  9.3
 I c =  Ib = = 0.917mA
10
+ 101  10
3
+1
Now, VCE = 30 − 10I C − 10IE Where IE = I
 c
101
VCE = 30 − 9.17 − 9.17  = 11.56V
100

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 Analog Electronics (Vol-3)

06. Ans: (D)

20 − 10
Solution: I = = 10mA
1K
also, VBE = 0.7  10 − V0 = 0.7
V0 = 9.3V
VCE = 20 − V0 = 10.7V

07. Ans: (A)

Solution: The given circuit is in fixed bias stabilization method. Apply KVL to outer loop then
V −V
V − I R − V = 0, R = CC CE = 6 − 3 = 3  1000 = 2k
CC C C CE C I 1.5mA 1.5
C
And we know that I = I
C B
I 1.5mA
I = c = = 10A
B  150

Apply KVL to inner loop

V − I R − V = 0. or active region V = 0.7
CC B B BE BE
V −V
R = R = CC BE = 6 − 0.7 = 0.53  106 = 530K
B 1 I 10A
B
Then, given  is changed from 150 to 200.

So, I =  I = 200  10A = 2mA

c B

By applying KVL to outer loop we can get V

CEQ
V −I R −V =0V = 6 − 2  2 = 6 − 4 = 2V
CC C C CEQ CEQ

08. Ans: (B)

Solution: I = 1mA;  = 50
E
 50
I = I =  1mA = 0.98mA
C  + 1 E 51
V = I R − 9 = 0.98  4.7 − 9 = −4.394V
C C C
I 1mA
I = E = = 19.6A, V = V −V
B  +1 51 EB E B

 V = V + V = 0.7 + 50  19.6  10 −3 = 1.68V

E EB B
 V = V − V = 1.68 − ( −4.394 ) = 6.074V
EC E C

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 Analog Electronics (Vol-3)

09. Ans: 0.7825

Solution:
Step (1):

KVL for B-E loop:

0 − IBRB − VBE − IERE + VEE = 0

IBRB + (1 +  ) IBRE = VEE − VBE

5 − 0.7
IB = = 8.3A
10k + 101  5k

IC = IB = 0.835 mA
Step (2):
KCL at node ‘C’
I = IC + IL
12 − V0 V0
= 0.835m +
5k 5k
1 1
2.4m − 0.835m = V0  + 
 5k 5k 
1.56m  5k
 V0 = = 3.9125V
2
V0
IR = = 0.7825 mA
5k

10. Ans: (B)

Solution:
Assume BJT in active region and we neglect ICBO and drawing Thevenin’s equivalent at input side
−12  15k 5  100k
VTh = + = 2.78V
115k 115k
15k  100k
R th = (15k || 100k ) = = 13k
115k
Ic = Ib .................. (i)
Vth − VBE
Ib =
R th
2.78 − 0.7
But Ib = = 1.6A
13  103
Using Ib in eq. (i) with  = 30
Ic = 4.8mA
VCC − VCE
But Ic =
RC
But VCE = 12 − 2.2k  4.8m = 1.44
As VCE  0.2V
BJT is in active region

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 Analog Electronics (Vol-3)

Type 5 – Small Signal Analysis of BJT and Single Stage BJT Amplifier
01. Ans: -238.50
Solution: To find out re, Use DC Analysis

IB =
VCC − VBE
=
(12 − 0.7 ) = 51.36A
RB 220  103
IE = (1 +  ) IB = 61  51.36 = 3.13mA ;

VT
re = = 8.31
I
Using re Model voltage gain Formula
R C || r0
AV = − = −238.50
re

02. Ans: 498-199

Solution:
Using Hybrid π Model
The equivalent circuit is as shown
Vri 
−V =
270 + r
v ir
VTH = −gm v r0 − v  = − v  ( gmr0 + 1 ) =
270 + r
(g r
m 0
+ 1)

Now, gmr =  = 100

100 100
r = = k = 50k
gm 2

v i 50k ( 2m  250k + 1 )
VTH = = 498v i
270 + 50k

03. Ans: (C)

Solution: Drawing the  − r model for transistor
At C we can write
V0 = − ( I0 +  Ib ) RL .................(i)
Also we can write
V0 − VB
= I0  V0 − 0 = I0RB
RB
Putting in equation (i)
V0 = −I0RL + ( − IbRL )
RL
V0 = −V0 + ( −IbRL )
RB
 R 
V0 1 + L  = −IbRL
 RB 

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 Analog Electronics (Vol-3)

RL .RB
V0 = −Ib ....................(ii)
RL + RB
Now, Applying KVL from B to G
0 = r Ib + (  + 1 ) IsR s + Vs

( )
Given r = 0  Vs = −  + 1 R s Ib ..............(iii)

V0  R LR B
Thus A v = =
Vs (R L
+ RB )(  + 1 ) R s
Since β is very large
R LR B
Av =
(R L + R B ) R s
also, RB  RL  RL + RB RB
RB  RL RL
Av =
RB .R s Rs
1k
Av = = 20
50

04. Ans: (A)

Solution: Converting into h parameter model, circuit will become

h 150
Here current gain A = − fe =− = −100
I 1+h R 20
oe L 1 +
40
05. Ans: (B)
Solution:
Resistance seen between base and ground will be
For this we have perform AC analysis:-
For that we have to find out value of r and gm from  model
DC Analysis: Base Emitter Loop:
(500k ) I B
+ VBE + ( I C + IB )  1k − 12 = 0

IC = IB
(500k ) I B
+ VBE + 101IB  1k − 12 = 0

IB = 18.8A
IC = 1.88mA
IC
gm =
VT

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 Analog Electronics (Vol-3)

  VT 100  25
r =  = = = 1.33k
gm IC 1.88
 -Model:-
V
Ri = i
IB
Vi = IBr + (1 +  ) IB (1k )
Vi
= R i = 101k + 1.33k
IB
Ri = 102.33k

06. Ans: (B,D,A)

Solution:
DC Analysis:-
1.2V − 0.7
IB =
50k
IB = 0.01mA
IC = IB = 1mA
VCEQ = 12V − 6k  1mA = 6V
ICQ 1mA
gm = = = 38.5mA V
VT 26mA
100
r =  = = 2.6k
gm 38.5mA V
AC analysis:-
Early voltage given r0 = 
R C  r
AV = −gmRL ; RL =
r + RB
 6k  2.6k 
A V = −38.5   
 50k + 2.6k 
AV = −11.4

07. Ans: (A)

Solution:
The AC equivalent circuit using
millers theorem

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 Analog Electronics (Vol-3)

IL −I C
AI = = = −hfe
Ib Ib
AI = −hfe = −100
Zi = hie = 1 k
Vc ILRL −A IRL
AV = = = = −476.2
Vb Z i Ib Zi
RB 100  103
Then = = 209.56
1 − AV 477.2
RB 209.56  103
Z it = || Z i = = 173.25
1 − AV 1209.56
 Zt   173.25 
A = AV  t i  = −476.2   = −15.94
 Z +R  5173.25 
 i s 
A = 15.94

08. Ans: −232.196

Solution:
Case (i):
DC equivalent of the given circuit.
11k
VTh =  12 = 3V
44k
R TH = 11k || 33k = 8.25k
KVL for B-E loop:
3 − 0.7
IB = = 10.88 A
8.25k + (1 +  ) 1.01k
IC = IB = 2.177 mA
IC 2.177 mA
gm = = = 87.08 m
vT 25 mV
hfe 200
hie = = = 2.2967 k
gm 87.08 m

Case (ii):
Small signal model of the given amplifier

Step (1):
V0 = −hfeib 5k
Step (2):
Vi = ib hie + (1 + hfe ) 10 

Step (3):
V0 −200  5k −200  5k
AV = = =
Vi 2.2967k + 201  10 4.3067k
 AV = −232.196

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 Analog Electronics (Vol-3)

Type 6 – DC Analysis and Biasing Circuits of MOSFET

01. Ans: (D)
Solution:

02. Ans: (A)

Solution: Given Vt = 2V and Vgs = Vds , thus system will be in saturation

( )
2
i.e. ID  Vgs − Vt

(V )
2
gs
− Vt
2mA Vgs = 3V
=
ID
( )
2
Vgs − Vt
Vgs = 4 V

( 4 − 2)
2

 ID = 2 = 8mA
(3 − 2)
2

03. Ans: (B)

Solution: Given IDSS = 1mA,Vp = −1V . It is given that quiescent to ground voltage is 10V, that mean

VD − 0 = 10

VD = 10V

24 − VD 14
 ID = = = 0.25mA
56 56

04. Ans: (B)

Solution:
Given data: VP = – 10V. IDSS = + 40 mA and VGS = – 5V
2 2
 VGS  −3  5 
IDS = IDSS  1 −  = 40  10  1 − 
 VP   10 
IDS = 10 mA
 RS Required for self bias an N – channel JFET is:
−VGSQ 5
RS = =
IDS 10  10−3
RS = 500 

05. Ans: (A)

Solution:
Since VG1 = VD1 ,Q1 is in saturation.

Q2 is also in saturation, iD1 = iD2 .

So,
5
VGS1 = VGS2 = = 2.5V
2

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 Analog Electronics (Vol-3)

Saturation current
1 W
ID = nCox  V − VT2 
2 L  GS 
1 100
( 2.5 − 1 ) = 5.625mA
2
I1 =  50 
2 1
Q 3 and Q4 have the same drain current,
So VGS3 = VGS4

(assuming Q 3 and Q4 are saturated)

VGS3 = VGS1
I2 = IGS = 5.625mA
V2 = 5 − 2.5 = 2.5V

06. Ans: (D)

Solution:
Step 1:
IS = IG = 0 [ IG = 0 in MOSFET]
1 2

 IDSQ1 = IS = 0 mA
1

[∵ ID = IS in MOSFET]
Step 2:
In a MOSFET, ID will be almost zero, when the channel is pinched off.
  VGS 
2

(i.e.) VGS = VP = −4V  ID = IDSS  1 −  
  VP  
  
07. Ans: 4
Solution:
In saturation

( )
2
IDS = k Vgs − VT

Since, VDS = 0 [i.e., drop across the MOSFET]

Vgs − VT = 0 [ in saturation region]

Or, Vgs = VT

Thus, Vg − Vs = 2

Vs = Vg − 2 = 10 − 2 = 8V

 V0 = 8 [ drop across the MOSFET=0]

20 − 8
 iD = = 6mA
2k

8−4
Current through source = + i = iD [Where iD is the drain current]
2k
i = 4mA

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 Analog Electronics (Vol-3)

Type 7 – Small Signal Analysis of MOSFET and Single Stage MOSFET Amplifier
01. Ans: (A)
Solution: Given IDSS = 8mA,rd = 90k,Vp = −6V
Step 1:- DC analysis of circuit

We can write
 10 
VG =    16 = 1.6..............(i)
 10 + 90 
V
Also ID = S = x mA
1K
2
 Vgs 
ID = IDSS  1 − 
 Vp 

2
2
 1.6 − x   6 + 1.6 − x 
x = 8 1 −  = 8
 ( −6 )   6 
2
36x = 8 7.6 − x 
2
4.5x = 7.6 − x 

x2 + 7.62 − 2  7.6x − 4.5x = 0

x2 − 19.7x + 57.76 = 0

19.7  19.72 − 4  57.76 19.7  157.05

x = =
2 2
 x = 3.584,16.11

Since x cannot be 16.11 [Vcc=16]

 x = 3.584  ID = 3.584mA

Now, calculating gm

−2IDSS  Vgs  −2
gm = 1 −  or I .I
VP  VP 
 VP D DSS

2
gm =  8  3.584 = 1.784m
6

Step 2:-AC analysis

V0 = −gm Vgs (rd || 2.1 )

V0 90  2.1
 Av = = −gm (rd || 2.1 ) −gm  −3.65
Vgs 92.1

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 Analog Electronics (Vol-3)

02. Ans: (C)

Solution:
Small signal equivalent circuit
RD = 10k

RS = 3k

gm = 2 k p IDQ = 0.447mA V

V0 = +gm VsgRD ........... (1 )

Vi = −VSG − gm VSGR S ........... ( 2 )

V0 −gmRD
AV = =
Vi 1 + gmR S

AV = −1.91

03. Ans: (A)

Solution:
Small signal model:-

gmD = 2 K nD IDQ = 2 1 ( 0.2 ) = 0.894 mA

V

r0D = r0L = 1 = 500k

IDQ

V0 = −gm Vgs (r0D || r0L )

V0 mA
AV = = −gmD (r0D || r0L ) = −0.894  (500K || 500K )
Vgs V

AV = −224

04. Ans: (B)

Solution:
DC Analysis:-

gm = 2 IQk n

gm = 2 0.5  10 −6 = 0.414mA V

ID = IQ = 0.5mA

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 Analog Electronics (Vol-3)

AC Analysis:-

V0 = −gmVgsRD
V0
AV = = −gmRD = −9.9
Vgs

05. Ans: (B)

Solution:
RD
Voltage gain of MOSFET common-source Amplifier is AV = −
rD + RD
Here µ = Amplification factor = gmrd
rd = Drain resistance
RD = Load Resistance at drain

gmrdRD
AV = - = −gmRD ( rd > > RD)
 R 
rd  1 + D 
 rd 
|AV| = gmRD

06. Ans: -9.9

Solution:
Small signal circuit is
V0 = −gmVgsRD
Vgs = Vi

V0
= gmRD
Vi

1 W
gm = 2 IDk n = 2 ID C = 2 1m  0.5m = 1.414m
2 n ox L
V0
AV = = −gmRD = −1.414  10−3  7  103 = −9.9
Vi

Type 8 – Frequency Response of BJT & MOSFET Amplifier (ECE)

01. Ans: (B,B)

Solution:

AC Analysis:-

R ib = r + (1 +  ) RE = 9.3k + 101  0.4

Rib = 9.5k + 40.4k

Rib = 50k

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 Analog Electronics (Vol-3)

Coupling always offer lower cut-off frequency

1
fL =
2CC R S + R i 

Ri = R1 || R2 || Rib
fL = 2.198Hz

02. Ans: (A)

Solution:
By pass capacitor CL always provide upper cut-off frequency:
1 1
f3dB = = = 2.39MHz
2CL (RL || RD ) 2  10  10 (10k || 20k )
−12

03. Ans: (C)

Solution:
1
f =
(
2r C + C )
fT = ( 2 − 1 f )
  100  26
r = = V = = 2600
gm IC T 1
1
f = = 24.5MHz
2  2600 ( 2.5 )  10 −12

fT = 2 − 1f = 2.45GHz

Type 9 – Multistage and Differential Amplifier

01. Ans: (C)
Solution:
Overall gain of the multistage amplifier
V4
AV =
Vin
V4 = 50V3
50V2  1000
V3 =
1250
50Vin  1000
V2 =
1250
V4 50  50 50  106
 = 
Vin 1250 1250
 V4   V4 
  = 20log10   = 98dB
 Vin dB  Vin 

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 Analog Electronics (Vol-3)

02. Ans: (B)

Solution:
1 1 1
= 1.1 2 + 2
fH f1 f2

1 1 1
= 1.1 +
fH
(10 ) (2  10 )
2 2
6 6

fH = 0.813MHz

03. Ans: (D)

Solution:
fL
%Tilt =  100%
f0
f0 = 100Hz
1
fL =
2CL ( 3k + 2k )
fL = 3.16Hz
  3.18
%Tilt =  100% = 10%
100

04. Ans: (C)

Solution:
fL
fL* =
1
2 n
−1
1
fL = fL* 2 n
−1
1
fL = 20 2 3
− 1 = 10.2Hz
1
fH* = fH 2 n
−1
f *

fH = H
1
2 n
−1
20k
fH = = 39.23KHz
1
2 n
−1

05. Ans: (B)

Solution:
( )
Rise time tr = 0.35 tp (pulse width)
tr 10
tp = = = 28.6s
0.35 0.35
The high 3-db frequency of amplifier to avoid excessive distortion is:
1
fH = 35 KHz
tr (pulse width)

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 Analog Electronics (Vol-3)

06. Ans: (A)

Solution:
T
Percent tilt or sog (P) =  100
2R1C1
Or
 f 
P =  L   100
 f 
Where f is the frequency of square wave and R1C1 is the time constant associated with the lower 3-dB frequency fL of the
multistage amplifier.
Thus;
  2000
P=  100
f
  2000  100
fmax = = 10kHz
20

07. Ans: (D)

Solution:

tr = 1.1 tr 0 2 + tr 12 + + t r n2

tr 0 : Resistance of multi-stage waveform

tr 1 : At 1st stage output

tr n : At nth stage output

Thus:

( 0.1 ) + (0.5 ) + (1 ) + (2 )
2 2 2 2
tr = 1.1 .10 −6

tr = 2.52 s

08. Ans: (C)

Solution:

For a Single input balanced output Differential amplifier

vo RC
Ad = =
v1 re

VT 25m
re = = = 12.5
IEQ 2m

RC 2k
 AD = − =− = −80
re 12.5

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 Analog Electronics (Vol-3)

Type 10 – Feedback Amplifier

01. Ans: (A)

02. Ans: (B)

Solution:
36
(a) A = = 1285
0.020
1.2
= = 0.012
100
V A 1285
Af = 0 = =
Vi 1 + A 1 + 1285  0.012
V0 = 78.2  0.028 = 2.19V
DH
(b) DHf =
1 + A
7
1=
1 + A
1 + A = 7
 1 + A  7
New input Vi = V0  =  36 = 0.196V
 A  1285

03. Ans: (B)

Solution: Feedback resistor, RF, which is tied between the base and collector of the BJT, samples the output voltage v 0 and
feeds back a current that is then mixed with the source current. Hence the feedback combination is voltage shunt or shunt-
shunt feedback.

04. Ans: (C)

Solution:
dA
Given data : A = -1000,  = -0.1 and = 20%
A
Assume negative feedback
dA f 1 dA 1 20
= =  20% = = 0.2%
dA 1 + A A 1 + 1000  0.1 100

05. Ans: (B)

Solution:
Three Amplifiers each of gain (A0/2) means:
3
A  A 03
That overall gain=  0  =
 2 8
 
Positive feedback gain  = 0.008.
For the system to be oscillatory, it should have satisfy the Barkhausen criteria
i.e. A = -1
A 03
  0.008 = −1
8
A 30 = -1000
A0 =- 10

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 Analog Electronics (Vol-3)

06. Ans: (C)

Solution:
Gm
Gmf = = −1m A
D V
Gm = −50 m A
V
−hfe
Gm = −50 =
R S + hie + R e
−150
Gm =
1 + hie + R e
R e : Emitter resistance
D = 1 + Gm = 1 + 50 Re = 50
Re  1k (  = −R e )
Thus hie = 1K
hfe Vt 150  0.026
IC = = = 3.9 mA
hie 1k
Since sampling is current and mixing is series, so current series feedback

07. Ans: 7.9

Solution:
20
Open loop gain = A = = 2000
10  10−3
10 10000
A CL =  103 = = 25
400 400
A
ACL =
1 + A
A 2000
1 + A = = = 80
ACL 25
A = 79
79
=
1000
79
% =  100 = 7.9%
1000

Type 11 – Power Amplifier (ECE)

01. Ans: (B)
Solution:
Tf − TA 150 − 25
= =
PD 50
 = 2.50 C / W

02. Ans: (A)

Solution:
VCE = VCC − ICRC

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 Analog Electronics (Vol-3)

VCC
IC(max ) = = 3A  VCE = 0 
RL
VCE(max ) = VCC = 24V IC = 0 

PT = VCE IC = IC ( VCC − ICR C )

PT = VCC IC − IC2RC
dPT
= VCC − 2ICR C = 0
dIC
VCC 24
IC = = = 1.5A
2R C 16
VCE at IC = 1.5A = 12V
PT (max ) = VCE(max ) IC(max ) = 12  1.5 = 18watt

03. Ans: (B)

Solution:
V02 (p − p) (5)2
A.C power output P0(ac) = = = 20.8 mW
2RL 2  600

04. Ans: (B)

Solution:
Class – A : Amplifier:
The output current flows during the entire cycle of the ac input signal.
Output power is low, therefore the collector efficiency is less than 50% with least minimum distortion.
Class – B : Amplifier:
It’s collector efficiency is quit high (  78.5%)
The output has much less distortion due to cancellation of all the even harmonic components.
In Class – B Amplifier cross over distortion occurs.

Class – AB : Amplifier:
In this collector efficiency is above 50% and bellow 78.5%. and minimum distortion occurs.
By using Class-AB Amplifier cross over distortion can be removed

Class – C : Amplifier:
In Class – C Amplifier collector efficiency is ( 90%). And maximum distortion occurs.

05. Ans: (B)

Solution:
For Class-B operation the biasing resistor are so adjusted that operating point-Q lies in the cut-off region i.e. approximately
at collector cut-off on both the d.c and a.c load lines

06. Ans: (C)

T
1
T 0 C CE
Solution: Pav = I V dt

VOUT
IC = IE = I0 + ; VCE = −VOUT + VCC
RL

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 Analog Electronics (Vol-3)

T
1  4 sin t 
Pav =   I0 +  (10 − 4 sin t ) dt
T 0 1K 
 V 
Pav = I0  VCC − m  ;
 2 
VCC = 10V; Vm = 4V,
  4 
 Pav = 5m  10 −    = 40 mw,
  2 

07. Ans: (D)

Solution:
T T
1 2
1 2
V 
Pav =
T 
0
VCE IC =
T  (V
0
CC
− Vm sin t )  m sin t 
 RL 
T T
1 2
VCC Vm 1 2
Vm2
Pav =
T 
0
RL
sin t −
T  2R
0 L
dt

VCC Vm Vm2 Vm  VCC Vm 

 Pav = − =  − 
RL 4RL RL   4 

Vm = 4V ; VCC = 6V ; RL = 10

 4  6 4
PAv =    −  = 0.3639 W
M1  10    4

Type 12 – Operational Amplifier [Op-Amp]

01. Ans: (C)

Solution Given Ad = 100dB

A c = 10  A c ( in dB ) = 20log A c = 20dB

Ad
 CMRR =
Ac
And
CMRR ( indB ) = A d ( indB ) − A c ( indB ) = 100 − 20 = 80dB

02. Ans: (D)

12 − 0
Solution: From figure, I1 = = 6mA
2

And I2 = I1 + 4 = 10mA

0 − V0
Also, I2 =  V0 = −10V..............(i)
1K

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 Analog Electronics (Vol-3)

V0 − 0
Thus I3 = = −2mA..............(ii)
5
From figure

I0 = I2 − I3 = 10 + 2 = 12mA

03. Ans: (B)

Solution: Converting  circuit into Y we will have

Applying nodal equation at (1)

1 3  3
Vi  +  − Vx =0
 R 4R  4R

7 3V
Vi = x  7Vi = 3Vx ..................(A)
4R 4R
At Node (2)

 3 3 3 3 3
Vx  + +  − Vi − V0 =0
 4R 4R R  4R 4R

Putting Vx from equation (A)

7  3 + 3 + 12  3 3
V − Vi = V0
3 i 4R  4R 4R

 42 3  3
 −  Vi = V0
 4R 4R  4R

V0 39
 = = 13
Vi 3

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04. Ans: (B)

Solution: Applying nodal equation at node A
1 1  V Vy
1  + + 1 − x − =0
2 2  2 1
V
2 − x − 2 = 0  Vx = 0.................(i)
2

Now applying equation at node (2)

1 1  V V V
Vy  + + 1  − x − A − 0 = 0
2 2  2 1 2

V0
2Vy − 0 − 1 − =0
2
V0
22 −1 =  V0 = 6V
2

05. Ans: (A)

Rf 22
Solution: Amplification factor due to V  ..............(i)
−
=
R1 10
And due to V
+

 R   Rf  +
V0 =   1 +  V
 R + 15   R1 
 R  Rf   R  22 
Amplification factor=    1 +  =   1 +  .............(ii)
 R + 15  R 1   R + 15  10 
Equating (i) & (ii)
 R  32  22
   =
 R + 15  10  10
32R = 22R + 22  15

22  15
R = = 33K
10

06. Ans: (A)

 −  +
Solution: V  0  = 5V = V  0 
C  C 
For t > 0 the equivalent circuit is

 20 
Vout = 5  1 +  = 10V
 20 
 +
 Time constant  = 20k  4 = 0.08s; V = V  0  = 5V; V = 10V
i   F

C F l (
V = V + V −V e
F ) −t  = 10 + (5 − 10) e−12.5tfor t  0

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 Analog Electronics (Vol-3)

07. Ans: (D)

dV0
Solution: We know the relationship between signal voltage and S.R is SR = = 2fV0
dt
Here, V0 → signal voltage and f → frequency

S.R 5  106 5
V0 =  V0 = = volts
2f 2  106 2

08. Ans: (C)

Solution: The given op–amp is a combination of both inverting and non inverting op –amp’s
R  R 
In inverting V = − F v , in non inverting V =  1 + F  v
0 R i 0  R  i
1  1
Here v = 1V
i
Apply super position theorem
 2
For v connected to positive terminal then V  = 0.5  1 +   V0 = 3  0.5 = 1.5V
i  0 1
2
For v connected to negative terminal then V  = −  1 = −2V
i 0 1
 V = V  + V  = 1.5 − 2 = −0.5V
0 0 0

09. Ans: 45.8

Solution:
 1 VCm 
V0 = Ad v d  1 + 
 CMRR Vd 
Here Vd = Vi1 − Vi2 = 150 − 140 = 10v
Vi1 + Vi2
150 + 140
Vc = = = 145v
2 2
 1 145  0.04  145
V0 = 4000  10v  1 +   = 0.04 + = 0.04 + 5.8  10−3 = 0.0458
 100 10  1000
V0 = 45.8mV

Type 13 – Op-Amp Applications

01. Ans: (A)
R  RCs 
Solution: Vx = Vi  Vx =   Vi ................(i)
1  RCs + 1 
R+
Cs
 Z 
Now, V0 = 1 + f  Vx
 Z1 
 1 
 C2s   RCs 
V0 = 1 +  V
 1   RsS + 1  i
 C1s 

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 Analog Electronics (Vol-3)

 c  RCs
A v = 1 + 1 
 c2  RCs + 1
It’s a high pass filter

02. Ans: (C)

Solution: Apply super position theorem

If Vi is connected only with negative terminal

1
RA 
Cs
1
RA + Vi
Vo = − Cs V = −
i
RA 1 + R A Cs

If Vi is connected only with positive terminal

 1 
 RA  
 Cs 
 1 
RA +
 Cs  Vi  2 + R A Cs  Vi
Vo =  1 + = 
 R A  2  1 + R A Cs  2
 
 
 
 
Vi  2 + R A Cs  Vi  R A Cs  Vi 
V = Vo + Vo = − +   =  
1 + R A Cs  1 + R A Cs   2  (1 + R A Cs )  2 


Hence it’s a High Pass filter

03. Ans: (C)

Solution: At node A
1 2 3
Vx 1 + 1 + 1 − − − =0
1 1 1
3Vx = 6  Vx = 2V..................(A)

Also VA = VB = Vx = 2V

Now at node B,

 1 1 1  ( −2 ) ( −3) V0
VB  + +  − − − =0
2 2 2 2 2 2

3VB + 2 + 3 = V0  V0 = 11V

04. Ans: (D)

Solution:
Figure (i) is standard Logarithmic amplifier and figure (ii) is peal detector

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 Analog Electronics (Vol-3)

05. Ans: (C)

Solution:
Case (1):
When input voltage is +ve, the switch ‘S’ is closed
Step (1):
−R
V0  = V
R i
V0  = −Vi ...............(1)
Then the circuit w.r.t op-amp 2 can be shown as
Step (2):
KCL at node V2
Vo' Vi V0
+ + =0
R R R
2
 
 Vi V0  
V0 = −R  +  = −  Vi − 2Vi 
R R 
 2 
 V0 = Vi

Case (ii):
When the input voltage is −ve, the switch S is open. Under these conditions the circuit given can be simplified as below.

It is a non inverting Op-Amp

R
V0 = − V = − Vi
R i
Note:
∵ Vi is already −ve, hence V0 = +ve

 The given circuit is a Full wave rectifier.

06. Ans: 3
Solution:
The above circuit is a summer, where V0 can be is given as
RF
V0 = − ( V + VS2 + VS3 + ..... + VSn )
R S1
2  103
V0 = −
5  103
(
5 + 10 + 15 + 20 + .... + 5n V )
n (n + 1 )
V0 = − ( 0.4 ) 5 (1 + 2 + 3 + ... + 5n ) V = −2 V
2

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 Analog Electronics (Vol-3)

−12V = −n (n + 1 ) V
n (n + 1 ) = 12
n2 + n − 12 = 0
−1  1 + 4 (12 ) −1  49 −1  7
n= = = = −4,3
2 2 2
Valid of n = 3

Type 14 – Sinusoidal Oscillator Circuits & 555 timers

01. Ans: (A)
Solution:

Case 1:- Consider V0 = +Vsat = 12V . In this case D2 will be conducting and circuit will look like

In this case voltage at +ve terminal of op-amp can be calculated as

 1 1 1  10 ( −10 ) 12
VA  + +  − − − =0
2 4 3 4 2 3
VA 6 + 3 + 4  − 30 + 60 − 48 = 0
18
VA = = 1.385V.................(i)
13

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 Analog Electronics (Vol-3)

Thus if Vi will increase above VA O/P switch to −Vsat

Now,
Case 2:- consider V0 = −Vsat = −12V . In this case circuit will look like. [D1 will be conducting]

 1 1 1  10 ( −10 ) ( −12 )
VA  + +  − − − =0
2 4 4  4 2 4

10 10 12
VA − + + =0
4 2 4
12 + 20 − 10
VA + = 0  VA = −5.5V............(ii)
4
Thus if Vi will become less than VA O/P will switch to +Vsat

02. Ans: (D)

Solution: Given V+ = V0 , thus lower threshold will be V− = −V0

( )
i.e. Hysteresis voltage=  V0 − − V0 = 2 V0
Also given that
Hysteresis voltage=1
2V0 = 1 V0 = 0.5
Since it is known that Triggering taken place only at lower & upper threshold i.e. +V0 & −V0
0.5 & -0.5

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 Analog Electronics (Vol-3)

03. Ans: (C)

Solution: Circuit will look like

Let V0 = 8V
1
Then V+ =  V0 =  8 = 1V , Now if Vs will be less that V+ = 1V O/P will remain at V0 = +8V
8
Thus option (i) is correct i.e. For Vs -ve & rising V+ = +1V
Now, if V0 = −8V then V+ = V0 = −1V . In this case O/P will remain at -8V, until V+ become greater than -1 i.e.

(2) For Vs positive & decreasing i.e. we are at lower part of graph. Thus V0 = −8  V+ = −1V
(3) Same logic as of (2)
(4) For Vs increasing through zero i.e. means we are at upper part of graph i.e. V0 = +8  V+ = 1
So only 1 & 4 are correct

04. Ans: (A)

Solution: Case 1:- Let V0 = +5V
Then
V0  ( 0.1 ) + VR  10
V1+ =
10 + 0.1
5  0.1 + 1  10 10.5
V1+ = = .......................(i)
10.1 10.1
Now V0 = −5V then

V0  ( 0.1 ) + VR  10
V1+ =
10 + 0.1
−5  0.1 + 10 9.5
V1+ = = ..................(ii)
10.1 10.1
10.5 − 9.5
Hysteresis VH = V1+ − V1+ = 0.1V
10.1

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 Analog Electronics (Vol-3)

05. Ans: (A)

Solution: This is an example of Colpitt’s Oscillator
1 1
f= =
 CC   10 
2 L  1 2  2 L  C2 
 C1 + C2   11 
1
40  103 =
 10 
2 0.1  C2 
 11 
C2 = 177F

06. Ans: (A)

Solution:
It is Wein bridge
1
f=
2 RR 'CC'
1
1kHz =
2 106  C2
1
C=
2  103  103
1
C= F
2

07. Ans: (B,C)

Solution:
1
fS = = 1.09MHz
2 LC
 C
fP = fS  1 + 
 C 
fP
= 1.033MHz
fS
fP exceeds by fS by 3.3%
SL L L
(b) Q = = = 410
R R C

08. Ans: (A)

Solution:
Oscillator is Hartley oscillator
And oscillation frequency

1 1
f=
2 ( L1 + L 2 ) C
f = 25.18MHz

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 Analog Electronics (Vol-3)

09. Ans: (B)

Solution:

For phase shift oscillator,

1
f=
2RC 6

1
RC =
2 6  5  103
C = 12.9 sec

10. Ans: (C)

Solution:

The capacitor ‘C’ charges toward Vcc though external resistors RA and RB

 Tcharging = 0.7(R1+R2) C
The capacitor ‘C’ discharges through resistor RB.

 Tdischarging = 0.7 R1C

Total time period T= Tcharging + Tdischarging

 The frequency of the astable circuits is then calculate using

1 1.44
f= =
T (2R1 + R 2 )C

11. Ans: (B)

Solution:
Monostable multivibrator is used to generate pulses.

Monostable multivibrator has one single stable state and one quasi stable state

In a bistable multivibrator, commutating capacitors are used to increase the speed of response

12. Ans: (D)

Solution:
During positive supply voltage, Diode (D) is in reverse bias condition. Resistance R b is not short circuited in this case. This

will increase the time constant.

Hence diode decreases the discharging time of capacitor (C).

13. Ans: (A)

Solution: Given is inverting Schmitt trigger
Upper cross over voltage when, v o = +10v ,
At upper threshold point , output changes from +10V to -10V

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 Analog Electronics (Vol-3)

 V−  V+
 10   20   5 
 2 +   VUTP =   10
 10 + 20   10 + 20   5 + 20 
VTh = 2V
Lower cross over voltage when v 0 = −10v
At lower threshold point, output changes from -10V to +10V
 V−  V+
 10   20   5 
  (2) +   VLTP =   ( −10 )
 10 + 20   10 + 20   5 + 20 
VLTP = −4V

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Singnal and System