Lecture Plan

Session (2024-25)
Course Course
Name of Course L T P Credit
Type Code
DC ECC209 Microprocessors & Microcontrollers 3 0 0 9

Sl. Topics to be Covered Lecture

No. Hours
1 1. Prerequisites for ‘Microprocessors’ 3
1.1. Importance of microprocessor (including a brief history)
1.2. Tri-State buffer
1.3. Registers
1.4. Logical configuration of ROM / ROM
1.5. Different types of RAMs and ROMs
1.6. RAM / ROM interfacing with a generic microprocessor
1.7. Configuring different sizes of RAM using smaller RAM chips

2 Intel 8085 CPU Architecture and Pin Outs, Timing Diagram, Stacks and Subroutines, 18
Addressing Modes, Instruction sets, Programming, Interrupt Structure and Serial I/O, Memory
and I/O Interface.

Details:
2. 8085 microprocessor
2.1. Internal architecture
2.2. A detail description of following
2.2.1. ALU
2.2.2. Accumulator
2.2.3. Timing and control unit
2.2.4. Oscillator Section and XTAL oscillator
2.2.5. Instruction register and instruction decoder
2.2.6. General purpose registers
2.2.7. Program counter
2.2.8. Stack pointer
2.3. Complete internal block diagram
2.4. The multiplexed address/data lines and their demultiplexing
2.4.1. Need of external LATCH and ALE
2.5. The events involved in a data/ instruction flow from RAM to the microprocessor
2.6. Pin configuration
2.6.1. Address and data lines, 𝑅̅̅𝐷̅ ,𝑊̅𝑅 ̅ ̅, ALE,
2.6.2. X1,X2: What is crystal? Why is the crystal frequency required to be twice of the
operating frequency?
2.6.3. HOLD and HLDA
2.6.3.1. Describing the need of DMA
2.6.4. Ready
2.6.4.1. Stating its role in interfacing slower peripheral
2.6.5. IO/𝑀̅
2.6.5.1. Describing the existence of I/O (or peripheral) registers and showing the
hardware involving IO/M to interface memory (chip select logic).
2.6.6. 𝑅̅̅𝑒̅𝑠̅𝑒̅𝑡̅ 𝚤̅𝑛̅ and Reset out (specifying their need).
2.6.7. Clk Out
2.6.8. TRAP, RST7.5, RST6.5, RST5.5, INTR, 𝐼̅𝑁̅𝑇̅𝐴̅
2.6.9. SOD, SID
2.6.10. S0, S1
2.6.11. Vcc, GND
2.7. Revision
2.8. Program model
2.9. Flags
 2.10. Addressing Modes
2.11. Instruction and example program
2.11.1. Data transfer group
2.11.2. Arithmetic group
2.11.3. Logical group
2.11.4. Branching group
2.11.5. NOP
2.11.6. EI/DI
2.11.7. Software interrupt
2.11.8. IN/OUT
2.11.9. RIM,SIM
2.12. Concept of Monitor Program
2.13. Exercise programs
2.13.1. Basic programs like –
2.13.1.1. Addition of two numbers
2.13.1.2. Ways of implementing loops in 8085 ALP
2.13.2. Shifting a block memory
2.13.3. Addition of a block of memory
2.13.4. Multiplication of numbers
2.13.5. Mirror image of a number
2.13.6. Factorial
2.13.7. Recursion
2.14. Timing diagram (with different examples)
2.14.1. Opcode fetch
2.14.2. Why some instructions like CALL, DCX consumes 6T states instead of 4T
2.14.3. Memory read
2.14.4. Memory write
2.14.5. I/O Read
2.14.6. I/O Write
2.14.7. Interrupt
2.14.8. HLT
2.15. How to calculate machine cycles of different instructions
2.16. Delay programs
2.16.1. Calculation of execution time of a program
2.16.2. Delay generation program
2.17. Interrupt
2.17.1. Software , Hardware
2.17.2. Maskable and non-maskable
2.17.3. Interrupt priorities
2.17.4. Internal diagram of interrupt facility
2.17.5. Detailing of EI, DI, SIM, RIM
2.17.6. Detailing of INTR & 𝐼̅𝑁̅𝑇̅𝐴̅
2.17.7. How to use a Software Interrupt as a Hardware Interrupts
2.17.8. Interrupt Driven Program
2.18. Serial communication using SOD & SID with program

3 Interfacing Different Peripherals: 7

Programmable Peripheral Interface (8255), Programmable Display and Keyboard Interface
(8279), Programmable Interval Timer (8254), Programmable Interrupt Controller (8259),
Introduction to Programmable DMA Controller (8237) and Programmable Communication
Interface (8251). Interfacing of A/D and D/A converters and Measurement of Physical
Quantities

Details:
3. Interfacing Different Peripherals
3.1. I/O (Peripheral) Mapped I/O, Memory Mapped I/O
3.2. Interfacing Switches (Inputs) and LEDs (Outputs) using decoders and tri-state Latches
3.3. 8255 and its interfacing
3.3.1. Functional description
3.3.2. Pin diagram
 3.3.3. Hardware Interfacing with 8085
3.3.4. Control word format
3.3.4.1. I/O and BSR
3.3.5. I/O Modes and their Description
3.3.6. 7-Segments LED interfacing with Program
3.3.7. ADC interfacing with 8255 with Program
3.3.8. DAC interfacing with 8255 with Program
3.4. 8279 and its interfacing
3.5.1. Functional description
3.5.2. Internal Block Diagram
3.5.3. Pin configuration
3.5.4. Hardware interfacing with 8085
3.5.5. Hardware interfacing with 7-segment LED and Keyboard
3.5.6. Modes of keyboard and display
3.5.7. Internal register configuration
3.5. 8259 interrupt controller
3.5.1. Functional description
3.5.2. Internal Block Diagram
3.5.3. Pin configuration
3.5.4. Hardware interfacing with 8085
3.5.5. Hardware connection to extend up to 64 interrupts by another 8 8259s
3.6. 8254 Timer/counter
3.6.1. Functional description
3.6.2. Internal Block Diagram
3.6.3. Pin configuration
3.6.4. Hardware interfacing with 8085
3.6.5. Internal register configuration
3.6.6. Control ward format
3.6.6.1. Including Counter Latch and Readback
3.6.7. Short description to six different modes
3.7. 8257 DMA
3.7.1. Functional description
3.7.2. Internal Block Diagram
3.7.3. Pin configuration
3.7.4. Why is the upper byte address lines are multiplexed with data unlike to 8085?
3.7.4.1. Hardware description
3.7.5. Hardware interfacing with 8085
3.8. Brief description of 8251

4 Intel 8086 CPU Architecture and Pin Outs, Minimum and Maximum Mode, Memory 5
Segmentation, Addressing Modes, Memory Interface, 8086 Interrupt Structure

Details:
4. 8086 Microprocessor
4.1. 8086 Internal Architecture
4.1.1. Different Internal registers
4.1.1.1. General purpose registers
4.1.1.2. Pointer and Index registers
4.1.1.3. Segment Registers
4.1.2. Execution Unit
4.1.2.1. ALU
4.1.2.2. Flag (description of the flags that are not available in 8085)
4.1.3. Bus Interface Unit
4.1.3.1. Instruction Pointer (why it is of 16 bit whereas the address lines are of 20
bits), Default value of IP
4.1.3.2. Segmented addressing
4.1.3.3. Generation physical address from effective address and segment base
address
4.1.3.4. Advantage of memory segmentation
4.1.3.5. Instruction queue
 4.2. 8086 Pinouts
4.2.1. Memory Interfacing with 8086
4.2.1.1. Circuit representation in MIN mode
4.2.1.2. Importance of 𝐵̅̅𝐻̅𝐸̅ and A0 in memory interfacing
4.2.1.3. Why is the memory separated into even and odd blocks?
4.2.1.4. How an instruction can start from an even or odd address and the
dependence of the execution cycle on this.
4.2.1.5. Circuit representation in MAX mode
4.3. 8086 Addressing Modes with examples
4.3.1. Resister addressing mode
4.3.2. Immediate addressing mode
4.3.3. Direct addressing mode
4.3.4. Register Indirect addressing mode

5. Microcontrollers 8051 systems; Memory Organization Input/Output Ports, and its assembly 8
language programming Concepts of 8051 μC.
Interfacing of 8051 with some basic peripherals.

Details:
5. 8051 Microcontroller
5.1. Difference between Microprocessor and Microcontrollers
5.2. Types of Microcontrollers
5.3. MCS51 family members
5.4. Features and internal peripherals of 8051
5.4.1. Bit processor as well as Byte processor
5.5. Pin configuration
5.5.1. Minimum high time for Reset, and the circuit for power-on-reset
5.5.1.1. Calculation of circuit parameters
5.5.2. 𝐸̅̅𝐴̅ and 𝑃̅̅𝑆̅𝐸̅𝑁̅
5.5.2.1. What if the 𝐸̅̅𝐴̅=1 but memory address is higher than 0FFFh
5.5.2.2. ̅ ̅
External Memory interfacing circuit using 𝑃̅̅𝑆̅𝐸̅𝑁̅, 𝑅̅̅𝐷̅, and 𝑊̅𝑅
5.5.3. XTAL1 and XTAL2, How to use them individually
5.5.3.1. Need of shunt capacitors with crystal oscillator, and what would happen if
they are removed
5.5.4. Internal configuration of PORT-1,3,2 and 0
5.5.4.1. Need for external pull-up registers with PORT-0, and their values
5.5.4.2. Why port-0 is called a true-bidirectional and others are called quasi-
bidirectional port (practical examples in respect to these)
5.6. SFRs and GPRs
5.6.1. Bit addressable registers
5.6.2. Default values of some SP
5.6.3. Direct/Indirect addressable RAM locations
5.6.4. Existence of indirectly addressable scratchpad RAM in parallel to SFR locations
5.7. Internal RAM organization
5.7.1. Register banks
5.7.2. PSW (Especially focusing on RS0,RS1, and overflow flag)
5.7.3. Bit addressable locations and the bit addresses
5.7.4. Stack and its range
5.8. 8051 assembly language
5.8.1. Data transfer group instructions
5.8.1.1. Special uses of MOVC
5.8.2. Arithmetic group instructions
5.8.2.1. MUL AB and DIV AB
5.8.2.2. DAA
5.8.3. Logic group instructions
5.8.3.1. SWAP A
5.8.3.2. Rotate instructions
5.8.4. Bit manipulation instructions
5.8.4.1. A common mistake: MOVC is different from MOV C
 5.8.5. Branching instructions
5.8.5.1. Relative address
5.8.5.2. Bit-related branching instructions
5.8.5.3. Unconditional branching
5.8.5.4. Difference between RET and RETI
5.8.5.5. Applications of DJNZ with programming
5.8.5.6. How JNZ in 8051 is different from that of 8085
5.9. Basic port interfacing circuits and programs
5.9.1. Blinking of LED
5.9.2. Binary Counter
5.9.2.1. Looping in 8051
5.9.3. Up/Down counter using a port pin as input

6. 6.1. Comparison of CISC and RISC processors. 1

6.2. Introduction to ARM microcontrollers

Textbook:
1. R.S. Gaonkar, “Microprocessor Architecture, Programming, and Applications with the 8085,” Penram
International Publishing, 2017.
2. A. K. Gautam, A. R. Jaiswal, “The 8086 & 8088 Microprocessors,” S. K. Kataria & Sons, 2003
3. Deshmukh, Ajay V. Microcontrollers: theory and applications. Tata McGraw-Hill Education,2005.

Reference Books:

1. The 8051 Microcontroller Based Embedded Systems, Manish K Patel, McGraw Hill Education (India), 2018.

Name of the Instructor:

Dr. Mrinal Sen

Associate Professor, Department of Electronics Engineering
Indian Institute of Technology (ISM) Dhanbad