High Throughput Architecture for KLEIN Block

Cipher in FPGA

Pulkit Singh B. Acharya R. K. Chaurasiya

Electronics & Telecommunication Electronics & Telecommunication Electronics & Telecommunication
National Institute of Technology, Raipur National Institute of Technology, Raipur National Institute of Technology, Raipur
Raipur, India Raipur, India Raipur, India
[email protected] [email protected] [email protected]

Abstract—In recent times, lightweight cryptographic algo- some merits and some demerits and are realized to be used on
rithms have drawn a lot of attention to the researchers for different low-end devices. Parallel design divides the complete
securing the fast and small-computing devices. However, different block message into equal parts and operates the process at the
algorithms have been developed to fulfill the requirements, same clock cycle [7] for single round and key scheduling,
and there has not been much research on transforming these simultaneously. This idea increases throughput as compared
algorithms to Field Programmable Gate Arrays (FPGAs) with
to other design styles with the expense of area.
minimal optimization. These reprogrammable devices are highly
attractive options for hardware implementations of encryption al- It is very easy to select intended design strategies which are
gorithms. A strong focus is placed on high-throughput implemen- suitable for resource-constrained environments. The designers
tations, which are required to support security for current and fix the applications, where particular designs can be used for
future high bandwidth applications. In this paper, two different
architectures are designed for resource-constrained environments.
implementation. These implementations can be done on Field
Among them, parallel processing implementation achieves high Programmable Gate Array (FPGA) and Application Specific
throughput of 2070.39 and 1646.12 Mbps on xc5vlx50t-3ff1136 Integrated Circuit (ASIC) [8]. FPGAs can be reprogrammed
and xc4vlx25-12ff668 devices, respectively. While in the other for the desired applications or functionality requirements after
design, 8-bits datapath architecture signifies the use for low I/O manufacturing, whereas designs in ASIC cannot be changed
port devices. All results are simulated and verified for different once it is taped-out. The circuit will work the same for its
devices of Xilinx Spartan & Virtex families. complete operating life. ASIC designs consume less power
Keywords—Lightweight cryptography, Security, KLEIN cipher, than FPGA designs because FPGAs have redundancy in the
Hardware implementation, FPGAs, Resource-constrained environ- hardware and FPGA is not suitable for designs requiring power
ments. optimization. When it comes to ASIC designs, we can optimize
them to the fullest.
I. I NTRODUCTION
A. Related Work
The lightweight stands for the devices that have low
resources in terms of area, power, and throughput. There For all lightweight block ciphers, different architecture
are many algorithms used to provide adequate security. Con- models have been developed using different datapaths. Au-
ventional algorithms such as Advanced Encryption Standard thors in [9] used various optimization strategies for AES 32-
(AES) [1] and Data encryption Standard (DES) [2] are not bits achieving an ultralow-energy, ultralow-power, low-cost,
used for providing security to high-valued devices. Conse- and high-throughput design with several levels of security.
quently, researchers are not much concerned with techniques Lara-Nino et. al [10] used improved data registers and key
that consume more power and have large area. However, mechanism for 80-bits and 128-bits keys for a datapath of
there are many applications where lightweight ciphers have 16-bits. This 16-bits datapath architecture with 80-bits key
its advantages like internet of things (IoTs), wireless sensor schedule was developed for applications where an area and
networks (WSNs), and radio frequency identification (RFID) security trade-off can be established. In [11], authors presented
[3], [4]. These applications require less memory storage, small a novel hardware design for the PRESENT [12] cipher aiming
area overhead, and low power expenditure. So, lightweight to obtain a low-cost design in terms of area. This architecture
algorithmic implementations in hardware are solutions to many has the advantage of reduced datapath width that are well
applications. suited for multiple platforms with reduced number of ports.
In [13], very compact hardware designs of LED [14] and
There are a large number of designs available to deal PHOTON [15] was developed on FPGAs with serialized and
with low-cost hardware implementations. Many of them are round-based implementations.
fulfilling the problem criteria by considering the different Moreover, Paper [16] considers the performance of encryption
ways in which they are designed to get intended results. algorithm and it uses AES, DES and RivestShamirAdleman
All can be designed according to their applications such that (RSA) [17] algorithm. It is found that, first the encryption
their implementations can have fewer expenses. some of these time is computed. The time is taken to convert plain text to
design styles are serial, round-based, unrolled, and parallel- cipher text is known as encryption time. Comparing these three
based architectures [5], [6]. These types of architectures have algorithms, RSA takes more time for computation process. The
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 memory usage of each algorithm is considered as memory byte B. Key Scheduling
level. RSA takes larger memory than AES and DES. Finally,
KLEIN utilizes the Feistel-based structure in key schedul-
the output byte is calculated by the size of output byte of each
ing to withstand against weak key attacks [19]. It employs
algorithm. The level of output byte is equal for AES and DES,
an incremental round counter that adds constant to each round
but RSA algorithm produces low level of output byte.
resisting the slide attack [19]. Subkeys are produced on-the-fly
mode simultaneously with round transformation that preserves
B. Contributions memory requirement for intermediate states. For all 64/80/96
In this paper, we have developed architectures based on bits of the key, the 64-bits from the LSB side are used in
different datapath inputs. These are designed according to their the algorithm. The key scheduling of KLEIN for 64-bits is
various design strategies by taking different datapath inputs. modeled as follows in Equation (1).
The following are the contributions of this paper:
• Developed a hardware design with reduced datapath K = k63 k62 k61 ......k2 k1 k0
input and output without reducing intermediate pro- K1 = k63 k62 k61 ......k34 k33 k32
cessing datapath size. The proposed design is effective K2 = k31 k30 k29 ......k2 k1 k0
for low bit I/O ports microcontrollers.  
K1 = K1 << 8 & K2 = K2 << 8
• Also, minimized datapath input for 16-bits plaintext     

makes four processing lines architecture that shows K1 = K2 & K 2 = K1 ⊕ K 2

Kf [44 : 40] = K1  [44 : 40] ⊕ RC i (1)
highest throughput to previous published some other
cipher’s architectures. 
Kf [11 : 08] = S(K2 [11 : 08])

The rest of paper is categorized as follows. Section II shortly Kf [15 : 12] = S(K2 [15 : 12])
describes the datapath and key scheduling for KLEIN cipher 

with its hardware architecture. Proposed design strategies are Kf [19 : 16] = S(K2 [19 : 16])

described in section III that elaborates the design of hardware Kf [23 : 20] = S(K2 [23 : 20])
implementations. Section IV describes the methodologies for
where, K is the master key, K1 &K2 are MSB 32-bits & LSB
the experimental works. Simulation results are discussed and
compared in section V. Section VI concludes the paper and 32-bits of the master key, K1 & K1 are intermediate key states,
Section VII guides the future work. Kf is the final key for the corresponding round, RC i denotes
round constant value incremented by one for each round, and
S represents S-box input bits.
II. A LGORITHM OVERVIEW Fig. 1 describes a basic hardware description of KLEIN
cipher with two specifications: Datapath and Key scheduling.
A. Data Path For each round, the key is generated that shows little changes
KLEIN [18] is a lightweight block cipher developed in algorithms for all three variants. Data path utilizes sixteen S-
mainly on legacy sensor platforms. Like AES, KLEIN per- boxes, while key scheduling uses four S-boxes for processing
forms similar round function: SubN ibbles, RotateN ibbles, the input bits and key bits, respectively. Key scheduling looks
M ixN ibbles. This Substitution-Permutation based network like a Feistel structure that adds additional security to cipher.
has 64-bits of plaintext, 64/80/96 bits of variable keys that Moreover, for 80 and 96-bits key, Most Significant Bit (MSB)
encrypt plaintext to produce ciphertext in 12/16/20 number of 64-bits are taken as the round key.
rounds, respectively. SubN ibbles is the only non-linear step
in KLEIN cipher that provides adequate security to resource-
constrained devices. Before performing round function in each
round, plaintext of 64-bits is XORed with 64-bits of the key
for the 64-bits of key size, whereas Least Significant Bit (LSB)
64-bits are extracted from the round keys for 80 and 96-bits of
key scheduling. The XORed result is then split into 16 equal
parts of 4-bits nibbles that passed through the S-boxes. Table I
shows the 4-bits S-box used in KLEIN cipher. Since, it is a 4x4
involuting S-box, which means that it saves the implementation
costs for the decryption process.
This algorithm is processed based on byte-oriented basis.
During the RotateN ibbles operation, every two bytes is
shifted left in each round. In M ixN ibbles step, mixing of
columns is performed as in AES algorithm [1] with the same
matrix multiplication.

TABLE I. S- BOX FOR KLEIN C IPHER

in 0 1 2 3 4 5 6 7 8 9 A B C D E F
out 7 4 A 9 1 F B 0 C 3 2 6 8 E D 5 Fig. 1. Basic Hardware Description of KLEIN [18]

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 III. P ROPOSED A RCHITECTURES key, producing round key. This scheme uses four clock cycles
to load the input data into four 16-bits registers. By doing this,
Two different structures have been developed that take
area overhead is reduced than previous proposed architectures.
different datapaths input showing their characteristics. These
architectures employ 8-bits and 16-bits data inputs, respec-
tively. Since S-box transforms the 4-bits input at a time, Parallel processing architecture requires four more cycles
any width divisible by four can be designed into a hardware to get the output for 64-bits key scheduling. As a result,
implementation. The design in Fig. 2 executes the plaintext total latency of 20 cycles are involved for 64-bits ciphertext.
with variable datapath that demands additional logic control to Additional one and two clock cycles are needed for producing
process the data. Moreover, data transformation from a small output for 80-bits and 96-bits key scheduling, respectively. By
width to a larger one or vice versa needs extra storage elements processing data into parallel fashion, it generates more number
and multiplexers which cost the area overhead and increase the of output bits with less clock cycle. By using four full storage
latency. To overcome that issue, a unified 16-bits datapath input 16-bits data and key registers and also, small intermediate
is utilized. However, having a smaller datapath increases the storage elements, it has minimal resource requirement than
clock cycles for getting the output. Thus, based on following iterative implementation.
strategies, two hardware implementations for KLEIN cipher
are examined in the following sub-section.

A. Proposed Iterative Architecture Implementation

Proposed design in Fig. 2 uses 8-bits input and produces
8-bits output with a key size of all variants. This scheme takes
eight clock cycles to load the data and 64-bits key into two
64-bits registers. These registers assist to load inputs serially,
shift 8-bits at each clock. These loaded values process all bits
in parallel fashion from both data register and key register.This
iterative design decreases the required resources for utilizing
the operation. Full datapath width design can be better one
in terms of throughput but it is not considered in this paper.
whereas 8-bits iterative design slows the operation. In addition,
it will offer respectable throughput. All the functions in each
round are same as shown in Fig.1.
When a block-cipher module is used in an embedded
device or an RFID tag for encrypting/decrypting data, it is not
practical to have an interface with a data width equal to that
of the state/key size. This is an aspect that is often ignored in Fig. 2. Iterative Architecture Design
related work, since depending on the realization of the interface
significant overhead costs in terms of area requirements arise.
Not only area requirement but also execution time and energy
consumption are strongly influenced by the interface. This
structure overcomes these issue by direct reducing the datapath
width by some amount.
To produce the 64-bits ciphertext, total latency of 28 cycles
are consumed for 64-bits key scheduling. In addition, 80-
bits and 96-bits key scheduling produce output data with the
latency of 30 and 32 clock cycles, respectively. For controlling
the variable data processing, this structure demands extra
controller logic circuitry. Due to this, iterative architecture for
8-bits shows more resource usage than other architectures. But,
it signifies the maximum operating frequency as compared
to corresponding devices. The iterative design is valuable for
those devices that have less I/O ports such as 8-bits micro-
controller. Thus, this architecture can work on high frequency
with some delay in the circuits.

B. Proposed Parallel Processing Architecture Implementation

This proposed design works on four processing data lines
in datapath as well as in key scheduling. Fig. 3 is designed
to take 16-bits data as input and produces equal 16-bits data
output. Alike datapath, Key scheduling is also applied in a
parallel manner by taking four extra clock cycles for 64-bits Fig. 3. Four Processing Lines-type Design

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 IV. M ETHODS Logic Blocks (CLBs) are considered similar for all devices,
which may guide to similar implementation results with respect
A. Environment
to resource utilization.
The proposed KLEIN architectures are synthesized in
Xilinx using Integrated Synthesis Environment (ISE) design D. Hardware Metrics
suite 14.6 and simulated using ISim simulator. For comparison,
Spartan-3, Virtex-4, Spartan-6 & Virtex-5 are employed with The architectures implemented in FPGAs are evaluated
devices xc3s200-5ft256, xc4vlx25-12ff668, xc6slx16-3csg324 on different hardware metrics such as area, performance, and
& xc5vlx50t-3ff1136, respectively. Each family has different power consumption. The area is expressed in terms of LUTs,
number of Slices, Look Up Tables (LUTs), and flip-flops. The Slices, and Flip-flops occupied by the structures. Performance
evaluations are done after performing placement and routing. behavior is evaluated concerning the throughput and latency.
Power is estimated by Xilinx X Power Analyzer for all design Latency is equal to the number of executed clock cycles for
technologies. getting the first output. Data and key for loading into registers
decide the number of flip-flops. One Slice can contain more
B. Synthesis Specification that one LUTs and flip-flops depending on the technologies.

For evaluation, a group of low area and low power ad- At last, power consumption depends directly on area size.
vanced boards were examined. The RAM/ROM resources As larger area consumes more power and vice versa. It also
embedded in FPGAs are not used for a fair comparison. This depends on the switching activity of the realization, so all
is done by preventing the suited standard in the Hardware results are compared for a constant operating frequency. To
Description Language (HDL) choices during realization pro- evaluate performance in terms of throughput, which is a
cedures. However, key scheduling section of architecture in function of maximum operating frequency. Equation (2) is used
Fig. 3 could be configured in the RAM/ROM resources for for calculating throughput and it is measured in Mega bit per
optimizing the area overhead further, but in this paper, key second (Mbps) [25].
scheduling is performed simultaneously with the data process- Block size × Operating F requency
ing part adding more resource usage to proposed design. T hroughput = (2)
Latency
C. Configurations In addition, Latency is measured as the time interval between
the moments of introducing the input data into a cipher
Two architectures of KLEIN are based on hardware metrics and getting the corresponding output data. It is expressed
realized in synthesis tools. These designs are configured for as number of clock cycles. For all design implementations,
result comparison as: block size is examined for 64-bits size.
• Design 1: By using smaller datapath input and output
as 8-bits, as shown in Fig. 2, the design is targeted for V. D ISCUSSION AND R ESULTS
lower I/O devices by considering iterative architecture. Table II shows the FPGAs implementation results of some
This design can be operated at high frequency. conventional and lightweight block ciphers. Results are evalu-
• Design 2: A parallel processing architecture operates ated in terms of resource usage, speed performance, and power
the 16-bits data input as presented in [11], revealed the consumption. There are different devices used to simulate the
high throughput design as compared to other proposed results. Under resource usages, area consuming elements like
implementations. Flip-flops, LUTs, and Slices are discussed. Moreover, latency,
operating frequency, and throughput are evaluated to compare
These designs are verified and compared under similar usage the speed of devices for different architectures in the literature.
conditions like synthesis tools, implementation process, pro- To measure the power consumption, total power is calculated
gramming style, and FPGAs devices. In addition, Configurable for various FPGAs families.

TABLE II. FPGA S IMPLEMENTATION RESULTS OF OTHER BLOCK CIPHERS

Block Area (Resources) Speed Total Power
Ciphers Flip-flops LUTs Slices Latency (Clock Cycles) Max. Freq. (MHz) Throughput (Mbps) (mW) Devices
PRESENT80 [12] 153 170 48 133 257.40 123.86 21.61 XC6SLX16-3CSG324
PRESENT128 [12] 201 220 61 136 210.66 99.13 21.76 XC6SLX16-3CSG324
PRESENT80 [12] 153 215 124 133 213.81 102.89 42.08 XC3S200-5FT256
PRESENT128 [12] 201 264 151 136 194.63 91.59 42.36 XC3S200-5FT256
LED80Round-based [13] 74 379 198 32 87.63 175.3 - XC3S50-5
LED128Round-based [13] 76 444 227 48 87.63 116.54 - XC3S50-5
LED80Serial [13] 157 332 169 608 157.43 16.6 - XC3S50-5
LED128Serial [13] 219 388 203 912 142.01 9.97 - XC3S50-5
PRESENT128 [20] 114 159 117 256 114.80 28.46 - XC3S50-5
HIGHT [20] 25 132 91 160 163.70 65.48 - XC3S50-5
AES128 [21] 338 531 393 534 - 16.86 23.83 XC3S50-5
AES128 [22] - - 184 160 45.64 36.50 - XC3S50-5
xTEA [23] - - 254 112 62.60 35.78 - XC3S50-5
SIMON [24] - 72 36 - 136 3.60 - XC3S500
PRESENT80 [12] 153 190 67 133 542.30 260.96 562.75 XC5VLX50T-3FF1136
PRESENT128 [12] 201 239 73 136 431.78 203.19 562.67 XC5VLX50T-3FF1136
PRESENT80 [12] 153 215 124 133 375.66 180.77 245.78 XC4VLX25-12FF668
PRESENT128 [12] 201 265 152 136 364.56 171.56 248.02 XC4VLX25-12FF668

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 TABLE III. FPGA S IMPLEMENTATION RESULTS OF KLEIN CIPHER
KLEIN Area (Resources) Speed Total
Cipher Flip-flops LUTs Slices Latency (Clock Cycles) Max. Freq. (MHz) Throughput (Mbps) Power (mW) Devices
Design 1 140 360 121 28 261.81 598.43 20 XC6SLX16-3CSG324
Design 2 132 379 97 12 214.98 1146.54 20 XC6SLX16-3CSG324
Design 1 141 461 263 28 159.39 364.32 40 XC3S200-5FT256
Design 2 133 410 240 12 138.81 740.32 40 XC3S200-5FT256
Design 1 141 327 110 28 407.84 932.19 562 XC5VLX50T-3FF1136
Design 2 133 378 145 12 388.20 2070.39 563 XC5VLX50T-3FF1136
Design 1 141 459 255 28 331.13 756.87 243 XC4VLX25-12FF668
Design 2 133 463 260 12 308.65 1646.12 243 XC4VLX25-12FF668

Table III exhibits and compares the results for KLEIN have been studied that can be involved in the applications,
cipher for proposed architectures. Round-based structure of where area-performance trade-off can be adjusted. Our better
LED80 [13] consumes less number of flip-flops as compared implementation circuit processes one KLEIN encryption with
to all ciphers in Table II as well as less latencies for xc3s50-5 12 clock cycles and offers respectable throughput. The pro-
device. But, this design shows low operating frequency and posed iterative design is significant for lower bits I/O ports in
low throughput as compared to both proposed architectures. embedded systems. It means that 8-bits designs help to secure
Designs presented in [10], have high latencies for producing the low I/O ports devices. Whereas, the parallel processing
the ciphertext and processing less number of bits at a given architecture has the capability to encrypt the datapath bits
time. Whereas, our proposed designs produce large number quickly and achieves smallest area that is applicable for
of bits at a same time and have low latencies. All ciphers resource-constrained applications. Consequently, an interesting
including proposed designs of KLEIN show almost equal application of our implementations arises in high throughput
power dissipation for corresponding devices. cryptography. In last, Reprogrammable devices such as FPGAs
are highly attractive options for hardware implementations of
Out of two designs, parallel processing architecture demon-
encryption algorithms, as they provide cryptographic algorithm
strates high throughput for all devices due to low latency.
agility, physical security, and potentially much higher perfor-
This design utilizes less Flip-flops and Slices than iterative
mance than software solutions.
architecture due to small loading registers and absence of extra
controlling circuits. Moreover, power comparison explores that
VII. F UTURE W ORK
power dissipation stands constantly across all architectures for
the same FPGAs apparatus. By using a 16-bits I/O ports, it Performance of proposed designs can be further enhanced
is feasible to have a latency of 20 cycles that is lower than by making appropriate design strategies with different op-
all designs shown in Table II. Among all proposed designs, timization techniques. There is still room for improvement
design 2 is showing highest throughput of 2070.39, 1647.12, by inserting registers of pipelining in optimal placements.
and 1146.54 Mbps in xc5vlx50t-3ff1136, xc4vlx25-12ff668, Investigating the robustness of lightweight implementations
and xc6slx16-3csg324 devices, respectively. Fig. 4 compares against side channel analysis and implementing lightweight
the throughput results for PRESENT and KLEIN ciphers and asymmetric cryptosystems is future work.
shows that Virtex-4 has highest throughput design options in
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