Click on Subject/Paper under Semester to enter.

Random Process and Electromagnetic

Professional English Linear Algebra -
Professional English - - II - HS3252 Fields - EC3452
MA3355
I - HS3152
C Programming and Networks and
Statistics and
Data Structures - Security - EC3401
Matrices and Calculus Numerical Methods -
CS3353
- MA3151 MA3251
1st Semester

3rd Semester

Linear Integrated

4th Semester
2nd Semester

Signals and Systems - Circuits - EC3451

Engineering Physics - Engineering Graphics
- GE3251 EC3354
PH3151 Digital Signal
Processing - EC3492
Physics for Electronic Devices and
Engineering Chemistry Electronics Engg - Circuits - EC3353
- CY3151 PH3254 Communication
Systems - EC3491
Control Systems -
Basic Electrical & EC3351
Problem Solving and Instru Engg - BE3254 Environmental
Python Programming - Sciences and
GE3151 Digital Systems Design Sustainability -
Circuit Analysis - - EC3352 GE3451
EC3251

Wireless
Communication -
EC3501 Embedded Systems
and IOT Design -
ET3491
VLSI and Chip Design
5th Semester

- EC3552 Human Values and

7th Semester

8th Semester
6th Semester

Artificial Intelligence Ethics - GE3791

and Machine Learning
Transmission Lines and - CS3491
RF Systems - EC3551 Open Elective 2 Project Work /
Intership
Open Elective-1 Open Elective 3
Elective 1
Elective-4
Open Elective 4
Elective 2
Elective-5
Elective 3
Elective-6
 All ECE Engg Subjects - [ B.E., M.E., ] (Click on Subjects to enter)
Circuit Analysis Digital Electronics Communication Theory
Basic Electrical and Electrical Engineering and Principles of Digital
Instrumentation Engineering Instrumentation Signal Processing
Electronic Devices Linear Integrated Circuits Signals and Systems
Electronic Circuits I Electronic Circuits II Digital Communication
Transmission Lines and Wave Control System Engineering Microprocessors and
Guides Microcontrollers
Computer Architecture Computer Networks Operating Systems
RF and Microwave Engineering Medical Electronics VLSI Design
Optical Communication and Embedded and Real Time Cryptography and
Networks Systems Network Security
Probability and Random Transforms and Partial Physics for Electronics
Processes Differential Equations Engineering
Engineering Physics Engineering Chemistry Engineering Graphics
Problem Solving and Python Object Oriented Programming Environmental Science
Programming and Data Structures and Engineering
Principles of Management Technical English Total Quality
Management
Professional Ethics in Engineering Mathematics I Engineering Mathematics
Engineering II
 www.BrainKart.com
4931_Grace College of Engineering,Thoothukudi

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

B.E. Electronics and Communication Engineering

Anna University Regulation: 2021

EC3552 – VLSI and Chip Design

III Year / V Semester

Question Bank

Unit – V
ASIC DESIGN AND TESTING

Prepared by,
Mrs. S. Pricilla Mary, AP/ECE

EC3552_VLSI and Chip Design

https://play.google.com/store/apps/details?id=info.therithal.brainkart.annauniversitynotes Page 1 of 5
 www.BrainKart.com
4931_Grace College of Engineering,Thoothukudi

UNIT V – ASIC DESIGN AND TESTING

1. What is meant by CBIC? (Apr/May-17)

A Cell Based ASIC or Cell Based IC is known as CBIC. It uses predesigned logic cells
like AND gate, OR gate, multiplexers & flip-flops.

2. Name the elements in a Configurable Logic Block. (Apr/May-17)

Configurable switch matrix with 4 or 6 inputs Some selection circuitry (MUX, etc.)
Flip-flop
3. What are feed-through cells? State their uses. (May/June-16)
Feed through is a piece of metal used to pass a signal through a cell or to a piece
in a cell. The connection between the rows of standard cell is made by feed through.

4. State the features of full custom design. (May/June-16)

In a Full custom ASIC, an engineer designs some or all of the logic cells, circuits
or layout specifically for one ASIC. It makes sense to take this approach only if there are
no suitable existing cell libraries available that can be used for the entire design.

5. What is standard cell based ASIC design. (Nov/Dec-16)

A cell-based ASIC (CBIC) uses predesigned logic cells known as standard cells. The
standard cell areas also called fle4xible blocks in a CBIC are built of rows of standard
cells. The ASIC designer defines only the placement of standard cells and the interconnect
in a CBIC. All the mask layers of a CBIC are customized and are unique to a particular
customer.

6. What is an antifuse? State its merits and demerits. (Nov/Dec-16)

An antifuse is normally high resistance (>100MΩ). on application of appropriate
programming voltages, the antifuse is changed permanently to a low-resistance
structure(200-500Ω) .

7. Write the various ways of routing procedures. (Nov/Dec-17)

o Global routing architecture
o Detailed routing architecture
o FPGA interconnect routing.

8. Differentiate between channeled and channel less gate array.

Channeled Gate Array Channel less Gate Array

S.No
Only the top few mask layers are
1 Only the interconnect is customized
customized
The interconnect uses predefined No predefined areas are set aside for
2
spaces between rows of base cells routing between cells.
Routing is done using the area of
3 Routing is done using the spaces
transistors
4 Logic density is less Logic density is higher

EC3552_VLSI and Chip Design

https://play.google.com/store/apps/details?id=info.therithal.brainkart.annauniversitynotes Page 2 of 5
 www.BrainKart.com
4931_Grace College of Engineering,Thoothukudi

9. Give the different types of ASIC and give the steps in ASIC design flow.
Types of ASIC:
Full custom ASICs
Semicustom ASICs - Standard cell based ASICs, Gate-array based ASICs
Programmable ASICs - Programmable Logic Device (PLD), Field Programmable
Gate Array (FPGA).
Steps in ASIC design flow:
Design entry
Logic synthesis system partitioning
Prelayout simulation
Floor planning
Placement
Routing
Extraction
Post layout simulation
10. What is FPGA and VLSI? (Nov/Dec-17)
VLSI:
Very-large-scale integration (VLSI) is the process of creating an integrated
circuit (IC) by combining thousands of transistors into a single chip.
FPGA:
A Field Programmable Gate Array (FPGA) is a programmable logic device that
supports implementation of relatively large logic circuits. FPGA can be used to implement
a logic circuit with more than 20,000 gates whereas a CPLD can implement circuits of up
to about 20,000 equivalent gates.

11. What are the types of gate arrays in ASIC?

1) Channeled gate arrays
2) Channel less gate arrays
3) Structured gate arrays

12. What is the full custom ASIC design?

In a full custom ASIC, an engineer designs some or all of the logic cells, circuits or layout
specifically for one ASIC. It makes sense to take this approach only if there are no suitable
existing cell libraries available that can be used for the entire design.

13. What is the standard cell-based ASIC design?

A cell-based ASIC (CBIC) uses predesigned logic cells known as STANDARD CELLS. The
standard cell areas also called flexible blocks in a CBIC are built of rows of standard
cells. The ASIC designer defines only the placement of standard cells and the interconnect
in a CBIC.

14. What is a FPGA?

A field programmable gate array (FPGA) is a programmable logic device that supports
implementation of relatively large logic circuits. FPGAs can be used to implement a logic
circuit with more than 20,000 gates whereas a CPLD can implement circuits ofupto
about 20,000 equivalent gates.

EC3552_VLSI and Chip Design

https://play.google.com/store/apps/details?id=info.therithal.brainkart.annauniversitynotes Page 3 of 5
 www.BrainKart.com
4931_Grace College of Engineering,Thoothukudi

15. What are the different methods of programming of PALs?

The programming of PALs is done in three main ways:
✓ Fusible links
✓ UV – erasable EPROM
✓ EEPROM (E PROM) – Electrically Erasable Programmable ROM

16. What is an antifuse?

An antifuse is normally high resistance (>100M). On application of appropriate
Programming voltages, the antifuse is changed permanently to a low-resistance structure
(200-500)

17. What are the different levels of design abstraction at physical design?
✓ Architectural or functional level
✓ Register Transfer-level (RTL)
✓ Logic level
✓ Circuit level

18. What are macros?

The logic cells in a gate-array library are often called macros.

19. What are Programmable Interconnects ?

In a PAL, the device is programmed by changing the characteristics if the switching
element. An alternative would be to program the routing.

20. Give the steps in ASIC design flow.

a. Design entry
b. Logic synthesis System partitioning
c. Prelayout simulation.
d. Floorplanning
e. Placement
f. Routing
g. Extraction
i.Postlayout simulation

21. Give the XILINX Configurable Logic Block .

EC3552_VLSI and Chip Design

https://play.google.com/store/apps/details?id=info.therithal.brainkart.annauniversitynotes Page 4 of 5
 www.BrainKart.com
4931_Grace College of Engineering,Thoothukudi

22. Mention the levels at which testing of a chip can be done?

a) At the wafer level
b) At the packaged-chip level
c) At the board level
d) At the system level
e) In the field

23. What are the categories of testing?

a) Functionality tests
b) Manufacturing tests

24. Write notes on functionality tests?

Functionality tests verify that the chip performs its intended function. These tests assert that
all the gates in the chip, acting in concert, achieve a desired function. These tests are usually
used early in the design cycle to verify the functionality of the circuit.

25. Write notes on manufacturing tests?

Manufacturing tests verify that every gate and register in the chip functions correctly. These
tests are used after the chip is manufactured to verify that the silicon is intact.

26. Mention the defects that occur in a chip?

a) layer-to-layer shorts
b) discontinous wires
c) thin-oxide shorts to substrate or well

27. What are the scan-based test techniques?

a) Level sensitive scan design
b) Serial scan
c) Partial serial scan
d) Parallel scan

28. What is known as IDDQ testing?

A popular method of testing for bridging faults is called IDDQ or current- supply monitoring.
This relies on the fact that when a complementary CMOS logic gate is not switching, it draws
no DC current. When a bridging fault occurs, for some combination of input conditions a
measurable DC IDD will flow.

PART-B
1. Discuss the different types of programming technology used in FPGA design. (NOV 2016) [D]
2. Draw and explain the operation of metal-metal antifuse and EPROM transistor. (June 2012) [D]
3. Find the reason for referring EPROM technology as floating gate avalanche MOS. (Dec. 2013) [D]
4. Explain the reprogrammable device architecture with neat diagrams. [D] (OR) With neat diagram
explain the functional blocks in PDA (Programmable Device Architecture). (AU: June 2015, June 2016) [D]
5. With neat sketch explain the CLB, IOB and Programmable interconnects of an FPGA device. (May 2016)
[D] (OR) Explain about building block architecture of FPGA. (April 2017, 2018, Nov 2018) [D] (Apr 2019)
(Nov/Dec 2019)
6. Give short notes on FPGA interconnect routing procedures. (May 2016) [D] (Apr 2019) (Nov/Dec 2019)
PART-B (SECOND HALF)
7. What is meant by Ad Hoc testing? Explain in detail? [D]
8. What is meant by Scan Design? Explain in detail? [D]
9. What is BIST? Explain in detail? [D]
10. Briefly explain IDDQ testing? [D]
11. Write short notes on Design for manufacturability? [D]
12. Explain Boundary Scan Testing? [D]

EC3552_VLSI and Chip Design

https://play.google.com/store/apps/details?id=info.therithal.brainkart.annauniversitynotes Page 5 of 5
 Click on Subject/Paper under Semester to enter.
Random Process and Electromagnetic
Professional English Linear Algebra -
Professional English - - II - HS3252 Fields - EC3452
MA3355
I - HS3152
C Programming and Networks and
Statistics and
Data Structures - Security - EC3401
Matrices and Calculus Numerical Methods -
CS3353
- MA3151 MA3251
1st Semester

3rd Semester

Linear Integrated

4th Semester
2nd Semester

Signals and Systems - Circuits - EC3451

Engineering Physics - Engineering Graphics
- GE3251 EC3354
PH3151 Digital Signal
Processing - EC3492
Physics for Electronic Devices and
Engineering Chemistry Electronics Engg - Circuits - EC3353
- CY3151 PH3254 Communication
Systems - EC3491
Control Systems -
Basic Electrical & EC3351
Problem Solving and Instru Engg - BE3254 Environmental
Python Programming - Sciences and
GE3151 Digital Systems Design Sustainability -
Circuit Analysis - - EC3352 GE3451
EC3251

Wireless
Communication -
EC3501 Embedded Systems
and IOT Design -
ET3491
VLSI and Chip Design
5th Semester

- EC3552 Human Values and

7th Semester

8th Semester
6th Semester

Artificial Intelligence Ethics - GE3791

and Machine Learning
Transmission Lines and - CS3491
RF Systems - EC3551 Open Elective 2 Project Work /
Intership
Open Elective-1 Open Elective 3
Elective 1
Elective-4
Open Elective 4
Elective 2
Elective-5
Elective 3
Elective-6
 All ECE Engg Subjects - [ B.E., M.E., ] (Click on Subjects to enter)
Circuit Analysis Digital Electronics Communication Theory
Basic Electrical and Electrical Engineering and Principles of Digital
Instrumentation Engineering Instrumentation Signal Processing
Electronic Devices Linear Integrated Circuits Signals and Systems
Electronic Circuits I Electronic Circuits II Digital Communication
Transmission Lines and Wave Control System Engineering Microprocessors and
Guides Microcontrollers
Computer Architecture Computer Networks Operating Systems
RF and Microwave Engineering Medical Electronics VLSI Design
Optical Communication and Embedded and Real Time Cryptography and
Networks Systems Network Security
Probability and Random Transforms and Partial Physics for Electronics
Processes Differential Equations Engineering
Engineering Physics Engineering Chemistry Engineering Graphics
Problem Solving and Python Object Oriented Programming Environmental Science
Programming and Data Structures and Engineering
Principles of Management Technical English Total Quality
Management
Professional Ethics in Engineering Mathematics I Engineering Mathematics
Engineering II