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DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING

VLSI LABORATORY MANUAL

Subject Code: 21ECL66
VI Semester

PREPARED BY

Dr. SUFIA BANU

ASSOCIATE PROFESSOR
DEPARTMENT OF ECE

SCRUTIZED BY

Dr. LATHA RAJAGOPALAN

PROFESSOR AND HEAD
DEPARTMENT OF ECE
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MISSION AND VISION OF THE INSTITUTION

Mission
 To achieve academic excellence through in-depth knowledge in science,
engineering and technology through dedication, innovation in teaching and
faith in human values.
 To enable the students to develop into outstanding professionals and
entrepreneurs with high ethical standards
 To provide educational opportunities to the deprived and weaker sections of
the society to uplift their socio-economic status

Vision
 To empower students through wholesome education and enable the students to
develop into highly qualified and globally competent professionals with ethics
and emerge as responsible citizens with broad outlook to build a vibrant nation.

MISSION AND VISION OF THE ECE DEPARTMENT

Mission

 To provide the best possible educational experience through excellence in

teaching and research activities for today’s students and professionals of
tomorrow.
 To hone young minds and train them to be conscientious individuals who
will serve the society as competent professionals in the field of Electronics
and Communication Engineering.

Vision
 To shape the students as disciplined humane engineers who can build a
strong, peaceful and vibrant country and focus on mutual respect, tolerance
and professional ethics.
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Programme Educational Objectives

PEO-1 To provide students with a strong foundation in engineering fundamentals

and in the computer science and engineering to work in the global
scenario.

PEO-2 To provide sound knowledge of programming and computing techniques

and good communication and interpersonal skills so that they will be
capable of analyzing, designing and building innovative software systems.

PEO-3 To equip students in the chosen field of engineering and related fields to
enable him to work in multidisciplinary teams.

PEO-4 To inculcate in students professional, personal and ethical attitude to relate

engineering issues to broader social context and become responsible
citizen.

PEO-5 To provide students with an environment for life-long learning which

allow them to successfully adapt to the evolving technologies throughout
their professional carrier and face the global challenges.

PROGRAM OUTCOMES (POs)

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals,

and an engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural sciences,
and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and design
system components or processes that meet the specified needs with appropriate consideration for the
public health and safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
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societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering solutions in
societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable
development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of
the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports
and design documentation, make effective presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the engineering
and management principles and apply these to one’s own work, as a member and leader in a team, to
manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

PROGRAM SPECIFIC OUTCOMES

1. Professional Skills: An ability to understand the basic concepts in Electronics & Communication
Engineering and to apply them to various areas, like Electronics, Communications, Signal processing,
VLSI, Embedded systems etc., in the design and implementation of complex systems.

2. Problem-Solving Skills: An ability to solve complex Electronics and communication Engineering

problems, using latest hardware and software tools, along with analytical skills to arrive cost effective
and appropriate solutions.

3. Employability and Entrepreneurship: An ability to become an entrepreneur or to contribute to

industrial services and / or Govt. organizations in the field of Electronics and Communication
Engineering.

4. Programming Skills: An ability to work on multidisciplinary teams with efficiency in different

Programming techniques
 VLSI LAB 18ECL7

SYLLABUS

11 Design and i. Set

characterize
the input6T signal
binaryto aSRAM
pulse VLSI cellLaboratory
with and
rise measure
time, fallthe timefollowing:
of 1ns and pulse width of 10ns and the
decided jointly by examiners. time period
• Read Time, Write Time, SNM, Power of 20ns and plot the input voltage and output voltage of designed inverter?
Course Code 21ECL66 CIE Marks 50
Students can pick one question • Draw Layoutii.
(experiment)From from
the
ofT:6T the
SRAM, questions
simulation resultlot prepared
compute
use optimum layout by
tpHL, the internal
tpLH and
methods. Verify for /external
td for all
DRC examiners
three geometrical settings
& LVS, extract parasitic of
jointly. Teaching Hours/Week (L: P: S) 0:0:2:0 SEE Marks 50
and performwidth? post layout simulations, compare the results with pre-layout simulations. Record the
Evaluation of testCredits
write-up/observations.
conduction iii. Tabulate
procedurethe and results of delay
result/viva willand find
1 the best
be conducted geometry
jointly for Hours
by examiners.
Exam minimum delay for 3CMOS
inverter?
General rubrics suggested for SEE are mentioned here, writeup-20%, Conduction procedure and result in -60%,
Course objectives:
outcomes (CourseofSkill Set):with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC and
Viva-voce 20% of maximum b) Draw
marks.layout inverter
SEE for practical shall be evaluated for 100 marks and scored marks shall
This
On laboratory
the completion courseof
LVS, extract
be scaled down to 50 marks (however, enables
this
basedparasiticstudents
laboratory
on course and to
course,
perform
type, the students
rubricspostshall will
layout be ableby
simulations,
be decided to:the
compare the results with pre-
examiners).
Change of experiment 
1. is Design,
Design
allowed model,
andonly
layout simulate
simulate
simulations.
once and and
15% verify
combinational
Record
Marks digital
and
the circuits.
sequential
to thedigital
observations.
allotted procedurecircuits
partusing
to be Verilog
made zero. HDL.
2. Design layouts
Understand the and perform
synthesis physical
process of verification
digital
The duration of SEE is 03 hours.Rubrics suggested in Annexure-II of Regulation book circuitsof CMOS
using EDAdigital
tool.circuits.
3. Perform
Perform ASIC
ASIC design
a) Capture design flow
flow and
the schematic and understand
understand
of 2-input the
the process
process
CMOS
of
NANDof synthesis,
synthesis, synthesis
synthesis
gate having
constraints
constraints
similar delay as
and
andthat of CMOS
6 evaluating the synthesis reports to obtain optimum gate level netlist.
evaluating the synthesis
inverter computed reports to obtain optimum
in experiment above. Verifygate level netlist.
the functionality of NAND gate and also find out
4. Perform
Design and RTL-GDSII
simulate flow and
basic CMOS understand
circuits the
like stages
inverter,
the delay td for all four possible combinations of input vectors.
in ASIC.
common source Table
amplifier, differential
the results. Increase the drive
amplifier, SRAM.
strength to 2X and 4X and tabulate the results.
Sl.No. Experiments
5. Performb) DrawRTL_GDSII the layout flow of and
NAND understand
with Wp/Wn the stages in ASIC
= 40/20, design. layout methods. Verify for DRC
use optimum
ASIC Digital Design
Assessment Detailsand LVS, (both CIE and
extract SEE) and perform post layout simulations, compare the results with pre-
parasitic
1 4-Bit layoutAdder simulations. Record the observations.
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The7minimum a)• Capture
Write Verilog
passingschematic
Codeof Common Source Amplifier with PMOS Current Mirror Load and find its
mark for the CIE is 40% of the maximum marks (20 marks). A student shall be deemed
• transient
Verify the response and
Functionality
to have satisfied the academic requirements AC response?
using Test-benchMeasure
and earned thethe Unit Gain
credits allottedBandwidth (UGB),The
to each course. amplification
student hasfactor
to
secure not less by varying
than 35%the
• Synthesize transistor
(18design
Marksby geometries,
outsetting study
of 50)proper the impact
in the constraints
semester-end of variation
andexamination in width
(SEE).
obtain the netlist. to UGB.
Continuous b) Draw
From Internal Layout
the report of common
Evaluation
generated (CIE):source
identify amplifier,
Critical use optimum
path, Maximum layout
delay, Total methods.
numberVerify
of cells,forPower
DRC & LVS,
extract
requirement parasitic
and Total and perform
areaisrequired post layout simulations, compare the results with pre-layout
CIE marks for the practical course 50 Marks.
simulations. Record the observations.
The2split-up
4-BitofBooth
CIE marksMultiplierfor record/ journal and test are in the ratio 60:40.
8 a) Capture schematics of two-stage operational amplifier and measure the following:
 Each •experiment
Writei.Verilog to be evaluated for conduction with observation sheet and record write-up. Rubrics for
UGB Code
the evaluation
• Verifyii.the of the journal/write-up for hardware/software experiments designed by the faculty who is
dBFunctionality
Bandwidth using Test-bench
handling the laboratory session and is made known to students at the beginning of the practical session.
• Synthesizeiii. Gain theMargin
design and phase proper
by setting marginconstraints
with and without and obtaincoupling capacitance
the netlist.
 Record should contain all the specified experiments in the syllabus and each experiment write-up will be
From the iv. Use the op-amp in the inverting and non-inverting configuration andofverify
cells, its
evaluated forreport
10 marks. generated identify Critical path, Maximum delay, Total number Power
requirement functionality.
and Total area required
 Total marks scored by the students are scaled downed to 30 marks (60% of maximum marks).
v. Study the UGB, 3dB bandwidth, gain and power requirement in op-amp by varying the
 3 Weightage
32-Bit ALU to beSupporting
given for neatness
4-Logical andandsubmission
4-Arithmetic of record/write-up oncase
time.and if statement for ALU
stage wise transistor geometries and recordoperations, using
the observations.
 Department
Behavioral shall conduct
Modeling 02 tests for 100 marks, the first test shall be conducted after the 8 th week of the
b) Draw layout of two-stage operational amplifier with minimum transistor width set to 300 (in
semester and the second test shall be conducted after the 14 week of the semester. th
• Write Verilog
180/90/45 nm technology),
Code choose appropriate transistor geometries as per the results obtained in part
 In each test, test write-up, conduction of experiment, acceptable result, and procedural knowledge will
a. •Use optimum layout methods. Verify for DRC and LVS, extract parasitic and perform post
carry a Verify
weightage functionality
of 60% and using
the Test-bench
rest 40% for viva-voce.
layout simulations, compare the results with pre-layout simulations. Record the
 The suitable rubricsthe
• Synthesize can be designed
design targeting to suitable
evaluatelibrary
each student’s performance
and by setting area andand learning
timing ability.
constraints
observations.
Rubrics suggested in Annexure-II of Regulation
• Tabulate the Area, Power and Delay for the Synthesized netlist book
 The average of 02 tests is scaled down Demonstration
to 20 marksExperiments
(40% of the maximum( For CIEmarks).)
• Identify Critical path
The9SumUART of scaled-down marks scored in the report write-up/journal and average marks of two tests is the total
4 Latch
CIE marks •scored and Flip-Flop
Writeby the student.
Verilog Code
 Synthesize the design and compare the synthesis report (D, SR, JK)
• Verify the Functionality using Test-bench
• Synthesize the design targeting suitable
ASIC Analog Design
library and by setting area and timing constraints
HKBK CE 1 Department of
5 a)• Capture
Tabulatethe
theschematic
Area, Power and Delay
of CMOS for the
inverter Synthesized
with netlist, Identify
load capacitance of 0.1pFCritical
and setpath
the widths of
Semester End Evaluation (SEE):
Inverter with
For synthesized Wn =
netlist Wp,out
carry Wnthe
= 2Wp, Wn = Wp/2 and length at selected technology.
following:
10marks
SEE for the Carry
practical course is 50 Marks.
• Floor planningout the following:
SEE shall be conducted and
• Placement jointly by the two examiners of the same institute, examiners are appointed by the
Routing
University • Record the parameters such as no. of metal layers used for routing, flip method for placement of
All laboratorystandard
experiments
cells are to be included for practical examination.
• Physical
(Rubrics) Breakup of Verification
marks and the andinstructions printed
record the DRC andonLVS
the cover
reportspage of the answer script to be strictly
adhered to •byGenerate
the examiners.
GDSII OR based on the course requirement evaluation rubrics shall be
 VLSI LAB 18ECL7
Introduction to VLSI:

What is VLSI?

VLSI stands for "Very Large Scale Integration". This is the field which involves packing more and
more logic devices into smaller and smaller areas. VLSI circuits are everywhere, your computer,
your car, your brand new state-of-the-art digital camera, the cell-hones, and what have you. All this
involves a lot of expertise on many fronts within the same field, which we will look at in later
sections. VLSI has been around for a long time, there is nothing new about it. But as a side effect of
advances in the world of computers, there has been a dramatic proliferation of tools that can be used
to design VLSI circuits. Alongside, obeying Moore's law, the capability of an IC has increased
exponentially over the years, in terms of computation power, utilization of available area. The
combined effect of these two advances is that people can now put diverse functionality into the IC's,
opening up new frontiers. Examples are embedded systems, where intelligent devices are put inside
everyday objects, and ubiquitous computing where small computing devices proliferate to such an
extent that even the shoes you wear may actually do something useful like monitoring your
heartbeats!. Digital VLSI circuits are predominantly CMOS based. The way normal blocks like
latches and gates are implemented in different from what you have seen so far, but the behavior
remains the same. All the miniaturization involves new things to consider. A lot of thought has to go
into actual implementations as well as design. Some of the factors involved are given below.

1. Circuit Delays: Large complicated circuits running at very high frequencies have one big
problem to tackle - the problem of delays in propagation of signals through gates and wires even for
areas a few micrometers across. The operation speed is so large that as the delays add up, they can
actually become comparable to the clock speeds.

2. Power: Another effect of high operation frequencies is increased consumption of power. This has
two-fold effect - devices consume batteries faster, and heat dissipation increases. Coupled with the
fact that surface areas have decreased, heat poses a major threat to the stability of the circuit.

3. Layout: Laying out the circuit components is a task common to all branches of electronics. What
is so special in this case is that there are many possible ways to do this; there can be multiple layers
of different materials on the same silicon, there can be different arrangements of the smaller parts
for the same component and so on.

The power dissipation and speed in a circuit present a trade-off; if we try to optimize on one, the
other is affected. The choice between the two is determined by the way we chose the layout the

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 VLSI LAB 18ECL7
circuit components. Layout can also affect the fabrication of VLSI chips, making it either easy or
difficult to implement the components on the silicon. The two widely used hardware description
languages are VHDL and Verilog. These languages provide support for modeling the system
hierarchically and also supports top down and bottom up design methodologies. The system and its
subsystems can be described at any level of abstraction ranging from the architecture level to the
gate level. The complex constructs and features of these languages are enough to be able to model
designs with high degrees of complexity.

THE VLSI DESIGN PROCESS

A typical digital design flow is as follows:

Specification--- Architecture ---- RTL Coding--- RTL Verification --- Synthesis --- Backend-- Tape
Out to Foundry to get end product….a wafer with repeated number of identical Ics.
All modern digital designs start with a designer writing a hardware description of the IC (using HDL
or Hardware Description Language) in Verilog/VHDL. A Verilog or VHDL program essentially
describes the hardware (logic gates, Flip-Flops, counters etc) and the interconnect of the circuit
blocks and the functionality. Various CAD tools are available to synthesize a circuit based on the
HDL. The most widely used synthesis tools come from two CAD companies. Synposys and
Cadence. Without going into details, we can say that the VHDL, can be called as the "C" of the
VLSI industry. VHDL stands for "VHSIC Hardware Definition Language", where VHSIC stands
for "Very High Speed Integrated Circuit". This languages is used to design the circuits at a high-
level, in two ways. It can either be a behavioral description, which describes what the circuit is
supposed to do, or a structural description, which describes what the circuit is made of. There are
other languages for describing circuits, such as Verilog, which work in a similar fashion. Both forms
of description are then used to generate a very low-level description that actually spells out how all
this is to be fabricated on the silicon chips. This will result in the manufacture of the intended IC.

A typical analog design flow is as follows:

Specifications ---- Architecture---- Circuit Design ------SPICE Simulation--- Layout ---- Parametric
Extraction / Back Annotation---- Final Design ----Tape Out to foundry.

While digital design is highly automated now, very small portion of analog design can be
automated. There is a hardware description language called AHDL but is not widely used as it does
not accurately give us the behavioral model of the circuit because of the complexity of the effects of
parasitic on the analog behavior of the circuit. Many analog chips are what are termed as “flat” or
HKBK CE 3 Department of
 VLSI LAB 18ECL7
non-hierarchical designs. This is true for small transistor count chips such as an operational
amplifier, or a filter or a power management chip. For more complex analog chips such as data
converters, the design is done at a transistor level, building up to a cell level, then a block level and
then integrated at a chip level. Not many CAD tools are available for analog design even today and
thus analog design remains a difficult art. SPICE remains the most useful simulation tool for analog
as well as digital design.

MOST OF TODAY’S VLSI DESIGNS ARE CLASSIFIED INTO THREE CATEGORIES:

1. Analog:
Small transistor count precision circuits such as Amplifiers, Data converters, filters, Phase Locked
Loops, Sensors etc.

2. ASICS or Application Specific Integrated Circuits:

Progress in the fabrication of IC's has enabled us to create fast and powerful circuits in smaller and
smaller devices. This also means that we can pack a lot more of functionality into the same area.
The biggest application of this ability is found in the design of ASIC's. These are IC's that are
created for specific purposes - each device is created to do a particular job, and do it well. The most
common application area for this is DSP - signal filters, image compression, etc. To go to extremes,
consider the fact that the digital wristwatch normally consists of a single IC doing all the time-
keeping jobs as well as extra features like games, calendar, etc.

3. SoC or Systems on a chip:

These are highly complex mixed signal circuits (digital and analog all on the same chip). A network
processor chip or a wireless radio chip is an example of an SoC.

MODEL QUESTIONS

1. Write the Verilog code and test bench for an jk f/f to do the simulation and synthesis
2. Draw the schematic layout for inverter and verify the dc and transient analysis.
3. Write the Verilog code and test bench for jk f/f to do the simulation and system.
4. Draw the schematic for differential amplifier and verify the dc,ac and transient analysis
5. Write the Verilog code and test bench for an d f/f to do the simulation and synthesis
6. Draw the schematic for and layout for common drain and verify the dc , ac and transient
analysis.
7. Write the Verilog code and test bench for t f/f to do the simulation and synthesis.
8. Draw the schematic for differential amplifier and verify the dc, ac and transient analysis.

HKBK CE 4 Department of
 VLSI LAB 18ECL7
9. Write the Verilog code and test bench for an transmission gate to do the simulation and
synthesis.
10. Draw the schematic and layout for common source and verify the dc, ac and transient
analysis.
11. Write the Verilog code and test bench for a 4-bit parallel adder to do the simulation and
synthesis.
12. Draw the schematic and layout for common source and verify the dc, ac and transient
analysis.
13. Write the Verilog code and test bench for a sr f/f to do the simulation and synthesis.
14. Draw the schematic for R-2R DAC and verify the transient analysis.
15. Write the Verilog code and test bench for a transmission gate do the simulation and
synthesis.
16. Draw the schematic for OPAMP and verify the dc, ac and transient analysis.
17. Write the Verilog code and test bench for an SR f/f to do the simulation and synthesis.
18. Draw the schematic for and layout for common source amplifier and verify the transient
analysis.
19. Write the Verilog code and test bench for an 4-bit parallel adder to do the simulation and
synthesis
20. Draw the schematic for OPAMP and verify the dc, ac and transient analysis.
21. Write the Verilog code and test bench for an logic gates to do the simulation and synthesis
22. Write the Verilog code and test bench for an 4-bit sync counter to do the simulation and
synthesis.

VIVA QUESTIONS

1. What are the factors that should be considered in VLSI design?

2. What is simulation?
3. What is synthesis?
4. What is Test bench? How to write it?
5. What is the relationship between ‘λ’ and technology?
6. What is the expansion of ‘ASIC’?
7. Define: DC analysis, AC analysis and Transient analysis.

HKBK CE 5 Department of
 VLSI LAB 18ECL7
8. What is the use of spice code.
9. Define primitive components in Verilog.
10. What is the difference between primitive component and user defined component?
11. What are the different description styles that can be used in Verilog programs.
12. Other than CMOS, What are the technologies available for VLSI design?
13. What is W/L ratio? What is its role in the output?
14. What is the difference between common source and common drain amplifier output? Why is it
so?
15. Name some CAD tools available for complete VLSI design.
16. What is LVS? What is the need for it?
17. What are the advantages of CMOS technology?
18. How does the inversion take place in CMOS inverter?
19. How to construct a buffer using invertors? What is the use of it?
20. What is transmission gate and its symbol?
21. What is the difference between pass transistor and transmission gate. How do they differ from
buffer?
22. What is the ASIC design flow?
23. What is a CMOS structure? Draw the CMOS Schematic of 2 input OR gate.
24. What is the difference between digital and analog circuit design?
25. What is port mapping in Verilog?
26. What is the difference between a buffer and inverter?
27. Expand VLSI?
28. Which 'law' describes the exponential growth of integrated circuit complexity?
29. Difference between CPLD and FPGA.
30. Is verilog/VHDL is a concurrent or sequential language?
31. What is a D-latch?
32. Implement D flip-flop with a couple of latches?
33. Implement a 2 input AND gate using transmission gate
34. What is SPICE?
35. Difference between latch and flip flop

36. What is the difference between wire and reg?

37. What is sensitivity list?
38. If you miss sensitivity list what happens?
39. What is delta simulation time?
40. What's the critical path

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VLSI LAB 18ECL7

VLSI DESIGN FLOW

HKBK CE 7 Department of
VLSI LAB 18ECL7

FIGURE 1: FULL CUSTOM IC DESIGN FLOW

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VLSI LAB 18ECL7

FIGURE 2: SEMI CUSTOM IC DESIGN FLOW

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VLSI LAB 18ECL7

ASIC DIGITAL DESIGN

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 VLSI LAB 18ECL7

EXP 1: FOUR BIT FULL ADDER

module fourbitadder(A,B,C0,S);
input [3:0]A,B;
input C0;
output [3:0]S;
wire C1,C2,C3,C4;
fulladder fa0 (A[0],B[0],C0,S[0],C1);
fulladder fa1 (A[1],B[1],C1,S[1],C2);
fulladder fa2 (A[2],B[2],C2,S[2],C3);
fulladder fa3 (A[3],B[3],C3,S[3],C4);
endmodule

module
fulladder(A,B,CIN,S,COUT); input
A,B,CIN;
output S,COUT;
assign S = A^B^CIN;
assign COUT = (A&B) |
(CIN&(A^B)); endmodule

TESTBENCH

module fourbitadder_t;
reg [3:0] A;
reg [3:0] B;
reg C0;
wire [3:0] S;

fourbitadder uut (.A(A), .B(B), .C0(C0), .S(S));

initial begin
A = 4'b0011;B=4'b0011;C0 = 1'b0;
#10; A = 4'b1011;B=4'b0111;C0 =
1'b1; #10; A = 4'b1111;B=4'b1111;C0
= 1'b1; #10;
end

endmodule

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 VLSI LAB 18ECL7

EXP 2: BOOTH MULTIPLIER

module boothmul(PRODUCT, A, B);

output reg signed [7:0] PRODUCT;
input signed [3:0] A, B;
reg [1:0] temp;
integer i;
reg e;
reg [3:0] B1;
always @(A,B)
begin
PRODUCT =
8'd0; e = 1'b0;
B1 = -B;
for (i=0; i<4; i=i+1)
begin
temp = { A[i], e };
case(temp)
2'd2 : PRODUCT[7:4] = PRODUCT[7:4] + B1;
2'd1 : PRODUCT[7:4] = PRODUCT[7:4] + B;
endcase
PRODUCT = PRODUCT >>
1; PRODUCT[7] =
PRODUCT[6]; e=A[i];
end
end
endmodule

TESTBENCH

module boothmul_t;
reg [3:0] A;
reg [3:0] B;
wire [7:0] PRODUCT;
boothmul uut (.PRODUCT(PRODUCT), .A(A), .B(B));
initial begin
A=0; B=0; #100;
A=1; B=0; #100;
A=7; B=5; #100;
A=-7; B=5; #100;
A=8; B=9; #100;
A=8;HKBK CE #100;
B=-9; 1 Department of
end
endmodule
 VLSI LAB 18ECL7
Output:

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 VLSI LAB 18ECL7

EXP 3: 32 BIT ALU

module alu32(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f; output
reg [31:0]y;
always@(*)
begin case(f)
3'b000:y=a&b; //AND Operation
3'b001:y=a|b; //OR Operation
3'b010:y=~(a&b); //NAND Operation
3'b011:y=~(a|b); //NOR Operation
3'b100:y=a+b; //Addition 3'b101:y=a-
b; //Subtraction 3'b110:y=a*b;
//Multiply default:y=32'bx;
endcase
end
endmodule

TESTBENCH

module alu32_tb;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;
alu32 dut(.y(y),.a(a),.b(b),.f(f)); initial begin
a=32'h00000000;
b=32'hffffffff;
f=3'b000; #10;
f=3'b001; #10;
f=3'b010; #10;
f=3'b011; #10;
f=3'b100; #10;
f=3'b101; #10;
f=3'b110; #10;
end
endmodule

HKBK CE 1 Department of
 VLSI LAB 18ECL7

EXP 4: FLIP FLOPS

D FLIP FLOP

module dff(d,clk,q,qb);
input d,clk;
output reg q=0,qb=1;
always@(posedge clk)
begin
case(d)
1'b0:q=0;
1'b1:q=1;
default:q=1'b0;
endcase
qb=~q;
end
endmodule

TESTBENCH
module dff_t;
reg d;
reg clk;
wire q;
wire qb;
dff uut (.d(d), .clk(clk), .q(q), .qb(qb));
Initial
clk =1;
always #5 clk=~clk;
initial begin
d=0; #10;
d=1; #10;
end
endmodule

HKBK CE 1 Department of
 VLSI LAB 18ECL7

SR FLIP FLOP

module srff(sr,clk,q,qb);
input[1:0]sr;
input clk;
output reg q=0,qb=1;
always@(posedge clk)
begin
case(sr)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=1'bz;
default:q=1'b0;
endcase
qb=~q;
end
endmodule

TESTBENCH
module srff_t;
reg [1:0] sr;
reg clk;
wire q;
wire qb;
srff uut (.sr(sr), .clk(clk), .q(q), .qb(qb));
Initial
clk=1
always #5 clk=~clk;
initial begin
sr=2’b00; #10;
sr=2’b01; #10;
sr=2’b10; #10;
sr=2’b11; #10;
end
endmodule

HKBK CE 1 Department of
 VLSI LAB 18ECL7

JK FLIP FLOP

module jkff(jk,clk,q,qb);
input[1:0]jk;
input clk;
output reg q=0,qb=1;
always@(posedge clk) begin
case(jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q; default:q=1'b0;
endcase
qb=~q;
end
endmodule

TESTBENCH
module jkff_t;
reg [1:0] jk;
reg clk;
wire q;
wire qb;
jkff uut (.jk(sjk), .clk(clk), .q(q), .qb(qb));
initial
clk=1
always #5 clk=~clk;
initial begin
jk=2’b00; #10;
jk=2’b01; #10;
jk=2’b10; #10;
jk=2’b11; #10;
end
endmodule

Output:

HKBK CE 1 Department of
 VLSI LAB 18ECL7
LATCHES
D LATCH

module
dlatch(e,d,q,qb);
input e,d;
output reg q=0,qb=1; always@(e)
begin
if(e)
q=d;
q=~qb
; end
endmodule

TEST BENCH
module dlatch_t;
reg e;
reg d;
wire q;
wire qb;

dlatch uut (.e(e), .d(d), .q(q), .qb(qb));

initial
e=1;
always #3 e=~e;
initial
d=0;
always #10 d=~d;
endmodule

Output:

HKBK CE 1 Department of
 VLSI LAB 18ECL7

SR LATCH

module
srlatch(sr,en,q,qb);
input [1:0]sr;
input en;
output reg q=0,qb=1;
always@(en)
begin
if(en)
case(sr)
2'b00:q=
q;
2'b01:q=0
;
2'b10:q=1;
2'b11:q=1'bz;
default:q=1'b0;
endcase qb=~q;
end
endmodule

TESTBENCH
module srlatch_t;
reg [1:0] sr;
reg en;
wire q;
wire qb;
srlatch uut(.sr(sr), .en(en), .q(q), .qb(qb));
initial
en=1;
always #3 en=~en;
initial begin
sr=00; #10;
sr=01; #10;
sr=10; #10;
sr=11; #10;
end
endmodule

Output:
HKBK CE 1 Department of
 VLSI LAB 18ECL7
JK LATCH

module jklatch(jk,en,q,qb);
input[1:0]jk;
input en;
output reg q=0,qb=1;
always@(en)
begin if(en)
case(jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
default:q=1'b0;
Endcase
qb=~q;
end
endmodule

TESTBENCH
module jklatch_t;
reg [1:0] jk;
reg en;
wire q;
wire qb;
jklatch uut (.jk(jk), .en(en), .q(q), .qb(qb));
initial
en=1;
always #3 en=~en; initial begin
jk=00; #10;
jk=01; #10;
jk=10; #10;
jk=11; #10;
end
endmodule

Output:

HKBK CE 2 Department of
VLSI LAB 21ECL6

ASIC ANALOG DESIGN

HKBK CE 2 Department of ECE

 VLSI LAB 21ECL6

INTRODUCTION
ASIC design GUI Tool display is as shown in figure 1.

To work on analog design go to Analog-tools_Analog design, the displayed analog design

window is as shown in below figure.

HKBK CE 2 Department of ECE

VLSI LAB 21ECL6

Figure 1: Default window of Electric VLSI Design system

_ Click on the file menu to create a new library and enter the new library name.
For ex: analog_design.

Figure 3: to create a new library

HKBK CE 2 Department of ECE
VLSI LAB 21ECL6

HKBK CE 2 Department of ECE

VLSI LAB 21ECL6

_ Right click on the newly created library i.e. analog_design and select new cell and enter
as inverter.

Figure 4:To create a new cell

_ Select inverter under explorer in editor window and go to components. Figure 5 shows
the available options in schematics and layout.

HKBK CE 2 Department of ECE

Figure 5: Options available for schematic and layout
VLSI LAB 21ECL6

HKBK CE 2 Department of ECE

 VLSI LAB 21ECL6
INVERTER
Objective: To design a schematic of an inverter
_ Steps to create a schematic of an inverter
1. Click on the PMOS Transistor in the Schematic Library pane and see the transistor moving
with the cursor when moved from there, now click on the cell to use the PMOS Transistor.

2. Follow the path provided in the below figure to Name the transistor according to the
technology file.

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VLSI LAB 21ECL6

3. After selecting the transistor for naming, check for the text “SPICE MODEL” displayed
on the transistor

4. To change the name of the Transistor to PMOS press “ctrl+I” and change the name in the
below window.

HKBK CE 2 Department of ECE

VLSI LAB 21ECL6

HKBK CE 2 Department of ECE

VLSI LAB 21ECL6

5. Similarly select nmos and set the spice model as nmos and also select power and ground as
shown below.

6. To connect the devices, Hold right control and click on the appropriate device terminal to be
connected. And check for the diagonal line visible in the above figure.

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VLSI LAB 21ECL6

7. Take I/O pins and place it on the schematic.

8. To name the Port click on the Port and Press “ctrl+e” export where u can enter the name.

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VLSI LAB 21ECL6

9. Similarly create export for in, out, vdd and vss pins as shown below.

10. To make a cell view , go to view_make icon view as shown below.edit the icon view
which created under current working library in blue colour as shown below.

HKBK CE 3 Department of ECE

VLSI LAB 21ECL6

HKBK CE 3 Department of ECE

VLSI LAB 21ECL6

11. To test the circuit, right click on the library and then select create new cell as
inveretre_test.

12. Go to components_go to cell_select inverter(ic) to create the test and place it on the
schematic window.connect pins and create exports as shown below.

HKBK CE 3 Department of ECE

VLSI LAB 21ECL6

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VLSI LAB 21ECL6

13. To simulate the circuit the bias and the inputs has to be specified, Go to misc_spice code
and place it on the schematic.select the text and press ctrl+I,select multipline text and enter
spice code as shown.

HKBK CE 3 Department of ECE

VLSI LAB 21ECL6

HKBK CE 3 Department of ECE

VLSI LAB 21ECL6

_ Geometry of transistors

Transistor Width Length

Pmos 20 2

Nmos 10 2

14. Check for the any error in the connections in the circuit as shown in the above figure “Tools
>DRC->Check hierarchically”.
15. To run simulations, tools_simulation(spice)_write spice desk

16. for transient analysis,change dc analysis in spice code by .tran 0 200n

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 VLSI LAB 21ECL6

Objective: To create layout of an inverter

_ Steps to create layout of an inverter.
1. Right click on working library, click on the new cell and select the layout cell, enter the name
of the cell, check the cell is added under the same library of the schematic.

2. Select the PMOS Transistor from the Layout library components pane and set the spice
model as pmos,similarly select nmos and set spice model as nmos as shown below.

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VLSI LAB 21ECL6

3. Select pmos and press ctl+I to change the width .Change the width of the both the transistors
which is same as that of schematic of an inverter i.e. 10 for nmos and 20 for pmos as shown
below.

4. Select p-act from layout editor pane, place it on both sides of pmos and select and set the x-
size of the p-act same as the width of pmos transistor as shown below.

HKBK CE 4 Department of ECE

VLSI LAB 21ECL6

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VLSI LAB 21ECL6

5. To connect, hold on right control on pact and then select pmos. Move p-act from both sides
so that it just coincides with pmos.

6. Similarly place n-act on both sides of nmos. Connect nmos with n-act on both sides and
move n-act from both sides so that it just coincides nmos. to rotate go to
edit_rotate_clockwise 90 degree as shown below.

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VLSI LAB 21ECL6

7. Place the Metal to Poly contact on the cell and connect the gate terminal of the transistors to
form the input port.

8. Short the drains of the both transistors (The Blue line) with the metal. as shown below. Place
the metal to metal contact onto the cell to connect the output port.

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VLSI LAB 21ECL6

9. The transistor generally has the fourth terminal the Substrate/Bulk has to be designed. Place
the N-Well and P-well at the PMOS and NMOS transistor sources respectively. Connect with
pmos and nmos with metal layer and move so that they just coincide.

10. Create export for input and output pins as shown below.

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VLSI LAB 21ECL6

11. After placing all the nodes simulate the design by clicking on tools_Simulation_write
spice deck. The simulation spice window LT-Spice will open as shown above. Click on
the visible traces to select the signal or display as seen in schematic.
12. Check for DRC, ERC, and NCC (LVS) in tools. The analysis of the signals can be done
using the wave form window in the LT-Spice.
_ Spice code for analysis
VDD VDD 0 DC 1.8
VGD GND 0 DC 0
Vin IN 0 PULSE (0 1.8 0 1n 1n 10n 20n)
.dc Vin 0 1.8 1m
.tran 0 200n
.include –path---

HKBK CE 4 Department of ECE

 VLSI LAB COMMON SOURCE AMPLIFIER 21ECL6
Objective: To design schematic and layout of an inverter and also to perform
DRC,ERC,NCC(LVS) and different types of analysis.
_ Steps to design schematic of a Common Source Amplifier.
1. Right click on the current working library and select create new cell for schematic.
2. Click on the components in editor window and select NMOS and PMOS instances ,place
it on schematic window
3. Set the spice model for both instance and set the geometries of transistors as given below.
Transistor Width (w) Length (L)

PMOS 50 1

NMOS 10 1

4. Place VDD and GROUND from editor to the schematic.

5. Add input and output pins and create export for all the as shown below.

3. To Create the symbol go to view_make icon view as shown below .

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VLSI LAB 21ECL6

4. Create test circuit and write the spice code and run the simulations as shown below.

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VLSI LAB 21ECL6

DC ANALYSIS
5. To perform transient analysis, enter .tran 0 5m instead dc analysis in spice code on the
schematic window and the analysis results are shown below.

Transient analysis
6. To perform ac analysis, connect AC voltage between VIN and ground and enter .ac DEC
20 100 500MEG in spice code on the schematic window as shown below.
HKBK CE 4 Department of ECE
VLSI LAB 21ECL6

Ac analysis
HKBK CE 4 Department of ECE
VLSI LAB 21ECL6

_ Steps to design layout of a Common Source Amplifier

1. Right click on current working library and select new cell for layout.
2. Select NMOS and PMOS from layout editor window and place it on layout window and
similarly select N-act, P-act and place it on both sides of NMOS and PMOS respectively.
3. Set the width of transistors, N-act and P-act as that of schematic of Common Drain
Amplifier.
4. Set spice model for NMOS and PMOS.
5. Select PWELL, NWELL for NMOS and PMOS respectively for substrate or bulk
connections.
6. Connect VDD, VSS, input and output as shown below with metal layer.
7. Add input and output pins and create export for all the as shown below and click on
misc_spice code, add the spice code as shown below.
8. Check for DRC, ERC and NCC (LVS).
9. To perform the analysis, go to tools_spice_write spice deck. Compare the results with
the results of schematic.

HKBK CE 5 Department of ECE

 VLSI LAB 21ECL6

DIFFRENTIAL AMPLIFIER
Objective: To design schematic and layout of Differential Amplifier.
_ Steps to design schematic of Differential amplifier
1. Right click on the current working library and select create new cell for schematic.
2. Click on the components in editor window and select NMOS and PMOS instances , place
it on schematic window. Design the circuit with the given configurations as shown
below. Select DC current from spice and connect between VDD and Idc
3. Set the spice model for both instance and set the geometries of transistors as given below.
Transistor Width (w) Length (L)

PMOS(2) 15 1

NMOS1 3 1

NMOS2 4.5 1

4. Place INPUTS, OUTPUT, VDD and GROUND from editor to the schematic.
5. Add input and output pins and create export for all the as shown below.

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VLSI LAB 21ECL6

6. To Create the symbol go to view_make icon view as shown below .

7. Create test circuit and write the spice code and run the simulations as shown below.

HKBK CE 5 Department of ECE

VLSI LAB 21ECL6

DC ANALYSIS
8. To perform ac analysis, connect AC voltage between VIN and ground and enter .ac DEC
20 100 500MEG in spice code on the schematic window as shown below.

HKBK CE 5 Department of ECE

VLSI LAB 21ECL6

Ac analysis
9. To perform transient analysis, enter .tran 0 5m instead Ac analysis in spice code on the
schematic window and the analysis results are shown below.

HKBK CE 5 Department of ECE

VLSI LAB 21ECL6

Transient analysis

_ Steps to design layout of a Differential Amplifier

1. Right click on current working library and select new cell for layout.
2. Select NMOS and PMOS from layout editor window and place it on layout window same
as schematic and similarly select N-act, P-act and place it on both sides of NMOS and
PMOS respectively.
3. Set the width of transistors, N-act and P-act as that of schematic of Common Drain
Amplifier.
4. Set spice model for NMOS and PMOS.
5. Select PWELL, NWELL for NMOS and PMOS respectively for substrate or bulk
connections.
6. Connect
HKBK CEVDD, VSS, inputs and output as shown
5 below with metal layer. Department of ECE
7. Connect all instances same as the schematic connections.
VLSI LAB 21ECL6

8. Add input and output pins and create export for all the as shown below and click on
misc_spice code, add the spice code as shown below.
9. Check for DRC, ERC and NCC (LVS).
10. To perform the analysis, go to tools_spice_write spice deck. Compare the results with
the results of schematic.
11. Perform DC analysis.

HKBK CE 5 Department of ECE

VLSI LAB 21ECL6

HKBK CE 5 Department of ECE

 VLSI LAB 21ECL6

OPERATIONAL AMPLIFIER
Objective:
To design schematic and layout of an operation amplifier and to perform DRC, ERC,
NCC (LVS) and also to perform various types of analysis.
_ Steps to design schematic of an operational amplifier
1. Right click on the current working library and select create new cell for schematic.
2. Click on the components in editor window and go to cell_select diff_amplifier(ic) and
cs_amplifier(ic). Place it on schematic.
3. Place INPUTS, OUTPUT, VDD and GROUND pins from components and create exports
as shown below.

4. To Create the symbol go to view_make icon view as shown below .

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VLSI LAB Page 35
21ECL6

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VLSI LAB 21ECL6

5. Create test circuit and write the spice code and run the simulations as shown below.

HKBK CE 6 Department of ECE

VLSI LAB 21ECL6

DC ANALYSIS
6. To perform ac analysis, connect AC voltage between VIN and ground and enter .ac DEC
20 100 500MEG in spice code on the schematic window as shown below.

HKBK CE 6 Department of ECE

VLSI LAB 21ECL6

Ac analysis
7. To perform transient analysis, enter .tran 0 5m instead Ac analysis in spice code on the
schematic window and the analysis results are shown below.

HKBK CE 6 Department of ECE

VLSI LAB 21ECL6

Transient analysis
_ Steps to design layout of a Operational Amplifier
1. Right click on current working library and select new cell for layout.
2. Select NMOS and PMOS from layout editor window and place it on layout window same
as schematic and similarly select N-act, P-act and place it on both sides of NMOS and
PMOS respectively.
3. Set the width of transistors, N-act and P-act as that of schematic of Common Drain
Amplifier.
4. Set spice model for NMOS and PMOS.
5. Select PWELL, NWELL for NMOS and PMOS respectively for substrate or bulk
connections.
6. Connect VDD, VSS, inputs and output as shown below with metal layer.
7. Connect all instances same as the schematic connections.
8. Add input and output pins and create export for all the as shown below and click on
misc_spice code, add the spice code as shown below.
9. Check for DRC, ERC and NCC (LVS).
HKBK CE 6 Department of ECE
VLSI LAB 21ECL6

HKBK CE 6 Department of ECE

VLSI LAB 21ECL6

10. To perform the analysis, go to tools_spice_write spice deck. Compare the results with the results
of schematic.
11. Perform DC analysis.

HKBK CE 6 Department of ECE

VLSI LAB 21ECL6

DEMONSTRATION EXPERIMENTS

HKBK CE 6 Department of ECE

VLSI LAB 21ECL6
UART

I. Aim: To Write verilog code for UART and carry out the following:
1. Perform functional verification using test bench
2. Synthesize the design targeting suitable library and by setting area and timingconstraints
a. For various constrains set, tabulate the area, power and delay for the synthesized netlist
b. Identify the critical path and set the constraints to obtain optimum gate level
netlist withsuitable constraints

II. Tool Required:

1. Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
2. Synthesis: Genus

III. Block Diagram:

IV. Verilog Code for UART: (File name = uart.v):

a) Functional Verification using Test Bench:

Source Code – Transmitter:

// This code contains the UART Transmitter. This transmitter is able

// to transmit 8 bits of serial data, one start bit, one stop bit,
// and no parity bit. When transmit is complete o_Tx_done will be
// driven high for one clock cycle.
// Set Parameter CLKS_PER_BIT as follows:
// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 25 MHz Clock, 115200 baud UART
// (25000000)/(115200) = 217
module UART_TX
#(parameter CLKS_PER_BIT =

HKBK CE 6 Department of ECE

VLSI LAB 21ECL6
217) (
input i_Clock,
input i_TX_DV,
input [7:0] i_TX_Byte,
output o_TX_Active,
output reg
o_TX_Serial, output
o_TX_Done
);
parameter IDLE = 3'b000;
parameter TX_START_BIT =
3'b001; parameter TX_DATA_BITS
= 3'b010; parameter TX_STOP_BIT
= 3'b011; parameter CLEANUP =
3'b100;
reg [2:0] r_SM_Main = 0;
reg [7:0] r_Clock_Count = 0;
reg [2:0] r_Bit_Index = 0;
reg [7:0] r_TX_Data =
0; reg r_TX_Done = 0;
reg r_TX_Active = 0;
always @(posedge
i_Clock) begin
case (r_SM_Main)
IDLE :
begin
o_TX_Serial<= 1'b1; // Drive Line High for
Idle r_TX_Done<= 1'b0;
r_Clock_Count<= 0;
r_Bit_Index<= 0;
if (i_TX_DV == 1'b1)
begin
r_TX_Active <= 1'b1;
r_TX_Data <=
i_TX_Byte;
r_SM_Main <= TX_START_BIT;
end
else
r_SM_Main <= IDLE;
end // case: IDLE
// Send out Start Bit. Start bit =
0 TX_START_BIT :

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VLSI LAB 21ECL6
begin
o_TX_Serial <= 1'b0;
// Wait CLKS_PER_BIT-1 clock cycles for start bit to
finish if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count +
1; r_SM_Main <= TX_START_BIT;
end
else
begin
r_Clock_Count <= 0;
r_SM_Main <= TX_DATA_BITS;
end
end // case: TX_START_BIT
// Wait CLKS_PER_BIT-1 clock cycles for data bits to finish
TX_DATA_BITS :
begin
o_TX_Serial <=
r_TX_Data[r_Bit_Index]; if
(r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count +
1; r_SM_Main <=
TX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
// Check if we have sent out all
bits if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= TX_DATA_BITS;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <=
HKBK CE 6 Department of ECE
VLSI LAB 21ECL6
TX_STOP_BIT; end
end
end // case: TX_DATA_BITS
// Send out Stop bit. Stop bit =
1 TX_STOP_BIT :
begin
o_TX_Serial <= 1'b1;
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to
finish if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count +
1; r_SM_Main <= TX_STOP_BIT;
end
else
begin
r_TX_Done <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= CLEANUP;
r_TX_Active <= 1'b0;
end
end // case: TX_STOP_BIT
// Stay here 1 clock

CLEANUP :
begin
r_TX_Done <= 1'b1;
r_SM_Main <= IDLE;
end
default :
r_SM_Main <= IDLE;
endcase
end
assign o_TX_Active = r_TX_Active;
assign o_TX_Done = r_TX_Done;
Endmodule

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VLSI LAB 21ECL6

Source Code – Receiver :

// This file contains the UART Receiver. This receiver is able to

// receive 8 bits of serial data, one start bit, one stop bit,
// and no parity bit. When receive is complete o_rx_dv will be
// driven high for one clock cycle.
//
// Set Parameter CLKS_PER_BIT as follows:
// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 25 MHz Clock, 115200 baud UART
// (25000000)/(115200) = 217
module UART_RX
#(parameter CLKS_PER_BIT =
217) (
input i_Clock,
input i_RX_Serial,
output
o_RX_DV,
output [7:0] o_RX_Byte
);
parameter IDLE = 3'b000;
parameter RX_START_BIT =
3'b001; parameter RX_DATA_BITS
= 3'b010; parameter RX_STOP_BIT
= 3'b011; parameter CLEANUP =
3'b100;
reg [7:0] r_Clock_Count = 0;
reg [2:0] r_Bit_Index = 0; //8 bits total
reg [7:0] r_RX_Byte = 0;
reg r_RX_DV = 0;
reg [2:0] r_SM_Main = 0;
// Purpose: Control RX state
machine always @(posedge
i_Clock)
HKBK CE 7 Department of ECE
VLSI LAB 21ECL6
begin
case (r_SM_Main)
IDLE :
begin
r_RX_DV <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index<= 0;
if (i_RX_Serial == 1'b0) // Start bit
detected r_SM_Main <=
RX_START_BIT;
else
r_SM_Main <= IDLE;
end
// Check middle of start bit to make sure it's still low
RX_START_BIT :
begin
if (r_Clock_Count ==
(CLKS_PER_BIT-1)/2) begin
if (i_RX_Serial ==
1'b0) begin
r_Clock_Count <= 0; // reset counter, found the middle
r_SM_Main <= RX_DATA_BITS;
end
else
r_SM_Main <= IDLE;
end
else
begin
r_Clock_Count <= r_Clock_Count +
1; r_SM_Main <= RX_START_BIT;
end
end // case: RX_START_BIT
// Wait CLKS_PER_BIT-1 clock cycles to sample serial data
RX_DATA_BITS :

begin
if (r_Clock_Count < CLKS_PER_BIT-1)
begin

HKBK CE 7 Department of ECE

VLSI LAB 21ECL6
r_Clock_Count <= r_Clock_Count +
1; r_SM_Main <=
RX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
r_RX_Byte[r_Bit_Index] <= i_RX_Serial;
// Check if we have received all
bits if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <=
RX_DATA_BITS; end
else
begin
r_Bit_Index <= 0;
r_SM_Main <=
RX_STOP_BIT; end
end
end // case: RX_DATA_BITS
// Receive Stop bit. Stop bit =
1 RX_STOP_BIT :
begin
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to
finish if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count +
1; r_SM_Main <= RX_STOP_BIT;
end
else
begin
r_RX_DV <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= CLEANUP;
end
end // case: RX_STOP_BIT

// Stay here 1
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VLSI LAB 21ECL6
clock CLEANUP
:
begin
r_SM_Main <= IDLE;
r_RX_DV <= 1'b0;
end
default :
r_SM_Main <= IDLE;
endcase
end
assign o_RX_DV = r_RX_DV;
assign o_RX_Byte = r_RX_Byte;
endmodule // UART_RX

V. Test-Bench Verilog Code for 4-bit adder: (File name = uart_test.v)

// This testbench will exercise the UART RX.
// It sends out byte 0x37, and ensures the RX receives it correctly.
`timescale 1ns/10ps
`include "uart_tx.v"
`include "uart_rx.v"
module UART_TB
();
// Testbench uses a 25 MHz clock
// Want to interface to 115200 baud UART
// 25000000 / 115200 = 217 Clocks Per
Bit. parameter c_CLOCK_PERIOD_NS
= 40; parameter c_CLKS_PER_BIT =
217; parameter c_BIT_PERIOD = 8600;
reg r_Clock = 0;
reg r_TX_DV =
0;
wire w_TX_Active, w_UART_Line;
wire w_TX_Serial;
reg [7:0] r_TX_Byte = 0;
wire [7:0] w_RX_Byte;
UART_RX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_RX_Inst
(.i_Clock(r_Clock),
.i_RX_Serial(w_UART_Line),
.o_RX_DV(w_RX_DV),
.o_RX_Byte(w_RX_Byte)

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VLSI LAB 21ECL6
);
UART_TX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_TX_Inst
(.i_Clock(r_Clock),

.i_TX_DV(r_TX_DV),
.i_TX_Byte(r_TX_Byte),
.o_TX_Active(w_TX_Active),
.o_TX_Serial(w_TX_Serial),
.o_TX_Done()
);
// Keeps the UART Receive input high (default) when
// UART transmitter is not active
assign w_UART_Line = w_TX_Active ? w_TX_Serial :
1'b1; always
#(c_CLOCK_PERIOD_NS/2) r_Clock<= !r_Clock;
// Main Testing:
initial
begin
// Tell UART to send a command (exercise
TX) @(posedge r_Clock);
@(posedge r_Clock);
r_TX_DV <= 1'b1;
r_TX_Byte <=
8'h3F; @(posedge
r_Clock); r_TX_DV
<= 1'b0;
end
endmodule

VI. EXECUTION:

1. Simulation (Design Functionality Verification):

2. Synthesis :

1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {uart_tx.v / uart_rx.v} //Choose any one
3. elaborate
4. read_sdc constraints_top.sdc //Reading Top Level SDC
5. set_db syn_generic_effort medium //Setting effort medium
6. set_db syn_map_effort medium
7. set_db syn_opt_effort
medium 35

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 VLSI LAB 21ECL6
8. syn_generic
9. syn_map
10. syn_opt //Performing Synthesis Mapping and Optimisation

3. Report generation:

11. report_timing > uart_timing.rep

//Generates Timing report for worst datapath and dumps into file
12. report_area > uart_area.rep
//Generates Synthesis Area report and dumps into a file
13. report_power > uart_power.rep
//Generates Power Report [Pre-Layout]
14. report_qor > uart_qor.rep
15. write_hdl > uart_netlist.v
//Creates readable Netlist File
16. write_sdc>uart_sdc.sdc//Creates Block Level SDC

SIMULATION WAVEFORM:

HKBK CE 7 Department of ECE

 VLSI LAB 21ECL6

SYNTHESIS RTL SCHEMATI

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VLSI LAB MANUAL 21ECL66

Department of ECE Engineering Page 78