TRIBHWAN UNIVERSITY

INSTITUTE OF ENGINEERING j Level BIt -

Examination Contnol Division i Prograrnme Bfjl,I3EX. BCT prr. mr.rc ;,i-
2080 Chaitra t-
IYrlrqt 1l{"11i___"
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Atte mpt Atquestions.
The .figures. in r.he
v: .margin indicate Fwll Mafkq..
4.e,.\ttnlc suitabla ciatu tI neca.\,s,art.

1' why power is an impartant tlesign inetrics in embedded

systern? List and explain the
diftbrent design metriis used in
"r]b.dd*d
,yr,.* J"jgr.
2' Design a custom single purpose processor
to find xn shorving all the steps invol,ed.
[1+3]

3' Describe programnler's viet'in the c.ntext of soft,,vare t8l

cle'zelopment for general pulpose
proeessor, Define Debugger, Simulator
and Emulator.
4' [s+3]
pennanence of memorv. consrruct
a Rol.,{lpRoiVr to store dara shown
ffiilffi,:T:age in
[3+sj
Address Inli-rrmation
X Y i l -i*- *-T-_-
,./ --
*\.,illOi1i p i-*_rl
0 0 U I 0
0i I
U

1t 1

_*_--.-.!
1l
ti rirffi
__--_r_*_+___*-_ 1
f

1
L

5' Define interfacirlg. Explain the needs

*u vr
of intertacing. l-)^Irr.ilil priority
'rLvrrswrrrE. Explain rnorlly arbltratlon.
arbitration.
6' [1+2+j]
what are the different situations when context
srvitching is necessary? Explain the details
of steps involved in context switching. comi..i.,
Ftu, pror*rres r.vith process IDs p1, p2,
P3 and P4 with estirnated compietiin time
7,4,1ii'r,r, ,.rp..tiveiy, enters the ready
queue together' Process Ps with completion
time 4 ms enters the ready'queue after 2 rns
the scheduling of procsss P1 siafis. balcuiate of
waiting iime arrd tunraround time for each
proL:ess and average r'vaiting times
and average tuniround time in preernptive
Jcrb First algorithnr. Assume there is shortest
no i/o *ulting for tlie process.
L2+4+ 6)
7 ' Draw the biock diagrarn
of a olosed - ioop control system to conrrol speed in
autornobile' Design the eontrol s,vstem showing an
no oscillatio, and *o unbound output.
ali the stel:s ancl 6erive t'\
\rvrrv\r the co'diti,n lor
l2+6t
tl' Drar'v the top - levei diaglam of a NAND gate using cMos. Expiain
the steps involved
in Full* Custom IC design.
q" List some impartant tbatures [3r-5]
of'805i microcontroller. write an Assemble la,guage
plogram to display 9 to 0 in ccmmon anode
shorv interfaci,g diagram arso.
*'''r'*r LUlrrrwvLULi
7-segment display ,,onn*.i.J at porl I and
e+61
10' Define beha'ioral modei. write a vHDI.,
code fbr 4 * bit tspA i, srructurai moclel,
[3-*5]
{<* *
 TRIBHUVAN III\IIVERSITY Exarn.
INSTITUTE OF ENGINEERING Level - BE Full Marks 80.

Examination Control Division Programme BLli. iltix. BC'f Pass h{arks 12

20?9 Chaitra Year / Part iII I Il 'fime 3 hrs.

Subject: - Embedded System (Cr 655)

Candidates are reqitiretl to gii'e their airsq'ers in their o'*ii1 words as fitr as practicabir:'
Atterytt All qtresti ons. i\ffi
The,figures in the margin indicate Full Markg
Assume suitable data if necessxry.
ts rwffiHil
lu r ffi& ffirts t

i. \\rhat are the ltatules ol an cinb.-iide d s1 i Erpl.tin thertt ri ilh erlinlpLes.

sterir [1]
2. Design a duel purposed processor that takes iu i0 nr-tmbers one at a time and finds
the
average ancl tlie marimuii'r oithe 10 numbers. Shorv algorithrn. FSN4II FSN4 and Datapath
for the processor. iE]

3. Flolv can pipeline be irnplcnrented to irnprove perl'ormance of a processor? \&rite doun

the leatures of a DSP. i4-41
.{. a") Clompose 4Kx5 RON,I using iKx2 }t0iv{. t4l
b) Explain the iinpi,Lct of cache size in perforn:ance o1'ca.che lnefilor-Y. l4i
5. Hor,v cioes Intcrrupl drireit i f) opclrtes r-.iiir Fr:ieii iSR.locaticri. C1c-ar1y'explain the:t,.:i-rs
b-v taking suitable example. i.qi

6. a) Irxplain how RTIIS differ tiom GPOS'I f)ifferentiate hetr.veen thread and process, [3l-3i
b) Four processes r.vith process IDs Pi, P2. P3 and P4 lvith priorities 0.2,4,,5 ancl
estin':ated completion tiine 5, 4. 6 and 4 ms respectiveh,' enter the read.v queue togetiter"
'fwo new piocesses F-5 and P5 with priorities 1, 3 and estinialed completiott time 2 and 3
rns respectivel.v enters the ready queue as: ['5 entcrs 1 ms of slart of execution rvhile F6
enters leady queue after 3 ms cf starl of execution of P4. Calculate WT. TAT, AWT.
ATAT assuming that there is no IiO r,r,aiting {br the process using pre-emptive priorit;*
based aird SJF/SRl'aigodthm. 16l

1" Compare and cr-rnirast betr,l'een operr loop and closed ioop controi s1'stem. Expiain PII)
control system with block diagram and equations. l4+4)
8. What are Full Cusiom IC techn,llogl'ancl Semi-Clustom iC technoiogy'? Explain the steps
inrrolved iir iC r"nanufacturing. [4-r"41

9. Explain data memor,v organization in 8051 microcontrolier. Write an assctnbl,v program

fbr 8051 to count number of 0's in an 8 - bit data stored in ROM at 40H aud result in
RAM at 4lH' [4 1'41

10. Explain different architecture model of VHDL. Write a VHDL code to design a traffic
light contrt>ller unit u,ith necessar,v assumptions using state machiue. t2+61
,i. * {<
 TRIBHUVAN LINIVERSITY M Reqular
INSTITUTE OF ENGINEERING Level Full Marks 80
Examination Control Division Pass Marks 32
2078 Chaitra Year/Part III/[ Time 3hrs.

S*:Uf_"!: ; Egb-g-d-{gd p-ysj-gp cr 6!s)

Candidates are required to give their answers in their own
Attempt All questions.
Thefigures in the margin indicate Full Marks.
Assume suitable data if necessary.

1. Define design metric and explain various design metrics of embedded system. t4]
Z. Design a singie purposed processor that gives the I-,CM of two digit 8-bit numbers. Start
with the algorithm, translate it into state diagram and state transition table. Also clraw the
required data-path. tSl
3. What do you mean b1, pipeline? Explain 5 stage pipelining. Describe features of DSP. [1+3+4]
4. Explain the operation of storing data in one Time Programmable ROM. Compose a
rlremory of size 2k*i*2n using 2k"n sized memory. [3+5]
5" Explain controi methods used for communication in interfacing. Describe Daisy-Chain
arbitration with the help of a block diagram and steps. [3-r-5]
6. Briefly explain the difTerent states of task. Consider three processes with process IDs Pl,
P2, P3 aod P4 with estimated completion time 53,17,68,24 ms respectively, enters the
ready queue together in order P1, P2, P3, P4. Calculate u,aiting time andturn around time
for each process and average waiting times and average turn around time in Round Robin
algorithm with tirne slice 4 ms. Assume there is no IiO waiting for the process. List
Coffman Condition for deadlock. L4+6+21
v. Differentiate betu,een open - loop and close - loop control system. Design control system
tor an automobile cruise control in open - ioop control system using P control. 12+61
8. Discuss the advantages and disadvantages of full-custonr IC technology. Explain the basic
steps of photo lithography process. i8l
9. I{ow are microcontrollers diffbrent from microprocessors? Write the ftatures of 8051
microcontroller. Assume that XTAI = I 1.0592 MHz, write a program to generate a
square wave of I kTIz &equency on pin P1.5 of 8051 microcontroller using timer. l2+2+41
10. Drawlhe state diagram for a sequence detector for the sequence 1011 and then develop a
VHDL code based on the state diagram. [3+5]

*r(Cr
 TRIBHUVAN LINIVERSITY
INSTITUTE OF ENGINEERING
Examination Control Division
2077 Chultra

Sabject: ; Embe_d-ded_ System (CT. 6s S)

candidates are required to give their answers in
their own worrls as far as practicable.
Attempt All questions.
The figures in tlte margin indicate
{ull tVarks,

l. Explain different purpose of ernbedded system with

examples. I4l
2' Design a single phase prclcessor that output Fibonacci
nurnbers upto ,n' places. What are
the optimization,ppurtunities in singre prpor* p.o".rrorr.
[5+3j
3' Explain the architecture of general purpose processor,
what are the criteria to seiect the
processor?
V+AJ
4' Design the internal architecture of 4x4 Rolv{. Explain the memory
""-"r write ability and
storage perrnanence with suitable example.
[3+5]
5' Define interfacing and rvrite about needs of interfacing.
Explain priority. artritration with
[3+5]
6' Compare task, process ancl threads. Three processes
with process IDs pl, p2, p3 with
estimated completion times 6, 8, milliseconds respectively enters the ready queue
together' Process P4 with estimated,2execution ."*pl.iion
time 4 milliseconcls enters the
ready queue after I millisecond. calculate ttre lvaiting
time and turn around time for each
process and the AwT and TAT in the..on-pr.r*-ptive
Describe basic function of rear tirne kerner
shortest
gvur Jvv a' scheduling.
]ot, first
[4+5+5]
7. Explain <lifTerent pertbrmance metric.s of coutrol s)1stem
response diagram. write an aigorithm fbr a plD -"*"--D
--- using suitabie perloruarrce
controi,
wt4)
8' Describe briefly about semi custom IC technology.
Explain the various
*rrvuo rLvl
steps involved in
photolithography.
i6l
9' Explain different configuration fbr seven segment display.
^r' write uJnw,rt'J
design a down counter that counts from 99
t ' an assembly program to
tc oo.
[2+6]
10. using structurar moclel, write a coire i, VHDL
to implement f,lr adder.
Ig]
,(**
 TRIBHUVAN LINIVERSITY Exam. ,irr,t&!k! ,,:.,, r, , ,.,lfiegUlai t,,t *;.T
INSTIT'UTE OF ENGINEERING LeveI BE Full Marla 80
Exarnination Control Division Programme BEX, BCT PassMarks 32
2076Bhadra Year / Part m/II Time 3 hrs.

_* su!jes!!::3,$j*{!nrru
to their answers in their own words as far *
t/ Attempt
lTj:3t::,T:::1:ir:d
Al!questions.
give
n.**il--
,, Thefigures in the margin indicate Full Marks.
{ Assume suitable data if necessary.

1' Define Embedded System and classify the embedded

system based on generations. What
using ,Bury7wait,.
is task synchronization and exprain the task synchronization
[4+4]
2' Design a custom single-purpose processor that display
I or 0 if the input integer is prime
or not showing all the steps.
tgl
3' Explain the design flow of embedded software developrnent.
Explain in brief about
programmer's view for general purpose processor.
14+41
4' Define two characteristics of memory: write ability and
storage pennanence with their
diffeient levels. Explain replacement algorithm, ,r.d in
cache ,i..nory. [5+3]
5' What is intenupts? How intenupt needed in digital devices?
write a summary of flow of
actions for interrupt driven I/o using fixed ISRlocatio,.
6' Explain process life cycle u'ith process state diagram. Ti,'ee processes r.vith process [2+3+3]
P7,P2, P3 IDs
estimated completion tirne 8, O. iO ms and priorities
"vith 0, 3,2 (g-highest,3-
lou'est) respectively, enters the ready queue togethei in order pl,p2,p3 (assume
only p1
is present in the Ready queue rvhen- tlie.schedller picks
it up and pi p3 enter ready
queue after that). Nolt'a process P4 ri'ith estimatei
completion time 6"nams and priority 1
enters the ready queue after 5 ms of execuiion of
P 1 . Calculate waiting time and TAT {bi.
each process and average rvaiting time and rAT.
Assr-rme there is no iio waiting for.tlie
processes and priority
-based scheduling
[3+5]
7 ' Explain the matrices used to
measure the control objectives. Explain soft,uvare
coding of
PID controller.
L4+41
8' Discuss the advantages and disadvantages of Fuli-custom
iC tecirnology. Explain
basic steps of photoiitrrography process. the
L2+61
9' Generate a periodic square wave having a period
of 15 rns and a duty cycle of 2ayo in
8051 usinSl assembil'prog,amming. The wavefo'n
sliould be produce;'ui;in zero of pofi
tlo (P2'0). the XTAL fi'equency is 1t.0592 MFiz andr.,r.
ii*., I in mode 0 (13-bit
timer mode)
10' write an algo'ithtn anci VI-IDL code for custom single purpose processor
that calculates
tire Gieatest conmon Divisor (GCD) of trvo nr*berf
as-Finite State Machine.
Lz+6J
***
 TRIBHWANTJNWERSITY Exam. , Back. ' :

. INSTITUTE OF ENGINEERING Level BE Full Marks 80

Examination Control Division Programme BEX, BCT Pass Marks ' 32

2075 Baisakh Year / Part m/II Time 3 hrs.

Subjeet: - Embedded System (CT 655)

Candidates are required to give their answers in their own words as far as practicable.
Attempt All questions.
The figures in the margin indicate FuIl Motkl
Assume suitable data if necessary.

l. Defirie design metic. Explain all important desigu metrics of a%ysem. 14)

2. Design a single purpose processor to determine &e sum of digits of an integer. Start the
design from thE function computing the desired resulL FSMD, datapath and controller. t8l
J. a) Explain with diagram about pipelining? t4I
b) Briefly explain suitabie criteria for selecting Microprocessor in Embedded system. t4I
4K x 16 ROM lK x 8 ROMs. Determine which cache is better: [5+3]

Which VO fuort based or bus based) is used in 8051 Microcontroller, describe in briefl
Explain structure, operation, advantages and disadvantages of daisy chain arbitration
method' [2+6]
a) Define kernel and explain its types. Explain file system handling of kernel. [3+3]
b) Tkee processes with process IDs PI, P2, P3 with estimated completion time 7, 8, 5
ms and priorities A, 3,2 (0-highest, 3-iowot) respectively, enters the ready queue
together in order Pl, P2, P3 (assume only Pl is present in the ready qrieue when the
scheduler picks it up and P2 andP3 enter ready queue after that). Now a process P4
with estimated completion time 10 ms and priority 1 enters the ready queue after 5ms
of execution of Ptr. Calculate waiting time and TAT for each process and *verage
waiting time and TAT. Assume there is no VO waiting for the process and priority -
based scheduling. l6l
7. a) Difi::rentiate betrveen open loop and close loop control system. Which system is
better for control system? 14l

b) \Vhat is PID controilers? Expiain iis type u4th real time application in embedded
systern. t4l
Explain about PORT 3 of 805i microcontroller. Using8051 insir,-rciions, controi rate of
bliri. cf I-ED at pin Pi.1 by two sr,i,itchcs at P2.1 and P2.2 ( One switch to itrcrcase the
rate cf blink, another tc decrease tl:e rate oi'biink) [2+6]
9. Whai's the use oi \,'IIDL code in cr:rire ddsci system? Dcsigl anci urite a ccdc for Decodcr
using VI{DL. [2+6]
!

1u Briefly explain semi-custom (ASIC) IC technology and write about its types. Explain IC
manufacturing steps of circuit given below [3+5]

A"{

0"J
..,. ,9
 TRIBHUVAN UNIVERSITY Exam.
INSTITUTE OF ENGINEERING Level BE Full Marks 80

Examination Control Division Programme BEX, BCT Pass Marks 32

2075 Bhadra Year lPart ru/il Time 3 hrs.

{y" !t: fi : Emp {de $

-e
S*qf"_ € r -6_1
s
)
Candidates are required te give their answers in their own rvords as far as practicable.
Artentpt 4ll questions.
The.figures in the margin inrlicate Fwtl Marlts,
Assume suituhle data if necessary.

1. What is an embedded system? Differentiate it with non embedded systems with suitable
example. In RTOS, describe mutual exciusion tluough sleep aud wake tor task
synchronization. [1 +3+4]
) What is Optimization? What are the parameter you consider for Optimization of single
purpose processors. l4+4]
J. Define daiapath and contrcller of a general purpose processor. Explain ASIP with its
types. L4+41

4. Define write ability and storage perrnanence of memory. Design a ROlvi to store the
following infonnation:_ [3+5]
x Y Z F1 F2 F3 F4
0 0 0 0 U i 0
0 0 1 1 1 0 0
0 1 0 0 1 0 1

0 1 I 1 1 I 1

1 0 0 0 0 1 I
1 0 1 0 1 0 1

1 1 0 1 0 I 0
I 1 1 0 0 1 1

5. a) What is intemrpt? Explain summarv of flow of actions of, interrupt driven IIO using
fixed ISR location. I4l
b) What is arbitration? With neat diagram explain Daisy-chain arbitration. I4:I

6. Explain the conditions favoring deadlock situation. Three Processes P1, P2 and P3 with
estimated completion time 5, 8, 7 ms respectively enters the ready queue together.
Calculate WT, TAT for each process and calculate AWf and ATAT using Round Robin
Pre-emptive scheduling algorithms u'ith tirne slice of 2 ms. [2+6]
7. Differentiate between closed - loop and open * loop control systems. Draw a typical
block diagram of a PID control system and describe PID turning. [3+s]
8. Draw a top down view and schematic for the following function: F : xz * yz'.Describe
with suitable diagram about positive photoresist used in photolithography. [5+3]
9. What is seven segment display and write its types. Design a circuit with 7 segments
display which is used as a counter watch which display second and minute. L2+61

10. Explain different models is VHDL. Write a VHDL code for a firll adder using two half
adders and one OR gate in structural model. [3+5]

{.**