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DPCO Revision

The document outlines the model examination for the Digital Principles and Computer Organization course at Arunai Engineering College, detailing the exam structure, including parts A, B, and C with specific questions. It includes topics such as logic circuits, flip-flops, data hazards, instruction formats, and memory concepts. The examination is scheduled for December 29, 2023, with a maximum score of 100 marks.

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renugasoundharya
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11 views3 pages

DPCO Revision

The document outlines the model examination for the Digital Principles and Computer Organization course at Arunai Engineering College, detailing the exam structure, including parts A, B, and C with specific questions. It includes topics such as logic circuits, flip-flops, data hazards, instruction formats, and memory concepts. The examination is scheduled for December 29, 2023, with a maximum score of 100 marks.

Uploaded by

renugasoundharya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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​ Reg. No: b. Design Mod-7 synchronous counter using JK flip-flop.


5104 - ARUNAI Reg. No:
ENGINEERING COLLEGE 5104 – ARUNAI ENGINEERING COLLEGE
TIRUVANNAMALAI TIRUVANNAMALAI
104 - COMPUTER SCIENCE AND ENGINEERING 104 - COMPUTER SCIENCE AND ENGINEERING
YEAR: II ​ ​ ​ SEMESTER: III YEAR: II ​ ​ SEMESTER: III
SET-A SET-A
MODEL EXAMINATION - NOV/DEC 2023 MODEL EXAMINATION - NOV/DEC 2023
CS3351-DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION CS3351-DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION
___________________________________________________________________ ___________________________________________________________________
Date: ​ 29.12.23 (FN) ​ ​ Maximum: 100 Marks Date: ​ 29.12.23 (FN) ​ ​ Maximum: 100 Marks
Time: ​ 09:30 am-12:30 pm​ ​ ​ ​ ​ Time: ​ 09:30 am-12:30 pm​
Answer ALL questions Answer ALL questions
PART – A (10X2 =20 Marks) PART – A (10X2 =20 Marks)
1.​ Construct half adder and full adder 1.​ Construct half adder and full adder
2.​ Evaluate the logic circuit of 2-bit comparator. 2.​ Evaluate the logic circuit of 2-bit comparator.
3.​ Define latch and flip-flop. 3.​ Define latch and flip-flop.
4.​ Difference between synchronous and asynchronous sequential circuit. 4.​ Difference between synchronous and asynchronous sequential circuit.
5.​ What is von Neumann bottleneck? 5.​ What is von Neumann bottleneck?
6.​ What are data transfer instructions? 6.​ What are data transfer instructions?
7.​ Draw the data path segment of ALU and load word and store word 7.​ Draw the data path segment of ALU and load word and store word
instructions. instructions.
8.​ Define data hazard and control hazard. 8.​ Define data hazard and control hazard.
9.​ Define locality of reference. 9.​ Define locality of reference.
10.​ Define hit rate or hit ratio and TLB. 10.​ Define hit rate or hit ratio and TLB.
PART – B (5X13 =65Marks) PART – B (5X13 =65Marks)
11.​ a. Design the 4-bit Magnitude Comparator with truth table and logic 11.​ a. Design the 4-bit Magnitude Comparator with truth table and logic
diagram. diagram.
Or Or
b. i. Simplify the given Boolean function F(a,b,c,d)=(0,1,2,5,8,9,10) into b. i. Simplify the given Boolean function F(a,b,c,d)=(0,1,2,5,8,9,10) into
SOP and POS form and implement using basic gates (5) SOP and POS form and implement using basic gates (5)

ii. Design octal to binary encoder. Solve this problem using 3 to 8 decoder ii. Design octal to binary encoder. Solve this problem using 3 to 8 decoder
f1(x2,x1,x0)=∑m(0,1,3,4,5,6) & f1(x2,x1,x0)=∑m(1,2,3,4,6) (8) f1(x2,x1,x0)=∑m(0,1,3,4,5,6) & f1(x2,x1,x0)=∑m(1,2,3,4,6) (8)

12.​ a. What is shift register? Outline the design of 4 bit shift register with a 12.​ a. What is shift register? Outline the design of 4 bit shift register with a
diagram(all types). diagram(all types).
Or
b. Design Mod-7 synchronous counter using JK flip-flop. Mrs. A.Winni de Leo, AP/CSE ​ Mrs.V.Umadevi
Ms. E.Saranya, AP/CSE​ HOD/CSE
13. a. Elaborate the various instruction formats: I-Format, J-Format, R-Format 13. a. Elaborate the various instruction formats: I-Format, J-Format, R-Format
instructions with examples. instructions with examples.
Or Or
b. Explain the following Byte Addressability, Big-endian b. Explain the following Byte Addressability, Big-endian
Assignment, Little-endian Assignment and word alignment. Assignment, Little-endian Assignment and word alignment.

14. a. Draw and explain the simple data path with the control unit and explain the 14. a. Draw and explain the simple data path with the control unit and explain the
execution of ALU instructions. execution of ALU instructions.
Or Or
b. Explain the different types of pipeline hazards with suitable examples. b. Explain the different types of pipeline hazards with suitable examples.

15. a. i. Present an Outline of interrupt driven I/O. (5) 15. a. i. Present an Outline of interrupt driven I/O. (5)
ii. Outline direct memory access with diagram and give the modes of DMA ii. Outline direct memory access with diagram and give the modes of DMA
transfer. (8) transfer. (8)
Or Or
b. Present an outline of virtual memory concept, concept of paging, b. Present an outline of virtual memory concept, concept of paging,
virtual to physical address translation buffer, page fault and demand virtual to physical address translation buffer, page fault and demand
paging. paging

PART – C (1X15 =15Marks) PART – C (1X15 =15Marks)

16. a. A sequential circuit with 2 D flip-flop A&B and input X and output Y is 16. a. A sequential circuit with 2 D flip-flop A&B and input X and output Y is
specified by the following next state and output equation specified by the following next state and output equation
A(t+1)=AX+BX A(t+1)=AX+BX
B(t+1)=A’X B(t+1)=A’X
Y=(A+B)X’ Y=(A+B)X’
Draw the logic diagram of the circuit, derive the state table and also draw Draw the logic diagram of the circuit, derive the state table and also draw
state diagram. state diagram.
Or Or
b. Outline the design of 3 to 8 line decoder circuit using inverters and AND b. Outline the design of 3 to 8 line decoder circuit using inverters and AND
gates and present the truth table for the same. gates and present the truth table for the same.

Prepared By,​ ​ ​ ​ Verified By,


Prepared By,​ ​ ​ ​ Verified By,
Mrs. A.Winni de Leo, AP/CSE ​ Mrs.V.Umadevi
Ms. E.Saranya, AP/CSE​ HOD/CSE

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