Lecture Seven 8085 Interrupts

Lecture Seven
8085 Interrupts

1. Interrupts
Interrupts are the signals generated by the external devices to request the
microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5,
RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter:
 Vector interrupt: In this type of interrupt, the interrupt address is known to
the processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
 Non-Vector interrupt: In this type of interrupt, the interrupt address is not
known to the processor so, the interrupt address needs to be sent externally
by the device to perform interrupts. For example: INTR.
 Maskable interrupt: In this type of interrupt, we can disable the interrupt by
writing some instructions into the program. For example: RST7.5, RST6.5,
RST5.5.
 Non-Maskable interrupt: In this type of interrupt, we cannot disable the
interrupt by writing some instructions into the program. For example: TRAP.
 Software interrupt: In this type of interrupt, the programmer has to add the
instructions into the program to execute the interrupt. There are 8 software
interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.

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Lecture Seven 8085 Interrupts

 Hardware interrupt: There are 5 interrupt pins in 8085 used as hardware

interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA. Figure (1.1)

Figure (1.1) 8085 interrupts Pins

Interrupts PINs are used by I/O devices to initiate data transfer to or from 8085,
without wasting any of the Central Processing Unit(CPU) time.

1.2 Enabling, disabling and masking of interrupts

There are two software instructions EI and DI associated with the interrupt
system. The EI instruction enables the interrupts while the DI instruction disables
all the interrupts except TRAP. Once any interrupt has been acknowledged, the
interrupt system is disabled automatically. However, TRAP is not disabled even
now. Because of this, TRAP is called the highest priority interrupt.
Various interrupts can be enabled or disabled selectively by masking. There is
an interrupt mask register in the interrupt control system Figure (1.2).

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Lecture Seven 8085 Interrupts

Various bits of this register are used for enabling or disabling of interrupts
- The first 3 bits—bit 0, bit 1, and bit 2—are devoted to interrupt masks for
RST 5.5, RST 6.5 and RST 7.5 interrupts respectively. If any of these bits is set
to 1, the particular interrupt is disabled, otherwise it is enabled.
- Bit 3 is the overriding bit for bit 0, bit 1, and bit 2. This bit is called the Mask
Set Enable (MSE). Only when this bit is set to 1, the mask bits for interrupts
RST 5.5, RST 6.5, and RST 7.5 are taken into consideration.
- Bit 4 is used to reset the RST 7.5 latch. When this bit is set to 1, the latch
associated with the RST 7.5 interrupt is reset regardless of whether RST 7.5
is masked or not.
- Bit 5 is not used.
- Bit 6 and bit 7 are devoted to serial output.

Figure (1.2) interrupts mask register

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Lecture Seven 8085 Interrupts

example, if we want to enable RST 7.5 and RST 5.5 and disable RST 6.5, the bit
pattern will be
0 0 0 1 1 0 1 0 = 1AH
The user will transfer 1AH to ACC and execute the SIM instruction (Set Interrupt
Mask).
If the user wishes to know about the status of the various interrupts, i.e.
whether they are enabled and whether any interrupt is pending on these lines. This
is facilitated by the RIM (Read Interrupt Mask) instruction.

1.3 Interrupt Service

When I/O port activates one of the interrupts Pins, the 8085 gets interrupted if
the following conditions are satisfied
1- The interrupt system is enabled by the (IE) interrupt enable.
2- The interrupt pin has not been masked
3- Higher interrupts are not active at the same time.

When an interrupts occur, the following action will be taken by the 8085 as shown
in figure (1.3)
1- It completes the execution of the current instruction>
2- Stores on the stack top the address of the next instruction, called the return
address which is present in the program counter(PC).
3- Program branches a subroutine called (interrupt service subroutine ISS) A
small program or a routine that when executed, services the corresponding
interrupt.

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Lecture Seven 8085 Interrupts

4- Normally the ISS consists of three portions:

a- The first portion is used for saving on stack all the value of 8085 registers
that might be used later by the routine using PUSH instruction.
b- The next portion will have instruction to achieve the purpose of the
interrupt. If it is data transfer, IN / OUT instruction will be used.
c- After the ISS is complete, the control will return to the program that was
interrupted. This is done by popping the top of the stack information to
the (PC) using (RET) instruction at the end of the ISS program.

Figure (1.3) interrupt steps

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Lecture Seven 8085 Interrupts

1.4 Hardware Interrupts

An external device, initiates the hardware interrupts of 8085 by placing an

appropriate signal at the interrupt pin of the processor. The processor keeps on
checking the interrupt pins at the second T -state of last. machine cycle of every
instruction. If the processor finds a valid interrupt signal and if the interrupt is
unmasked and enabled, then the processor accepts the interrupt. The acceptance
of the interrupt is acknowledged by sending an INTA signal to the interrupted
device.

Priority of 8085 interrupts

1.4.1 Reset IN and Reset OUT

RESET IN:
This pin is used for hard resting the microprocessor. It works on active low
signal. When the signal on this pin is low for at least 3 clocking cycles, it forces the
microprocessor to hard reset itself. Resetting the microprocessor means,

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Lecture Seven 8085 Interrupts

1- It Clears the PC and IR.

2- Disabling all interrupts (except TRAP).
3- Disabling the SOD pin.
4- All the buses (data, address, control) are tri-stated.
5- Gives HIGH output to RESET OUT pin.

RESET OUT:
RESET OUT is used to reset the peripheral devices and other ICs present on the
circuit. It is an output signal. It works on active high signal. The output on this pin
goes high whenever RESET IN is given low signal. The output remains high as long
as RESET IN is kept low.

1.4.2 INTR and INTA

INTR is an active high pin. This is having the lowest priority. It can interrupt the
8085 only if the 8085 is not required to service any other interrupt at the same
time. INTR is a maskable interrupt. It is a general purpose interrupt. By general
purpose we mean that it can used at vector microprocessor to any specific
subroutine having any address.
INTA stands for interrupt acknowledge. It is an outgoing signal. It is an active low
signal. Low output on this pin indicates that microprocessor has acknowledged the
INTR request.

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Lecture Seven 8085 Interrupts

1.4.3 TRAP
It is non maskable interrupts. TRAP has the highest priority and it is vectors
interrupt. In case of sudden power failure, it executes a ISR and send the data from
main memory to backup memory. it has the highest priority, it need not be enabled
and it cannot be disable.

1.4.4 RST 5.5 and RST 6.5

RST6.5 has a higher priority than RSTS.5. RST5.5 in turn has higher priority than
INTR. The function of RST5.5 and RST6.5 are very similar. These pins should remain
high till the 8085 checks all the internal interrupt signals at about the end of an
instruction. As can be easily seen from Fig. 18.7, the RST5.5 and RST6.5 internal
interrupt signals are activated only when

1. These external interrupt pins are in logic 1 state;

2. IE flip-flop is in logic 1 state;
3. These interrupts are not masked by the SIM instruction.

The 8085 gets interrupted because of RST5.5 or RST6.5 pin, only if the following
conditions are met.
1. RSTS.5 or RST6.5 internal interrupt signal is active;
2. Higher priority internal interrupt signals are not active.
If these conditions are not met, even though RST5.5 or RST6.5 pins are activated,
the 8085 does not get interrupted. In such a case, these pins should remain high till
these conditions are met in order to interrupt the 8085.

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Lecture Seven 8085 Interrupts

As we always start with a reset of the 8085, because of the switching on of the
microcomputer system, all interrupts except TRAP are disabled to start with. So, if
we want these pins to interrupt the 8085, it is necessary that we have EI instruction
in our program. The interrupt system will then be enabled after executing the next
instruction after EI.
RST5.5 and RST6.5 are vectored interrupts in 8085. By this we mean that the
8085 knows by itself the starting address of the ISS. It is 5.5 * 8 = 002CH in the case
of RSTS.5, and 6.5 * 8 = 0034H in the case of RST6.5. The action taken by 8085 when
RST5S.5 or RST6.5 is activated.

1.4.5 RST 7.5

RST7.5 pin is used by peripherals that send a pulse, rather than a sustained high
level, for interrupting the processor. RST7.5 internal interrupt signal has a higher
priority than the internal interrupt signals of RST6.5, RST5.5. The RST7.5 internal
interrupt signal is activated only when
1. Q output of the RST7.5 flip-flop is at logic 1;
2. IE flip-flop is in logic 1 state;
3. RST7.5 interrupt is not masked by SIM instruction.
The 8085 gets interrupted because of RST7.5 pin, only if the following conditions
are met.
1. RST7.5 internal interrupt signal is active;
2. TRAP internal interrupt signal is not active.
If these conditions are not met, even though a rising edge occurs on RST7.5 pin,
the 8085 does not get interrupted. As we always start with a reset of the 8085,
because of the switching on of the micro- computer system, all interrupts except

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Lecture Seven 8085 Interrupts

TRAP are disabled to start with. So, if we want the RST7.5 pin to interrupt the 8085,
it is necessary that we have EI instruction in our program. The interrupt system will
then be enabled after executing the next instruction after EI.
RST7.5 is a vectored interrupt in 8085. By this we mean that the 8085 knows by
itself the starting address of the ISS. It is 7.5 * 8 = 003CH. The action taken by 8085
when RST7.5.

1.4.6 hardware interrupt summary

Shown below is a table of summery of the 8085 hardware interrupts

8085 hardware interrupts summery

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Lecture Seven 8085 Interrupts

1.5 software Interrupt

The software interrupts are program instructions. When the instruction is
executed, the processor executes an interrupt service routine stored in the vector
address of the software interrupt instruction. The software interrupts of 8085 are
RST 0, RST 1, RST 2, RST 3, RST 4, RSTS, RST 6 and RST 7.
The vector addresses of software interrupts are given in table below.

The software interrupt instructions are included at the appropriate (or required)
place in the main program.
When the processor encounters the software instruction:
1- It pushes the content of PC (Program Counter) to stack.
2- Loads the Vector address in PC and starts executing the Interrupt Service
Routine (ISR) stored in this vector address,

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Lecture Seven 8085 Interrupts

3- At the end of ISR, a return instruction - RET will be placed. When the RET
instruction is executed, the processor POP the content of stack to PC. Hence
the processor control returns to the main program after servicing the
interrupt. Execution of ISR is referred to as servicing of interrupt.

All software interrupts of 8085 are vectored interrupts. The software interrupts
cannot be masked and they cannot be disabled, the software interrupts are RSTO,
RST1, ... RST7.

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