MPMC

UNIT–I Introduction: Basic Microprocessor architecture, Harvard and Von Neumann architectures with
examples, Microprocessor Unit versus Microcontroller Unit, CISC and RISC architectures.
8086 Architecture: Main features, pin diagram/description, 8086 microprocessor family, internal
architecture, bus interfacing unit, execution unit, interrupts and interrupt response, 8086 system timing,
minimum mode and maximum mode configuration.
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Concept-1: Basic Microprocessor architecture, Harvard and Von Neumann architectures with examples
Concept-2: Microprocessor Unit versus Microcontroller Unit
Concept-3: CISC and RISC architectures
Concept-4: Main features of 8086mp
Concept-5: 8086 microprocessor family
Concept-6: Internal architecture
Concept-7: Pin diagram/description
Concept-8: Physical Memory Organization
Concept-9: Interrupts and interrupt response
Concept-10: 8086 system timing
Concept-11: Minimum mode and Maximum mode configuration

***
Concept-1: Basic Microprocessor architecture, Harvard and Von Neumann architectures with
examples

Introduction: A Microprocessor is a Digital Electronic Device used to perform several operations like data
transfer operations, arithmetic and logical operations and fabricated on a single Silicon integrated Circuit (IC)
Chip. It is used to fetch, decode and execute a given instruction.

Basics of Microprocessor –
A Microprocessor takes a bunch of instructions in machine language and executes them, telling the
processor what it has to do. Microprocessor performs three basic things while executing the instruction:
 It performs some basic operations like addition, subtraction, multiplication, division, and some logical
operations using its Arithmetic and Logical Unit (ALU). New Microprocessors also perform operations
on floating-point numbers also.
 Data in microprocessors can move from one location to another.
 It has a Program Counter (PC) register that stores the address of the next instruction based on the value
of the PC, Microprocessor jumps from one location to another and takes decisions.

Fig: A typical Microprocessor structure

Microprocessor generally use two types of Architecture.
• Von Neumann Architecture
• Harvard Architecture

Harvard and Von Neumann architectures with examples

Historically there have been 2 types of Computers:

Fixed Program Computers – Their function is very specific and they couldn’t be reprogrammed, e.g.
Calculators.
Stored Program Computers – These can be programmed to carry out many different tasks, applications are
stored on them, hence the name.
 Modern computers are based on a stored-program concept introduced by John Von Neumann.
 In this stored-program concept, programs and data are stored in a separate storage unit called memories
and are treated the same.
 This novel idea meant that a computer built with this architecture would be much easier to reprogram.

The Von Neumann Architecture basic structure is like this,

It is also known as ISA (Instruction set architecture) computer and is having three basic units:

 The Central Processing Unit (CPU)

 The Main Memory Unit
 The Input/Output Device
Let’s consider them in detail.
Control Unit –
A control unit (CU) handles all processor control signals. It directs all input and output flow, fetches code for
instructions, and controls how data moves around the system.

Arithmetic and Logic Unit (ALU) –

The arithmetic logic unit is that part of the CPU that handles all the calculations the CPU may need, e.g.
Addition, Subtraction, Comparisons. It performs Logical Operations, Bit Shifting Operations, and Arithmetic
operations.
Main Memory Unit (Registers) –
 Accumulator: Stores the results of calculations made by ALU.
 Program Counter (PC): Keeps track of the memory location of the next instructions to be dealt with.
The PC then passes this next address to the Memory Address Register (MAR).
 Memory Address Register (MAR): It stores the memory locations of instructions that need to be
fetched from memory or stored in memory.
 Memory Data Register (MDR): It stores instructions fetched from memory or any data that is to be
transferred to, and stored in, memory.
 Current Instruction Register (CIR): It stores the most recently fetched instructions while it is waiting
to be coded and executed.
 Instruction Buffer Register (IBR): The instruction that is not to be executed immediately is placed
in the instruction buffer register IBR.
 Input/Output Devices – Program or data is read into main memory from the input device or secondary
storage under the control of CPU input instruction. Output devices are used to output information from
a computer. If some results are evaluated by the computer and it is stored in the computer, then with
the help of output devices, we can present them to the user.
 Registers – Registers refer to high-speed storage areas in the CPU. The data processed by the CPU are
fetched from the registers. There are different types of registers used in architecture.
MAR (Memory Address Register) – This register holds the memory location of the data that needs
to be accessed.
 MDR (Memory Data Register) – This register holds the data that is being transferred to or from
memory.
 AC (Accumulator) – This register holds the intermediate arithmetic and logic results.
 PC (Program Counter) – This register contains the address of the next instruction to be executed.
 CIR (Current Instruction Register) – This register contains the current instruction during processing.
Buses – Data is transmitted from one part of a computer to another, connecting all major internal
components to the CPU and memory, by the means of Buses. Types:
 Data Bus: It carries data among the memory unit, the I/O devices, and the processor.
 Address Bus: It carries the address of data (not the actual data) between memory and processor.
 Control Bus: It carries control commands from the CPU (and status signals from other devices) in
order to control and coordinate all the activities within the computer.

Von Neumann bottleneck –

 Whatever we do to enhance performance, we cannot get away from the fact that instructions can only
be done one at a time and can only be carried out sequentially.
 Both of these factors hold back the competence of the CPU.
 This is commonly referred to as the ‘Von Neumann bottleneck’.
 We can provide a Von Neumann processor with more cache, more RAM, or faster components but if
original gains are to be made in CPU performance then an influential inspection needs to take place of
CPU configuration.
This architecture is very important and is used in our PCs and even in Super Computers.

Harvard Architecture
In a normal computer that follows von Neumann architecture, instructions and data both are stored in the same
memory. So same buses are used to fetch instructions and data.

 This means the CPU cannot do both things together (read the instruction and read/write data). Harvard
Architecture is the computer architecture that contains separate storage and separate buses (signal path)
for instruction and data.
 It was basically developed to overcome the bottleneck of Von Neumann Architecture.
 The main advantage of having separate buses for instruction and data is that the CPU can access
instructions and read/write data at the same time.
Structure of Harvard Architecture:

 Buses
Buses are used as signal pathways. In Harvard architecture, there are separate buses for both instruction
and data. Types of Buses:
 Data Bus: It carries data among the main memory system, processor, and I/O devices.
 Data Address Bus: It carries the address of data from the processor to the main memory system.
 Instruction Bus: It carries instructions among the main memory system, processor, and I/O devices.
 Instruction Address Bus: It carries the address of instructions from the processor to the main
memory system.

 Operational Registers
There are different types of registers involved in it which are used for storing addresses of different types
of instructions.
For example, the Memory Address Register and Memory Data Register are operational registers.

 Program Counter
It has the location of the next instruction to be executed. The program counter then passes this next address
to the memory address register.
 Arithmetic and Logic Unit
The arithmetic logic unit is that part of the CPU that operates all the calculations needed. It performs
addition, subtraction, comparison, logical Operations, bit Shifting Operations, and various arithmetic
operations.

 Control Unit
The Control Unit is the part of the CPU that operates all processor control signals. It controls the input
and output devices and also controls the movement of instructions and data within the system.

 Input/Output System
Input devices are used to read data into main memory with the help of CPU input instruction. The
information from a computer as output is given through Output devices. The computer gives the results
of computation with the help of output devices.

Advantage of Harvard Architecture:

 Harvard architecture has two separate buses for instruction and data. Hence, the CPU can access
instructions and read/write data at the same time. This is the major advantage of Harvard architecture.
 In practice, Modified Harvard Architecture is used where we have two separate caches (data and
instruction). This is common and used in X86 and ARM processors.

Parameters Von Neumann Architecture Harvard Architecture

Definition The Von Neumann Architecture is Harvard Architecture is a modern type

an ancient type of computer of computer architecture that follows
architecture that follows the the concept of the relay-based model by
concept of a stored-program Harvard Mark I.
computer.

Physical It uses one single physical address It uses two separate physical addresses
Address for accessing and storing both data for storing and accessing both
and instructions. instructions and data.

Buses (Signal One common signal path (bus) It uses separate buses for the transfer of
Paths) helps in the transfer of both both data and instructions.
instruction and data.

Number of It requires two clock cycles for It executes any instruction using only
Cycles executing a single instruction. one single cycle.

Cost It is comparatively cheaper in cost It is comparatively more expensive

than Harvard Architecture. than the Von Neumann Architecture.

Access to The CPU is not able to read/write The CPU can easily read/write data as
CPU data and access instructions at the well as access the instructions at any
same time. given time.

Uses This method comes to play in the This architecture is best for signal
case of small computers and processing as well as microcontrollers.
personal computers.

Requirement As compared to Harvard This one requires more hardware. It is

of Hardware Architecture, Von Neumann because it requires separate sets of data
Architecture requires lesser as well as address buses for individual
architecture. It is because it only memory.
needs to reach one common
memory.
 Requirement This architecture basically This architecture comparatively
of Space requires less space. requires more space.

Usage of This architecture does not waste This type of architecture can result in
Space any space. It is because the space wastage. It is because the
instruction memory can utilize the instruction memory cannot utilize the
left space of the data memory. It leftover space in the data memory. It
can also happen vice-versa. also cannot happen vice-versa.

Execution The speed of execution of the Von The overall speed of execution of
Speed Neumann Architecture is Harvard Architecture is comparatively
comparatively slower. It is faster. It is because the processor, in
because it is not capable of this case, is capable of fetching both
fetching the instructions and data instructions and data at the very same
both at the same time. time.

Controlling The process of controlling The process of controlling becomes

becomes comparatively simpler comparatively complex with this
with this architecture. It is because architecture. It is because it basically
it fetches either instructions or fetches both instructions and data
data at any given time. simultaneously at the very same time.

Sample Questions From Concept-1:

1. Explain about Von Neumann architecture.
2. Explain about Harvard architecture
3. Difference between Von Neumann architecture and Harvard architecture.

Concept-2: Microprocessor Unit versus Microcontroller Unit

Integrated circuits or ICs are the electronic circuits used to construct the circuits which are smaller,
compact, quicker, and cheaper. The microprocessor and microcontroller are integrated circuits.
Microprocessor Microcontroller
Heart of the system. Heart of the embedded system.
Externally connected with input-output Input - output components are embedded.
components.
The circuit may be large depending upon usage. The circuit is very small.
Not cost-effective. Cost-effective.
The total consumption of power is high. Total consumption of power is less.
Power saving mode is not generally available. Power saving mode is generally offered.
Used in PC. Used in MP3 players, washing machines, etc.
Memories like RAM and ROM are absent. Carries RAM, ROM, etc.
Runs at a very high speed. Runs at a relatively lower speed.
It is complex and costly. Simple and cheap.
Example: DEC Alpha 21164, IBM RS6000, etc Example: Intel 8031/8051, PIC1x, etc.

Sample Questions From Concept-2: (June/July’2022)

1. Differentiate between microprocessor unit and microcontroller unit

Concept-3: CISC and RISC architectures
 RISC is an abbreviation for Reduced Instruction Set Computer, while CISC is an abbreviation for
Complex Instruction Set Computer.
 Out of these, the RISC processors have a comparatively smaller set of instructions along with few
addressing nodes.
 On the other hand, the CISC processors consist of a larger set of instructions along with multiple
addressing nodes.

RISC and CISC Architecture

Reduced Instruction Set Computer or RISC Architecture
The fundamental goal of RISC is to make hardware simpler by employing an instruction set that consists of
only a few basic steps used for evaluating, loading, and storing operations. A load command loads data but a
store command stores data.

Characteristics of RISC:
1. It has simpler instructions and thus simple instruction decoding.
2. More general-purpose registers.
3. The instruction takes one clock cycle in order to get executed.
4. The instruction comes under the size of a single word.
5. Pipeline can be easily achieved.
6. Few data types.
7. Simpler addressing modes.

Complex Instruction Set Computer or CISC Architecture

The fundamental goal of CISC is that a single instruction will handle all evaluating, loading, and storing
operations, similar to how a multiplication command will handle evaluating, loading, and storing data, which
is why it’s complicated.

Characteristics of CISC:
1. Instructions are complex, and thus it has complex instruction decoding.
2. The instructions may take more than one clock cycle in order to get executed.
3. The instruction is larger than one-word size.
4. Lesser general-purpose registers since the operations get performed only in the memory.
5. More data types.
6. Complex addressing modes.
Both CISC and RISC approaches primarily try to increase the performance of a CPU. Here is how both of
these work:
1. CISC: This kind of approach tries to minimize the total number of instructions per program, and it does so
at the cost of increasing the total number of cycles per instruction.
2. RISC: It reduces the cycles per instruction and does so at the cost of the total number of instructions per
program.

When programming was done in assembly language earlier, there was a desire to make the instructions perform
more tasks. It is because assembly programming was arduous and error-prone and led to the evolution of CISC
architecture. But as the dependency of high-level language on assembly language decreased, RISC architecture
prevailed.
Example
Suppose we need to add two different 8-bit numbers:
1. CISC approach: There would be a single instruction or command for this, such as ADD, that would
perform the task.
2. RISC approach: In this case, the programmer would write the very first load command in order to load
data in the registers. Then it would use a suitable operator and store the obtained result in the location that is
desired.
 The add operation here is divided into parts, namely, operate, load, and store. Due to this, RISC
programs are much longer, and they require more memory to get stored, even though they require fewer
transistors because the commands are less complex.
Practice Problems in RISC and CISC Architecture
1. Both the RISC and CISC architectures have primarily been developed to reduce _____________.
a. Time delay
b. Semantic gap
c. Cost
d. All of the above
Answer – (b) Semantic gap
2. Pipe-lining is the special feature of ____________.
a. IANA
b. ISA
c. CISC
d. RISC
Answer – (d) RISC
3. Which of these architectures is power efficient?
a. IANA
b. ISA
c. CISC
d. RISC
Answer – (d) RISC

Sample Questions From Concept-3:

1. Differentiate between RISC and CISC architectures.
2. Explain about RISC architecture.
3. Explain about CISC architecture

Concept-4: Main features of 8086 µp

Overview or Features of 8086
• It is a 16-bit Microprocessor(μp).It’s ALU, internal registers works with 16bit binary word.
• 8086 has a 20 bit address bus can access up to 220= 1 MB memory locations.
• 8086 has a 16bit data bus. It can read or write data to a memory/port either 16bits or 8 bit at a time.
• It can support up to 64K I/O ports.
• It provides 14, 16 -bit registers.
• Frequency range of 8086 is 6-10 MHz
• It has multiplexed address and data bus AD0- AD15 and A16 – A19.
• It requires single phase clock with 33% duty cycle to provide internal timing.
• It can prefetch upto 6 instruction bytes from memory and queues them in order to speed up instruction
execution.
• It requires +5V power supply.
• A 40 pin dual in line package.
• 8086 is designed to operate in two modes, Minimum mode and Maximum mode.
o The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a single
microprocessor configuration.
o The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This is a multi micro
processors configuration.
Sample Questions From Concept-4:
1. Explain the features of 8086 microprocessor
Concept-5: 8086 microprocessor family
Transistor was invented in 1948 (23 December 1947 in Bell lab). IC was invented in 1958 (Fair Child
Semiconductors) By Texas Instruments J Kilby. The first microprocessor was invented by INTEL(INTegrated
ELectronics).
The first microprocessor introduced in 1971 was a 4-bit microprocessor with 4m5KB memory and had a set
of 45 instructions.
Size of the microprocessor – 4 bit
Name Year of Invention Clock Number of Inst. per
speed transistors sec
INTEL 1971 by Ted Hoff and Stanley 740 kHz 2300 60,000
4004/4040 Mazor

Size of the microprocessor – 8 bit

Name Year of Invention Clock Number of Inst. per sec

speed transistors
8008 1972 500 kHz 3500 50,000
8080 1974 2 MHz 6000 10 times faster than
8008
8085 1976 (16-bit address 3 MHz 6500 769230
bus)

Size of the microprocessor – 16 bit

Name Year of Invention Clock Number of Inst.

speed transistors per sec
8086 1978 (multiply and divide instruction, 16-bit 4.77 MHz, 29000 2.5
data bus and 20-bit address bus) 8 MHz, 10 Million
MHz
8088 1979 (cheaper version of 8086 and 8-bit 2.5
external bus) Million

80186/80188 1982 (80188 cheaper version of 80186, and 6 MHz

additional components like interrupt
controller, clock generator, local bus
controller, counters)
80286 1982 (data bus 16bit and address bus 24 bit) 8 MHz 134000 4
Million
Size of the microprocessor – 32 bit

Name Year of Invention Clock Number of Inst. per sec

speed transistors
INTEL 1986 (other versions 80386DX, 16 MHz – 275000
80386 80386SX, 80386SL , and data bus 33 MHz
32-bit address bus 32 bit)
INTEL 1986 (other versions 80486DX, 16 MHz – 1.2 Million 8 KB of cache
80486 80486SX, 80486DX2, 100 MHz transistors memory
80486DX4)
PENTIUM 1993 66 MHz Cache memory 8 bit
for instructions 8 bit
for data

Size of the microprocessor – 64 bit

Name Year of Invention Clock speed Number of Inst. per sec

transistors
INTEL 2006 (other versions 1.2 GHz to 3 GHz 291 Million 64 KB of L1
core 2 core2 duo, core2 quad, transistors cache per core 4
core2 extreme) MB of L2 cache
i3, i5, i7 2007, 2009, 2010 2.2GHz – 3.3GHz,
2.4GHz – 3.6GHz,
2.93GHz – 3.33GHz

Generations of microprocessors:
First-generation –
From 1971 to 1972 the era of the first generation came which brought microprocessors like INTEL 4004
Rockwell international PPS-4 INTEL 8008 etc.

Second generation –
The second generation marked the development of 8-bit microprocessors from 1973 to 1978. Processors like
INTEL 8085 Motorola 6800 and 6801 etc came into existence.

Third generation –
The third generation brought forward the 16-bit processors like INTEL 8086/80186/80286 Motorola 68000
68010 etc. From 1979 to 1980 this generation used the HMOS technology.

Fourth generation –
The fourth-generation came into existence from 1981 to 1995. The 32-bit processors using HMOS fabrication
came into existence. INTEL 80386 and Motorola 68020 are some of the popular processors of this generation.

Fifth-generation –
From 1995 till now we are in the fifth generation. 64-bit processors like PENTIUM, Celeron, dual, quad, and
octa-core processors came into existence.
Types of microprocessors :

Complex instruction set microprocessor –

The processors are designed to minimize the number of instructions per program and ignore the number of
cycles per instruction. The compiler is used to translate a high-level language to assembly-level language
because the length of code is relatively short and an extra RAM is used to store the instructions. These
processors can do tasks like downloading, uploading, and recalling data from memory. Apart from these tasks,
this microprocessor can perform complex mathematical calculations in a single command.
Example: IBM 370/168, VAX 11/780

Reduced instruction set microprocessor –

These processors are made according to function. They are designed to reduce the execution time by using the
simplified instruction set. They can carry out small things in specific commands. These processors complete
commands at a faster rate. They require only one clock cycle to implement a result at uniform execution time.
There is a number of registers and less number of transistors. To access the memory location LOAD and
STORE instructions are used.
Example: Power PC 601, 604, 615, 620

Superscalar microprocessor –
These processors can perform many tasks at a time. They can be used for ALUs and multiplier-like arrays.
They have multiple operation units and perform tasks by executing multiple commands.

Application-specific integrated circuit –

These processors are application-specific like personal digital assistant computers. They are designed
according to proper specifications.

Digital signal multiprocessor –

These processors are used to convert signals like analog to digital or digital to analog. The chips of these
processors are used in many devices such as RADAR SONAR home theatres etc.

Advantages of the microprocessor –

 High processing speed

 Compact size
 Easy maintenance
 Can perform complex mathematics
 Flexible
 Can be improved according to a requirement

Disadvantages of microprocessors –

 Overheating occurs due to overuse

 Performance depends on the size of the data
 Large board size than microcontrollers
 Most microprocessors do not support floating-point operations

Sample Questions From Concept-5: (June/July’2022)

1. Explain the concept of evaluation of microprocessor
2. What are the advantages and disadvantages of microprocessor?
3.Define a microprocessor. Explain in detail the evolution of microprocessor in microprocessor age from
4004 MP to core-2 system.
4. What is microprocessor? Explain the brief history of evolution of microprocessor.
Intel 8086
o Intel 8086 microprocessor is the enhanced version of Intel 8085 microprocessor. It was designed by
Intel in 1976.
o The 8086 microprocessor is a16-bit, N-channel, HMOS microprocessor. Where the HMOS is used for
"High-speed Metal Oxide Semiconductor".
o Intel 8086 is built on a single semiconductor chip and packaged in a 40-pin IC package. The type of
package is DIP (Dual Inline Package).
o Intel 8086 uses 20 address lines and 16 data- lines. It can directly address up to 220 = 1 Mbyte of
memory.
o It consists of a powerful instruction set, which provides operation like division and multiplication very
quickly.
o 8086 is designed to operate in two modes, i.e., Minimum and Maximum mode.

Sample Questions From Concept-5:

1. Explain 8086 family

Concept-6: Internal architecture

Architecture of 8086.

8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit) and BIU (Bus Interface
Unit). It has the following functional parts –

EU (Execution Unit)
Execution unit gives instructions to BIU stating from where to fetch the data and then decode and execute
those instructions. Its function is to control operations on data using the instruction decoder & ALU. EU has
no direct connection with system buses as shown in the above figure, it performs operations over data through
BIU.

ALU
It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.
Flag Register
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result stored in the
accumulator. It has 9 flags and they are divided into 2 groups − Conditional Flags and Control Flags.

Conditional Flags:
It represents the result of the last arithmetic or logical instruction executed. Following is the list of conditional
flags −
• Carry flag − This flag indicates an overflow condition for arithmetic operations.
• Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow from lower
nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry given by D3 bit to
D4 is AF flag. The processor uses this flag to perform binary to BCD conversion.
• Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order 8-bits of
the result contains even number of 1’s, then the Parity Flag is set. For odd number of 1’s, the Parity
Flag is reset.
• Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set
to 0.
• Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is negative, then
the sign flag is set to 1 else set to 0.
• Overflow flag − This flag represents the result when the system capacity is exceeded.
Control Flags:
Control flags controls the operations of the execution unit. Following is the list of control flags −
• Trap flag − It is used for single step control and allows the user to execute one instruction at a time
for debugging. If it is set, then the program can be run in a single step mode.
• Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the interruption of a
program. It is set to 1 for interrupt enabled condition and set to 0 for interrupt disabled condition.
• Direction flag − It is used in string operation. As the name suggests when it is set then string bytes are
accessed from the higher memory address to the lower memory address and vice-a-versa.
Register Organization of 8086 :
General purpose register:
There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers can be
used individually to store 8-bit data and can be used in pairs to store 16bit data. The valid register pairs are
AH and AL, BH and BL, CH and CL, and DH and DL. It is referred to the AX, BX, CX, and DX respectively.
• AX register − It is also known as accumulator register. It is used to store operands for arithmetic
operations.
• BX register − It is used as a base register. It is used to store the starting base address of the memory
area within the data segment.
• CX register − It is referred to as counter. It is used in loop instruction to store the loop counter.
• DX register − This register is used to hold I/O port address for I/O instruction.

Stack pointer register:

It is a 16-bit register, which holds the address from the start of the segment to the memory location, where a
word was most recently stored on the stack.
BIU (Bus Interface Unit)
BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses, fetching
instructions from the memory, reading data from the ports and the memory as well as writing data to the ports
and the memory.
EU (Execution Unit)
EU has no direction connection with System Buses so this is possible with the BIU. EU and BIU are connected
with the Internal Bus.
It has the following functional parts −
• Instruction queue − BIU contains the instruction queue. BIU gets upto 6 bytes of next instructions and
stores them in the instruction queue. When EU executes instructions and is ready for its next instruction,
then it simply reads the instruction from this instruction queue resulting in increased execution speed.
• Fetching the next instruction while the current instruction executes is called pipelining.
• Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of instructions
and data in memory, which are used by the processor to access memory locations. It also contains 1 pointer
register IP, which holds the address of the next instruction to executed by the EU.
•
o CS − It stands for Code Segment. It is used for addressing a memory location in the code segment of
the memory, where the executable program is stored.
o DS − It stands for Data Segment. It consists of data used by the program andis accessed in the data
segment by an offset address or the content of other register that holds the offset address.
o SS − It stands for Stack Segment. It handles memory to store data and addresses during execution.
o ES − It stands for Extra Segment. ES is additional data segment, which is used by the string to hold
the extra destination data.
• Instruction pointer − It is a 16-bit register used to hold the address of the next instruction to be executed.

Sample Questions From Concept-6: (June/July’2022)

1. Draw and explain the architecture of 8086 microprocessor.
2. Explain the functional blocks of 8086 microprocessor.
3. Explain the register organization of 8086 microprocessor.
4. Draw and explain about flag register of 8086 microprocessor.
5.What are the functions of Bus Interface Unit (BIL) and Execution Unit (EU) in 8086?

Concept-7: Pin diagram/description

Pin diagram of 8086.
The 8086 microprocessor is a 40 pin Dual in Package Integrated Circuit Chip. The signals of 8086 mp is
classified into 3 groups
1. Common Mode signals
2. Minimum Mode signals
3. Maximum Mode signals
1. Common Mode signals
 Power supply and frequency signals
It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.
 Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for operations. Its
frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
 Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and AD8AD15
carries higher order byte data. During the first clock cycle, it carries 16-bit address and after that it
carries 16-bit data.
 Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries 4-bit
address and later it carries status signals.
 S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of data using
data bus D8-D15. This signal is low during the first clock cycle, thereafter it is active.
 Read($\overline{RD}$)
It is available at pin 32 and is used to read signal for Read operation.
 Ready
It is available at pin 22. It is an acknowledgement signal from I/O devices that data is transferred. It is
an active high signal. When it is high, it indicates that the device is ready to transfer data. When it is
low, it indicates wait state.
 RESET
It is available at pin 21 and is used to restart the execution. It causes the processor to immediately
terminate its present activity. This signal is active high for the first 4 clock cycles to RESET the
microprocessor.
 INTR
It is available at pin 18. It is an interrupt request signal, which is sampled during the last clock cycle
of each instruction to determine if the processor considered this as an interrupt or not.
 NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input, which
causes an interrupt request to the microprocessor.
$\overline{TEST}$
This signal is like wait state and is available at pin 23. When this signal is high, then the processor has
to wait for IDLE state, else the execution continues.
 MN/$\overline{MX}$
It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the processor is to
operate in; when it is high, it works in the minimum mode and vice-averse

2.Minimum Mode signals

 INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the microprocessor receives
this signal, it acknowledges the interrupt.
 ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated each time the
processor begins any operation. This signal indicates the availability of a valid address on the
address/data lines.
 DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286. The
transreceiver is a device used to separate data from the address/data bus.
  DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction of data
flow through the transreceiver. When it is high, data is transmitted out and vice-a-versa.
 M/IO
This signal is used to distinguish between memory and I/O operations. When it is high, it indicates I/O
operation and when it is low indicates the memory operation. It is available at pin 28.
 WR
It stands for write signal and is available at pin 29. It is used to write the data into the memory or the
output device depending on the status of M/IO signal.
 HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal acknowledges the
HOLD signal.
 HOLD
This signal indicates to the processor that external devices are requesting to access the address/data
buses. It is available at pin 31.

3.Maximum Mode signals

 QS1 and QS0
These are queue status signals and are available at pin 24 and 25. These signals provide the status of
instruction queue. Their conditions are shown in the following table −

 S0, S1, S2
These are the status signals that provide the status of operation, which is used by the Bus Controller
8288 to generate memory & I/O control signals. These are available at pin 26, 27, and 28. Following
is the table showing their status −

 LOCK
When this signal is active, it indicates to the other processors not to ask the CPU to leave the system
bus. It is activated using the LOCK prefix on any instruction and is available at pin 29.
  RQ/GT1 and RQ/GT0
These are the Request/Grant signals used by the other processors requesting the CPU to release the
system bus. When the signal is received by CPU, then it sends acknowledgment. RQ/GT0 has a higher
priority than RQ/GT1.

Sample Questions From Concept-7: (Feb’2022)

1. Explain the functionality of pins used in the following modes of 8086 microprocessor: i) Minimum mode
ii) Maximum mode.
2. Explain signal description of 8086 microprocessor
3. Explain pin diagram of 8086 microprocessor

Concept-8: Memory Segmentation or Memory Organization

➢ The memory in an 8086 based system is organized as segmented memory.
➢ The CPU 8086 is able to access 1MB of physical memory. The complete 1MB of memory can be
divided into 16 segments, each of 64KB size and is addressed by one of the segment register.
➢ The 16-bit contents of the segment register actually point to the starting location of a particular
segment. The address of the segments may be assigned as 0000H to F000h respectively.
➢ To address a specific memory location within a segment, we need an offset address. The offset address
values are from 0000H to FFFFH so that the physical addresses range from 00000H to FFFFFH.

physical address is calculated as below:

Ex: Segment address-------→ 1005H

Offset address ----------→ 5555H
Segment address -------→ 1005H-------0001 0000 0000 0101
Shifted left by 4 Positions ------0001 0000 0000 0101 0000
+
Offset address --- 5555H ------ 0101 0101 0101 0101

Physical address -------155A5H 0001 0101 0101 1010

0101
The main advantages of the segmented memory scheme are as follows:
1. Allows the memory capacity to be 1MB although the actual addresses to be handled are of 16-bitsize.
2. Allows the placing of code, data and stack portions of the same program in different parts (segments)
of memory, for data and code protection.
 3. Permits a program and/or its data to be put into different areas of memory each time the program is
executed, i.e., provision for relocation is done.
Overlapping and Non-overlapping Memory segments:
➢ In the overlapping area locations physical address = CS1+IP1 = CS2+IP2. Where ‘+’ indicates the
procedure of physical address formation.

Physical Memory Organization Block Diagram:

There are 20 address lines in the 8086 microprocessor. This gives us 220 different memory locations
Hence the total size is 220 Bytes (is each memory location is Byte Addressable, one byte of data can he stored
at every single location), which is equal to IMB
Even the memory is byte-addressable yet the 8086 microprocessor an easily handle up to 16 bits of
data at a time through its 16 data lines. So, to organize the memory efficiently, the entire memory in 8086 is
divided into two memory banks: odd bank and the even bank

The way in which data is read or written is decided by the value of BHE, and the last address but that is the
AO line. It is done in the following way

BHE' A0 Operation performed on memory

0 0 16 bits of data will be read or written into the memory

0 1 8 bits of data will be read/written into the odd memory bank

1 0 8 bits of data will be read/written into the even memory bank

1 1 No operation is performed

 To read or write 8 bits of data, it would require only 1 CPU cycle, no matter the data is stored in any
of the memory banks, but to read or write 16 bits of data, the BIL of the 8086 may require either I or 2
memory cycles depending upon whether the lower byte of word is located at even or odd memory
address
 If the lower byte of the word is stored at even memory bank and the upper byte is stored at odd memory
bank then the CPU will require only I memory cycle. So, it is better to store data in this way
 If the lower byte of the word is located at an odd memory address, then the CPU will require 2 memory
cycles.
 The first memory cycle is required for accessing the lower byte of the word through the higher data
bus, ie D15 to DS, and the second memory cycle is required for accessing the upper byte of the word
through the lower data bus, ie D7 to DO

Sample Questions From Concept-8:

1 Explain the physical memory organization of 8086 microprocessor.
2 What is the use of memory segmentation in 8086 microprocessor?
Concept-9: Interrupts and interrupt response
Interrupt is the method of creating a temporary halt during program execution and allows peripheral
devices to access the microprocessor. The microprocessor responds to that interrupt with an ISR (Interrupt
Service Routine), which is a short program to instruct the microprocessor on how to handle the interrupt.
The following image shows the types of interrupts we have in a 8086 microprocessor −

Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin to
the microprocessor. The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable
interrupt and INTR is a maskable interrupt having lower priority. One more interrupt pin associated is INTA
called interrupt acknowledge.

NMI
It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt
request pin (INTR)and it is of type 2 interrupt.
When this interrupt is activated, these actions take place −
• Completes the current instruction that is in progress.
• Pushes the Flag register values on to the stack.
• Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the
stack.
• IP is loaded from the contents of the word location 00008H.
• CS is loaded from the contents of the next word location 0000AH.
• Interrupt flag and trap flag are reset to 0.
INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are
enabled using set interrupt flag instruction. It should not be enabled using clear interrupt Flag instruction. The
INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then the
microprocessor first completes the current execution and sends ‘0’ on INTA pin twice. The first ‘0’ means
INTA informs the external device to get ready and during the second ‘0’ the microprocessor receives the 8 bit,
say X, from the programmable interrupt controller.
These actions are taken by the microprocessor −
• First completes the current instruction.
• Activates INTA output and receives the interrupt type, say X.
• Flag register value, CS value of the return address and IP value of the return address are pushed on to
the stack.
• IP value is loaded from the contents of word location X × 4
• CS is loaded from the contents of the next word location.
• Interrupt flag and trap flag is reset to 0
Software Interrupts
Some instructions are inserted at the desired position into the program to create interrupts. These
interrupt instructions can be used to test the working of various interrupt handlers. It includes −
INT- Interrupt instruction with type number
It is 2-byte instruction. First byte provides the op-code and the second byte provides the interrupt type number.
There are 256 interrupt types under this group.
Its execution includes the following steps −
• Flag register value is pushed on to the stack.
• CS value of the return address and IP value of the return address are pushed on to the stack.
• IP is loaded from the contents of the word location ‘type number’ × 4
• CS is loaded from the contents of the next word location.
• Interrupt Flag and Trap Flag are reset to 0
The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly for type2
is 00008H and ……so on. The first five pointers are dedicated interrupt pointers. i.e. −
TYPE 0 interrupt represents division by zero situation.
TYPE 1 interrupt represents single-step execution during the debugging of a program.
TYPE 2 interrupt represents non-maskable NMI interrupt.
TYPE 3 interrupt represents break-point interrupt.
TYPE 4 interrupt represents overflow interrupt.

The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and interrupts from
32 to Type 255 are available for hardware and software interrupts.
INT 3-Break Point Interrupt Instruction. It is a 1-byte instruction having op-code is CCH. These instructions
are inserted into the program so that when the processor reaches there, then it stops the normal execution of
program and follows the break-point procedure.
Its execution includes the following steps −
• Flag register value is pushed on to the stack.
• CS value of the return address and IP value of the return address are pushed on to the stack.
• IP is loaded from the contents of the word location 3×4 = 0000CH
• CS is loaded from the contents of the next word location.
• Interrupt Flag and Trap Flag are reset to 0

INTO - Interrupt on overflow instruction

It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH. As the name
suggests it is a conditional interrupt instruction, i.e. it is active only when the overflow flag is set to 1 and
branches to the interrupt handler whose interrupt type number is 4. If the overflow flag is reset then, the
execution continues to the next instruction.
Its execution includes the following steps −
• Flag register values are pushed on to the stack.
• CS value of the return address and IP value of the return address are pushed on to the stack.
• IP is loaded from the contents of word location 4×4 = 00010H
• CS is loaded from the contents of the next word location.
• Interrupt flag and Trap flag are reset to 0
For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler. When an
interrupt is invoked, the microprocessor runs the interrupt service routine. For every interrupt, there is a fixed
location in memory that holds the address of its ISR. The group of memory locations set aside to hold the
addresses of ISRs is called the interrupt vector table.
When an interrupt is occurred, the microprocessor stops execution of current instruction. It transfers the
content of program counter into stack. It also stores the current status of the interrupts internally but not on
stack. After this, it jumps to the memory location specified by Interrupt Vector Table (IVT). After that the
code written on that memory area will execute.
Interrupt Vector Table

The first 1Kbyte of memory of 8086 (00000 to003FF) is set aside as a table for storing the starting
addresses of Interrupt Service Procedures(ISP).Since 4-bytes are required for storing starting addresses of
ISPs, the table can hold 256 Interrupt procedures.
The starting address of an ISP is often called the Interrupt Vector or Interrupt Pointer. Therefore the
table is referred as Interrupt Vector Table. In this table, IP value is put in as low word of the vector & CS is
put in high vector.

Sample Questions From Concept-9: (Feb’2022)

1. Explain the Interrupt vector table of 8086 microprocessor
2. What is an Interrupt in microprocessor and explain about the types of interrupts.
3. Discuss the interrupts and interrupt response of 8086
Concept-10: 8086 system timing
The bus cycle is also named as machine cycle. Bus cycle of 8086 is used to access memory, peripheral devices
(Input/Output devices), and Interrupt controller. Bus cycle corresponds to a sequence of events that starts with
an address being output on system address bus followed by a write or read data transfer. During these
operations, a series of control signals are also produced by microprocessor to control direction and timing of
bus.

There are at least four clock periods in a bus cycle of 8086 microprocessor. These four clock periods are called
T1, T2, T3 and T4 states.

These four clock states gives bus cycle duration T of 200 ns *4 = 800 ns in 5-MHz 8086 system.

Read Cycle :
When a read cycle is to be performed, during T1 microprocessor puts an address on address bus, and then bus
is put in high impedance state during T2 state. Data to be read must be out on bus during T3 and T4. During
T3 bus is made “reserved for data in” and finally data is read during T4.

Write Cycle :
In case of write memory cycle, during T1 state microprocessor puts an address on address bus. Data is put on
data bus by CPU during T2 state and maintained during T3 and T4 states, that is written out to memory or I/O
devices.

Sample Questions From Concept-10: (June/July’2022)

1. Evaluate system bus timing with neat block diagram
2 Explain about read cycle of 8086 microprocessor?
3. Explain about write cycle of 8086 microprocessor?
Concept-11: minimum mode and maximum mode configuration
Operating 8086 in minimum mode

 The microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1.
 In this mode, all the control signals are given out by the microprocessor chip itself.
 There is a single microprocessor in the minimum mode system.
 The remaining components in the system are latches, transceivers, clock generator, memory and I/O
devices.
 Latches are generally buffered output D-type flip-flops like 8282. They are used for separating the
valid address from the multiplexed address/data signals and are controlled by the ALE signal generated
by 8086.
 Transceivers are the bidirectional buffers and some times they are called as data amplifiers. They are
required to separate the valid data from the time multiplexed address/data signals. They are controlled
by two signals namely, DEN and DT/R.
 The DEN signal indicates the direction of data, i.e. from or to the processor.
 The system contains memory for the monitor and users program storage. Usually, EPROM are used
for monitor storage, while RAM for users program storage. A system may contain I/O devices.
 The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two
parts, the first is the timing diagram for read cycle and the second is the timing diagram for write cycle.
Read & Write Cycles:
 The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO
signal. During the negative going edge of this signal, the valid address is latched on the local bus.
 The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal indicates a
memory or I/O operation.
 At T2, the address is removed from the local bus and is sent to the output. The bus is then tristated.
The read (RD) control signal is also activated in T2.
 The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the
valid data is available on the data bus.
 The addressed device will drive the READY line high. When the processor returns the read signal to
high level, the addressed device will again tristate its bus drivers. A write cycle also begins with the
assertion of ALE and the emission of the address.
 The M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the
address in T1, the processor sends the data to be written to the addressed location.
 The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of T2
(unlike RD is somewhat delayed in T2 to provide time for floating).
 The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read
or write.

Read Cycle Timing Diagram for minimum mode

Write Cycle Timing Diagram for minimum mode

Operating 8086 in Maxiimum mode

 In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
 In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller
derives the control signal using this status information.
 In the maximum mode, there may be more than one microprocessor in the system configuration. The
components in the system are same as in the minimum mode system.
 The basic function of the bus controller chip IC8288, is to derive control signals like RD and WR ( for
memory and I/O devices), DEN, DT/R, ALE etc. using the information by the processor on the status
lines.
 The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven by CPU.
 It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and AIOWC. The
AEN, IOB and CEN pins are specially useful for multiprocessor systems.
 AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the
MCE/PDEN output depends upon the status of the IOB pin.
 INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting
device.
 IORC, IOWC are I/O read command and I/O write command signals respectively . These signals enable
an IO interface to read or write the data from or to the address port.
 The MRDC, MWTC are memory read command and memory write command signals respectively and
may be used as memory read or write signals.
 All these command signals instructs the memory to accept or send data from or to the bus.
 Here the only difference between in timing diagram between minimum mode and maximum mode is
the status signals used and the available control and advanced command signals.
Read & Write Cycles:
 S0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on the ALE
and apply a required signal to its DT / R pin during T1.
 In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC or
IORC. These signals are activated until T4.
 For an output, the AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is activated
from T3 to T4.
 The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.
 If reader input is not activated before T3, wait state will be inserted between T3 and T4.
 Fig: Maximum mode Read Cycle

Fig: Maximum mode Write Cycle

Sample Questions From Concept-11

1. Explain about the minimum mode configuration of 8086 microprocessor
2. Explain about minimum mode configuration read cycle of 8086 microprocessor?
3. Explain about minimum mode configuration write cycle of 8086 microprocessor?
4. Explain about the maximum mode configuration of 8086 microprocessor
5. Explain about maximum mode configuration read cycle of 8086 microprocessor?
6. Explain about maximum mode configuration write cycle of 8086 microprocessor?
1. What is a register? Mention the registers in 8086 and explain each.
Register organization of 8086
General 16-bit registers
The registers AX, BX, CX, and DX are the general 16-bit registers.
AX Register: Accumulator register consists of two 8-bit registers AL and AH, which
can be combined together and used as a 16- bit register AX. AL in this case contains the low-order byte of the
word, and AH contains the high-order byte. Accumulator can be used for I/O operations, rotate and string
manipulation.
BX Register: This register is mainly used as a base register. It holds the starting base location of a memory
region within a data segment. It is used as offset storage for forming physical address in case of certain
addressing mode.
CX Register: It is used as default counter or count register in case of string and loop
instructions.
DX Register: Data register can be used as a port number in I/O operations and implicit operand or destination
in case of few instructions. In integer 32-bit multiply and divide instruction the DX register contains high-
order word of the initial or resulting number.
Segment registers:
To complete 1Mbyte memory is divided into 16 logical segments. Each segment contains 64Kbyte of memory.
There are four segment registers.
Code segment (CS) is a 16-bit register containing address of 64 KB segment with
processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction
pointer (IP) register. CS register cannot be changed directly.
The CS register is automatically updated during far jump, far call and far return
instructions. It is used for addressing a memory location in the code segment of the
memory, where the executable program is stored.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with
program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base
pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP
instruction. It is used for addressing stack segment of memory. The stack segment is that segment of memory,
which is used to store stack data.
Data segment (DS) is a 16-bit register containing address of 64KB segment with
program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX,
DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP
and LDS instructions. It points to the data segment memory where the data is resided.
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By
default, the processor assumes that the DI register references the ES segment in string manipulation
instructions. ES register can be changed directly using POP and LES instructions. It also refers to segment
which essentially is another data segment of the memory. It also contains data.
Pointers and index registers.
The pointers contain within the particular segments. The pointers IP, BP, SP
usually contain offsets within the code, data and stack segments respectively
Stack Pointer (SP) is a 16-bit register pointing to program stack in stack segment.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based,
based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as
well as a source data addresses in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect
addressing, as well as a destination data address in string manipulation instructions.
Conditional Flags
Conditional flags are as follows:
Carry Flag (CY): This flag indicates an overflow condition for unsigned integer
arithmetic. It is also used in multiple-precision arithmetic.
Auxiliary Flag (AC): If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 –
D3) to upper nibble (i.e. D4 – D7), the AC flag is set i.e. carry given by D3 bit to D4 is AC flag. This is not a
general-purpose flag, it is used internally by the Processor to perform Binary to BCD conversion.
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the result contains
even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity flag is reset.
Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset.
Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation
is negative, sign flag is set.
Control Flags:
Control flags are set or reset deliberately to control the operations of the execution unit.
Control flags are as follows:
Trap Flag (TF): It is used for single step control. It allows user to execute one
instruction of a program at a time for debugging. When trap flag is set, program can be run in single step mode.
Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the maskable
interrupt of 8086 is enabled and if it is reset, the interrupt is disabled. It can be set by executing instruction sit
and can be cleared by executing CLI instruction.
Direction Flag (DF): It is used in string operation. If it is set, string bytes are accessed from higher memory
address to lower memory address. When it is reset, the string bytes are accessed from lower memory address
to higher memory address.

2. Draw the minimum mode pin diagram and explain the function of each pin in detail.

Power supply and frequency signals

It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.
Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for operations. Its frequency is
different for different versions, i.e. 5MHz, 8MHz and 10MHz.
Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and AD8AD15 carries
higher order byte data. During the first clock cycle, it carries 16-bit address and after that it carries 16-bit data.
Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries 4-bit address and
later it carries status signals.
S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of data using data
bus D8-D15. This signal is low during the first clock cycle, thereafter it is active.
Read($\overline{RD}$)
It is available at pin 32 and is used to read signal for Read operation.
Ready
It is available at pin 22. It is an acknowledgement signal from I/O devices that data is transferred. It is an active
high signal. When it is high, it indicates that the device is ready to transfer data. When it is low, it indicates
wait state.
RESET
It is available at pin 21 and is used to restart the execution. It causes the processor to immediately terminate
its present activity. This signal is active high for the first 4 clock cycles to RESET the microprocessor.
INTR
It is available at pin 18. It is an interrupt request signal, which is sampled during the last clock cycle of each
instruction to determine if the processor considered this as an interrupt or not.
NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input, which causes an
interrupt request to the microprocessor.
$\overline{TEST}$
This signal is like wait state and is available at pin 23. When this signal is high, then the processor has to wait
for IDLE state, else the execution continues.
MN/$\overline{MX}$
It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the processor is to operate
in; when it is high, it works in the minimum mode and vice-aversa.
INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the microprocessor receives this
signal, it acknowledges the interrupt.
ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated each time the
processor begins any operation. This signal indicates the availability of a valid address on the address/data
lines.
DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286. The transreceiver
is a device used to separate data from the address/data bus.
DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction of data flow
through the transreceiver. When it is high, data is transmitted out and vice-a-versa.
M/IO
This signal is used to distinguish between memory and I/O operations. When it is high, it indicates I/O
operation and when it is low indicates the memory operation. It is available at pin 28.
WR
It stands for write signal and is available at pin 29. It is used to write the data into the memory or the output
device depending on the status of M/IO signal.
HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal acknowledges the HOLD
signal.
HOLD
This signal indicates to the processor that external devices are requesting to access the address/data buses. It
is available at pin 31.

3. Explain the functions of ALE, READY, HOLD, and BHE pins of 8086 microprocessor.

ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated each time the
processor begins any operation. This signal indicates the availability of a valid address on the address/data
lines.
Ready
It is available at pin 22. It is an acknowledgement signal from I/O devices that data is transferred. It is an active
high signal. When it is high, it indicates that the device is ready to transfer data. When it is low, it indicates
wait state.
HOLD
This signal indicates to the processor that external devices are requesting to access the address/data buses. It
is available at pin 31.
BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of data using data
bus D8-D15. This signal is low during the first clock cycle, thereafter it is active.

4. What is a microprocessor? State its importance.

A microprocessor is a Digital electronic device used to perform several operations like data transfer
operations, arithmetic and logical operations developed on a single chip. It is used for fetching, decoding and
execution of given instruction.
Importance:
A device that uses a microprocessor is normally capable of many functions, such as word processing,
calculation, and communication via Internet or telephone. However, for the device to work properly, the
microprocessor itself has to communicate with other parts of the device. For example, a microprocessor would
need to communicate with the video display to control the output data that a program may produce. Therefore,
a microprocessor would act as device's "brain" in that it transmits, receives and interprets the data needed to
operate a device.

5. Draw the flag register of 8086 microprocessor and explain the function of each flag.

Conditional Flags
Conditional flags are as follows:
Carry Flag (CY): This flag indicates an overflow condition for unsigned integer
arithmetic. It is also used in multiple-precision arithmetic.
Auxiliary Flag (AC): If an operation performed in ALU generates a carry/barrow from lower nibble (i.e. D0 –
D3) to upper nibble (i.e. D4 – D7), the AC flag is set i.e. carry given by D3 bit to D4 is AC flag. This is not a
general-purpose flag, it is used internally by the Processor to perform Binary to BCD conversion.
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the result contains
even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity flag is reset.
Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset.
Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation
is negative, sign flag is set.
Control Flags:
Control flags are set or reset deliberately to control the operations of the execution unit.
Control flags are as follows:
Trap Flag (TF): It is used for single step control. It allows user to execute one
instruction of a program at a time for debugging. When trap flag is set, program can be run in single step mode.
Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the maskable
interrupt of 8086 is enabled and if it is reset, the interrupt is disabled. It can be set by executing instruction sit
and can be cleared by executing CLI instruction.
Direction Flag (DF): It is used in string operation. If it is set, string bytes are accessed from higher memory
address to lower memory address. When it is reset, the string bytes are accessed from lower memory address
to higher memory address.
 6. Differentiate between minimum and maximum mode operations of 8086 microprocessor.

Minimum mode Maximum mode

In minimum mode there can be only one processor In maximum mode there can be multiple processors
i.e. 8086. with 8086, like 8087 and 8089.

MN/MX is 1 to indicate minimum mode. MN/MX is 0 to indicate maximum mode.

ALE for the latch is given by 8086 as it is the only ALE for the latch is given by 8288 bus controller as
processor in the circuit. there can be multiple processors in the circuit.

DEN and DT/R for the trans-receivers are given by DEN and DT/R for the trans-receivers are given by
8086 itself. 8288 bus controller.

Direct control signals M/IO, RD and WR are given Instead of control signals, each processor generates
by 8086. status signals called S2, S1 &S0.

Control signals M/IO, RD and WR are decoded by Status signals S2, S1 &S0 are decoded by a bus
a 3:8 decoder like 74138. controller like 8288 to produce control signals.

INTA is given by 8086 in response to an interrupt INTA is given by 8288 bus controller in response to an
on INTR line. interrupt on INTR line.

HOLD and HLDA signals are used for bus request RQ /GT lines are used for bus requests by other
with a DMA controller like 8237. processors like 8087 or 8089.

The circuit is simpler. The circuit is more complex.

Multiprocessing cannot be performed hence As multiprocessing can be performed, it can give very
performance is lower. high performance.

7. What is the use of memory segmentation in 8086 microprocessor?

Segmentation is the process in which the main memory of the computer is divided into different segments
and each segment has its own base address. It is basically used to enhance the speed of execution of the
computer system, so that processor is able to fetch and execute the data from the memory easily and fast.
Need for Segmentation –
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below) called as
Segment Registers.
• Code segment register (CS): is used for addressing memory location in the code segment of the memory,
where the executable program is stored.
• Data segment register (DS): points to the data segment of the memory where the data is stored.
• Extra Segment Register (ES): also refers to a segment in the memory which is another data segment in the
memory.
• Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack segment is that
segment of memory which is used to store stack data.

The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to access one of the 1MB
memory locations. The four segment registers actually contain the upper 16 bits of the starting addresses of
the four memory segments of 64 KB each with which the 8086 is working at that instant of time. A segment
is a logical unit of memory that may be up to 64 kilobytes long. Each segment is made up of contiguous
memory locations. It is independent, separately addressable unit. Starting address will always be changing. It
will not be fixed. Note that the 8086 does not work the whole 1MB memory at any given time. However it
works only with four 64KB segments within the whole 1MB memory.
Bellow is the one way of positioning four 64 kilobyte segments within the 1M byte memory space of an 8086.
Types of Segmentation –
1. Overlapping Segment – A segment starts at a particular address and its maximum size can go up to
64kilobytes. But if another segment starts along this 64kilobytes location of the first segment, then
the two are said to be Overlapping Segment.
2. Non-Overlapped Segment – A segment starts at a particular address and its maximum size can go
up to 64kilobytes. But if another segment starts before this 64kilobytes location of the first segment,
then the two segments are said to be Non-Overlapped Segment.
Advantages of the Segmentation The main advantages of segmentation are as follows:
• It provides a powerful memory management mechanism.
• Data related or stack related operations can be performed in different segments.
• Code related operation can be done in separate code segments.
• It allows to processes to easily share data.
• It allows to extend the address ability of the processor, i.e. segmentation allows the use of 16 bit
registers to give an addressing capability of 1 Megabytes. Without segmentation, it would require 20
bit registers.
• It is possible to enhance the memory size of code data or stack segments beyond 64 KB by allotting
more than one segment for each area.

8. List and explain the machine control flags of 8086 microprocessor.

In 8086 there are 3 different flags which are used to enable or disable some basic operations of the
microprocessor. These flags and their functions are listed below.
Flag Bit Function

D This is directional flag. This is used in string related operations. D = 1, then the string will be
accessed from higher memory address to lower memory address, and if D = 0, it will do the
reverse.

I This is interrupt flag. If I = 1, then MPU will recognize the interrupts from peripherals. For I = 0,
the interrupts will be ignored

T This trap flag is used for on-chip debugging. When T = 1, it will work in a single step mode.
After each instruction, one internal interrupt is generated. It helps to execute some program
instruction by instruction.
MICROPROCESSOR AND MICROCONTROLLER Page |1

UNIT-II: 8086 PROGRAMMING: Program development steps, instructions, addressing

modes, assembler directives, writing simple programs with an assembler, assembly language
program development tools.
***
Concept-1: Program development steps
Concept-2: ALP to machine codes
Concept-3: Instructions
Concept-4: Addressing modes
Concept-5: Assembler directives
Concept-6: Writing simple programs with an assembler
Concept-7: Assembly language program development tools.

Unit Outcomes:
At the end of this unit you will learn:
1. Write a task list, flow chart or pseudo code for simple programming problem.
2. Write code, assemble and run a very simple assembly language program.
3. Describe the use of program development tools such as editors, assemblers,
linkers, locators, debuggers and emulators.
4. Properly document assembly language programs
Introduction:
What is Assembly Language?
➢ An assembly language is a low-level programming language for microprocessors and
other programmable devices.
➢ Each personal computer has a microprocessor that manages the computer's
arithmetical, logical, and control activities.
➢ Each family of processors has its own set of instructions for handling various
operations such as getting input from keyboard, displaying information on screen and
performing various other jobs. These set of instructions are called 'machine language
instructions'.
➢ A processor understands only machine language instructions, which are strings of 1's
and 0's.
➢ An assembly language implements a symbolic representation of the machine code
needed to program a given CPU architecture.
Why you should learn Assembly Language?

RCEE, ECE Dept ANLH