Alfaisal University

College of Engineering
Department of Software and Electrical Engineering

EE 210/SE223
Digital Design

Chapter 5
Sequential Circuits -- Introduction

1
 Topics
• Introduction to sequential circuits
• Storage elements
– Latches and Flip-flops
• SR and D latches
• D, T, and JK Flip-flops
• Sections 5.1 to 5.4

2
 Sequential Circuits
• So far, we have considered combinational circuits
– The outputs at any time are entirely dependent on current inputs.

• A sequential circuit consists of a combinational circuit

and memory elements.
• The outputs of memory elements are connected to the
inputs of combinational circuit to form a feedback path.

(From Mano & Ciletti)

3
 Sequential Circuits (cont.)
• The memory elements are devices capable of
storing binary information within them.
• The binary information stored in the memory
elements at any given time defines the state of the
sequential circuit.
-Present state: The outputs of memory elements.
• The outputs are functions of inputs and the present
states.
• The next state of storage elements is also a function
of inputs and the present state.

4
(From Mano & Ciletti)
 Sequential Circuits (cont.)
• There are two main types of sequential circuits:
– Synchronous and asynchronous circuits (the classification is a function of the timing of
their signals)
• Synchronous sequential circuits are synchronized by a central signal called a
clock to update the circuit at discrete times.
– A storage element of a synchronous circuit is called flip-flop (FF); it stores either 0 or 1.
– The clock is connected to all FFs (periodic train of clock pulses – the storage element is
only affected at the arrival of each pulse).

(From Mano & Ciletti)

5
 Sequential Circuits (cont.)
• An asynchronous circuit does not have a clock.
– Its behavior depends upon the input signals at any instant of time
and the order in which the inputs change.
– It should have at least one feedback path.
• It is a combinational circuit with feedback.
• The memory elements commonly used in asynchronous
sequential circuits are time-delay devices.
– The propagation delay between the inputs and outputs of memory
elements.
• We begin with asynchronous circuit elements (latches) that will
allow us to implement FFs and synchronous circuits. From then
on, we will focus on synchronous circuits for this course.

6
(From Mano & Ciletti)
 SR Latch
• With NOR gates:
1 0 1 0
0 0 1 0
0 1 0 1
0 0 0 1
1 1 0 0
(From Mano & Ciletti)

• In normal operations:
– Q and Q' are the complements of each other
– S=0 & R=0 à The outputs hold the previous state
– S=1 & R=0 à Q=1, Q’=0; the latch is in the set state
– S=0 & R=1 à Q=0, Q’=1; the latch is in the reset state
• SR = 11 is avoided à Outputs are not complementary.
– Input transition 11à00 circuit goes to unpredictable state.
7
 SR Latch
• In the SR latch using NOR gates, the inputs are
active-high.

• By replacing NOR gates with invert-AND, the SR

latch can be made with NAND gates.
• In the SR latch using NAND gates, the inputs
are active-low.

8
(From Mano & Ciletti)
 SR Latch With NAND

• In normal operations: (From Mano & Ciletti)

– Q and Q' are the complements of each other.

– S=1 & R=1 à The outputs hold the previous state
– S=0 & R=1 à Q=1, Q’=0; the latch is in the set state
– S=1 & R=0 à Q=0, Q’=1; the latch is in the reset state
• SR = 00 is avoided
• By complementing inputs in the function table of the NOR
gate latch, it is obtainedà sometimes called S’R’ latch.
9
 Latch With Control Input (gated latch)
• The additional control input (En) acts as an enable signal; to
control when the state of the latch can be changed.

(From Mano & Ciletti)

• The inputs are active-high.

• In the indeterminate condition (all inputs are 1):
– Both inputs of basic SR latch are 1 à forbidden state.
– When En changes from 0à1, one cannot determine the next state. It
depends on whether S or R goes to 0 first.
10
 D Latch (Transparent Latch) (to eliminate the undesired condition)
• If S=D and R=D’

(From Mano & Ciletti)

• The D input (data) is sampled when En = 1.

– If D=0à Q=0, the circuit is in the reset state.
– If D=1à Q=1, the circuit is in the set state.
11
 Graphic Symbols for Latches
• Inputs are in the left and outputs (Q & Q’) are in the
right.
• Bubbles at the inputs mean the corresponding inputs
are active low.
• The SR latches may have the En signal.

(From Mano & Ciletti)

12
 Latches vs. Flip-Flops
• The latches are level sensitive.
– They respond to the inputs if the level of the enable signal
is high.

(From Mano & Ciletti)

– Consider a D-Latch with the clock signal connected to the

control input. Then, its output can change anytime while
the clock is at its active level.

13
 Latches vs. Flip-Flops (cont.)
• The flip-flops are edge-triggered; they respond to the
inputs during a signal transition.
– Positive-edge (rising-edge)

(From Mano & Ciletti)

– Negative-edge (falling-edge)

14
 Storage Elements: Flip-Flops
• There are two ways that a latch can be modified to
form a Flip-flop:
1. Using two latches (master and slave) to isolate the
external output of the FF from its external input.
2. Produce a FF so that it is only enabled during the clock
transition.
• In both cases the FF will be edge-triggered.

15
 Edge-triggered D Flip-Flop (Master-Slave)

• A negative-edge triggered D flip-flop (DFF) using two

D latches is shown below: Y(t)=D(t) Y(t0)=D(t0)
Q holds
En Output
0 Hold
1 Input

Clk
(From Mano & Ciletti)
Y(t) holds D(t0)
• While Clk=1 à Y will follow input D, i.e., Q(t)=Y(t)= D(t0)
Y(t)=D(t) but Q will hold its current value.
– At the time just before the falling edge (t=t0), Y(t0)=D(t0)
• While Clk=0 à Y holds D(t0) and it will be fixed, and Q will
follow Y.
• Function table and graphical symbol are
– Q(t+1)=D(t0) Clk Q(t+1)
D 16
 Positive-edge DFF (Master-Slave)
• A positive-edge triggered DFF can be obtained by
changing the inversion of the clock signal.
– Output of master latch (Y) follows D when clock is low
(slave is in hold state).
– Output of slave latch (Q) follows Y when clock is high
(master is in hold state).

(From Mano & Ciletti)

17
 Another Positive-edge Triggered DFF
• Two latches respond to the external D and Clk inputs.
• The third latch provides the output of DFF.

(From Mano & Ciletti)

18
 Another Positive-edge Triggered DFF (Clk=0)

• If Clk=0,
– S=1 & R=1. The output latch holds the current state.

1
0

(From Mano & Ciletti)

19
 Another Positive-edge Triggered DFF (D=0, Clk:0à1)

• If D=0 and a rising edge at Clk appears (0à1),

– R = 1à0 and the output latch goes into its reset state (Qà0).
• Further changes in D while Clk=1 cannot change R.

0 (Reset)

1
à à0
0à1
à à1
à
1 à0

0 1
20
(From Mano & Ciletti)
 Another Positive-edge Triggered DFF (D=1, Clk:0à1)

• If D=1 and a rising edge at Clk appears (0à1),

– S = 1à0 and the output latch goes into its set state (Qà1).
• Further changes in D while Clk=1 cannot change S

1 (Set)

1 à0
à à à1
0à1
à à0
1

1 0
21
(From Mano & Ciletti)
 Direct (or Asynchronous) Inputs
• Some FFs have asynchronous inputs to force the
output Q to a particular value.
• An asynchronous signal that forces Q=1 is called an
asynchronous set or preset
– The output will remain 1 as long as the set input is active
(changes in D and CLK are ignored).
• An asynchronous signal that forces Q=0 is called an
asynchronous clear or reset
– The output will remain 0 as long as the reset input is active
(changes in D and CLK are ignored).

22
 DFF with an Active Low Asynchronous Reset
• If Reset=0, then

1 0

(From Mano & Ciletti) 23

 DFF with Asynchronous inputs
• Active low set and reset signals.
-

• Active high set and reset signals.

-

24
 Characteristic Tables and Equations
• A characteristic table shows the properties of a FF in
tabular form
– It shows the next FF output value (Q(t+1)) based on the
current FF input value (Q(t)) after the active edge
transition of the clock.
• The characteristic table for a DFF is:
• The characteristic equation
– Q(t+1) = D

(From Mano & Ciletti)

25
 JK Flip-Flop
• It can be constructed from DFF

(From Mano & Ciletti)

26
 QU = JQCt) + 1Q(t)
·

Q( + 1) = D(to) = D
State Q D at the
The of =

clock edge chaupe

time aff the
 -

---

P ,
!
:
-
---
ak-
I -

+
-
-
 JK Flip-Flop (cont.)

(From Mano & Ciletti)

• From the circuit, D=JQ’(t)+K’Q(t). By using the

characteristic equation of a DFF (Q(t+1)=D):
– The characteristic equation of a JK FF can be obtained as
Q(t+1)=JQ’(t)+K’Q(t).

27
 T (Toggle) Flip-Flop
• It can be obtained from a JK FF when J and K are
tied together.

(From Mano & Ciletti)

• The characteristic equation (J=K=T):

• Q(t+1) = JQ’(t)+K’Q(t) = TQ’(t)+T’Q(t) = !⨁#(%)

28
 T (Toggle) Flip-Flop
• It can be constructed using a DFF.

(From Mano & Ciletti)

I
8

11
D
O
I

O .

29
Ask yourself
C a you build a D-ff out of < JK-ff %
&

* Com build a T-FF out

of a
JK-FF)
you
build D-ff out T-FF ?
*
Can you a
of a

build JK-ff cut T-fFC

Can of
a
a
*
you
-

showed how build

(Previous slides just you
to

out D )
a JK an T of . .

-
 Overview of Synchronous Sequential Circuits
• As mentioned before, a sequential circuit has inputs,
outputs and internal states.

(From Mano & Ciletti)

• These circuits are modeled in two forms:

– The Mealy model
– The Moore model
• These two models are refereed to as finite state
machines (FSM).

30
 Moore and Mealy Models of FSM
• In a Moore machine, the output is a function of the
state only.

(From Mano & Ciletti)

• In a Mealy machine, the output is a function of the

state and the inputs.

(From Mano & Ciletti)

31
 State Diagrams
• Finite state machines are usually represented by
state diagrams.
• It shows the time sequence of inputs, outputs and FF
states.
• A state diagram consists of:
– States which are represented by circles.
– Transitions which are represented by arcs.

32
 State Diagrams (cont.)
• States of the system define the history of the circuit.
• One state should always be the initial or starting
state of the system, which is entered immediately
after power up.
• Transitions are identified by the inputs.
• On the active edge of the clock, the machine will
change state along a transition.

33
 Representing the Outputs in State Diagrams
• In a Moore model machine, the output is a function of the
state only.
(From Mano & Ciletti)

– Therefore, each state should specify its outputs.

– Output changes synchronously to the clock.
• In a Mealy model machine, the output is a function of the state
and the inputs.

(From Mano & Ciletti)

– Therefore, outputs are specified on the transition arcs.

– Output may change asynchronous to the clock.

34
 Design Problem: Three 1s Detector

Design a clocked circuit with one input x and one

output y. The output y is 1 if a sequence of three or
more consecutive 1s appears in x.

001100111000 1001111 00

00000000100000 0 001100

35
 Synchronous Circuit Design Procedure

1. From the word description and specification or

timing diagram, draw the state diagram.
2. Reduce the number of states if possible.
3. Assign binary values to states.
4. Obtain the binary-coded state table.
5. Choose flip-flop type.
6. Derive simplified flip-flop input equations and output
equations.
7. Draw the logic diagram.

36
 Step 1 of Design Procedure (three 1s detector)
1. From the word description and specification or timing
diagram, draw the state diagram.
• First, we design the Moore model.
– The outputs are specified as part of each state.

g
input =

O
-

S Havert see
imput Psaoutput
one
o

output
any Is

G
O
~

Furo &
=0
= imput
imt
C
-

· Seei
owes
output
A&
-
impute
Leart -
37
 Step 2 of Design Procedure (three 1s detector)
2. Reduce the number of states if possible.
• This is called state reduction.
• It will be considered later.

A reduce FSM
·
Simplifies the
logic
Simplifies the circuit
-

38
 Step 3 of Design Procedure (three 1s detector)
3. Assign binary values to the states (state assignment).
Assignment 1 Assignment 2 Assignment 3 (From Mano & Ciletti)

State Binary

C
Gray Code One-Hot
A B A B A B C D
S0 & O O O 00 o I

i !
0010
S1 O I
S2 I 018 O
O
S3 I I I O 100 .
0

• These binary values will be stored in flip-flops.

• Sometimes the choice of state assignment has a large impact on the cost of
the final implementation.
• It is difficult to choose the optimal assignment (nobody knows how).
• Unused bit combinations will be don't cares in our circuit. We do not have
them in this example.

is the used the caring sides

his
encoding in
39
 Step 4 of Design Procedure (three 1s detector)
4. Obtain the binary-coded state table from the state diagram
and the state assignment table.
Present Next
State Input State Output

So
S0
S0
S1

So
S1
S2 (From Mano & Ciletti)
S2 Se
S3 So
S3 I

O O O
O I 8
• Assignment 1 à -G E

I O O

o G O

[ I O
O O I
I I I
40
 Step 4 of Design Procedure (cont.)

(From Mano & Ciletti)

• In the state table: the next state of FFs are functions

of the present state A(t), B(t) and inputs x.

• The output is a function of the present state.

41
 Step 5 of Design Procedure

5. Choose flip-flop type.

• For now, we will focus on the use of D flip-flops: Q(t+1) = DQ
to
inputstuffs ,

~
DA DB
Te
[ (3
,

5 7 )
Da =
, , .

Dis = [ (1 ,
3, 7) ·

(From Mano & Ciletti)

y = [(6 ,
7) .

42
 Step 6 of Design Procedure
6. Derive simplified flip-flop input equations and output
equations.
– A(t+1) = DA(A,B,x) = Σ(3,5,7)
– B(t+1) = DB(A,B,x) = Σ(1,5,7)
– y(A,B,x) = Σ(6,7)

Bet
A00011
16
A
By
00011 10
ABx oa
110

I O
i o i I
O

11

Da DB Y
I AxteX = Ax + Bx = AB. 43
 Step 7 of Design Procedure

7. Draw the logic diagram

– DA = Ax + Bx
– DB = Ax + B’x
– y = AB QA
At
H Ax +BX

QB
a By

AxtB +

ais

QAQB AB
(From Mano & Ciletti) 44
 Synthesis Using JK Flip-Flops
-
-

• First, we obtain the excitation table of the JK FF from

its characteristic table.

Q(t) Q(t+1)

0 X
1 X
X 1
X 0

45
 Synthesis Using JK Flip-Flops (three 1s detector)

• The output would not change since it is a function of

the present state: y = AB.
• Using the FF excitation and state tables, we obtain
the truth tables for inputs (JK) of all FFs.

Q(t) Q(t+1)

8 X
1 + X 1
o Y X0
X0OX
XO I X
X0 X0
X I XI

46
Synthesis Using JK Flip-Flops (three 1s detector)

AB.
from before , T
=

JA KA JB Ki
Byood"10 Blood 10
A
Blood 11 10

*
Byoo o I " 10

↑ A
I 1XX XX
XXXXo
I
↑ XXxx i I 1XX i XX I

Bei By X An + Ad
47
Synthesis Using JK Flip-Flops (three 1s detector)
• JA = Bx’
• KA= Bx
• JB = x
• KB= Ax + A’x’ =
= A⨁#

(From Mano & Ciletti)

48
 TA TB

&

%
A
TAF Ax
+ ABX
Ti =
Bx A
+
·
A

At
-

B4
 Design Example Using One-Hot Assignment: Three 1s
Detector
• At any time, only one bit is 1 One-Hot
– # of FFs = # of states State EFGH
• It usually leads to simpler combinational S0 0001
logic blocks at the expense of more FFs. S1 0010
• The state diagram should have an initial S2 0100
state. S3 1000

Present Next
Start State Input State
S0 S0 State Output
S0 S1 S0 0
S1 S0 S1 0
S1 S2 S2 0
S2 S0 S3 1
S2 S3
S3 S0
S3 S3

49
 Design Example Using One-Hot (cont.)
Present Next
Present Next State Input State
One-Hot State Input State
EFGH x EFGH
State EFGH
S0 S0 0001
S0 0001 S0 S1 0001
S1 0010 S1 S0 0010
S2 0100 S1 S2 0010
S3 1000 S2 S0 0100
S2 S3 0100
S3 S0 1000
S3 S3 1000
EFGH y
0001 0
0010 0
0100 0
1000 1

50
 Design Example Using One-Hot (cont.)
Present Next
• H(t+1) = DH = x’
State Input State
EFGH x EFGH • G(t+1) = DG = xH
0001 0001 • F(t+1) = DF = xG
0001 0010 • E(t+1) = DE = xF + xE
0010 0001
0010 0100 • Y=E
0100 0001
0100 1000
1000 0001
1000 1000

• Don’t forget the FSM should start from the initial state (S0).
• The asynchronous Clear inputs of all FFs except H are
connected to the Start input.
• Only the Preset input of H is connected to the Start input signal.

51
 Exercise: Design Two 1s Detector
• Design a clocked sequential circuit with one input x and one
output z. The output z is 1 if the input x was 1 during the
previous two clock cycles.
N

MoorE -
O
G⑳en
output Da
Is
&
no

output
o
O
one
o
I

↑
Dr seen two Is

output = A

I 52
 Exercise: Design Two 1s Detector
• Design a clocked sequential circuit with one input x and one
output z. The output z is 1 if the input x was 1 during the
previous two clock cycles.

MEALY /0
-
-
-

Sto& t
I

do
&
do
I
↓ D
,
input/output 52
 Synthesis Using T Flip-Flops
• As mentioned before, the characteristic table
defines the next state of a FF based on its present
state and input(s).
– It is mainly used in analysis.

• For design, we want to obtain the input(s) of a FF

based on the FF transition from the present state
Q(t) to the next state Q(t+1)
– Such a table is called an excitation table.
Q(t) Q(t+1) T

53
 Synthesis Using T Flip-Flops
• The output would not change since it is a function of
present state: y=AB
• Using the FF excitation and state tables, we obtain
the truth tables for inputs (T) of all FFs.
FF Inputs
TA TB

Q(t) Q(t+1) T

54
Synthesis Using T Flip-Flops

55
 Moore and Mealy Models of FSM
• In a Moore machine, the output is a function of the
state only.

(From Mano & Ciletti)

• In a Mealy machine, the output is a function of the

state and the inputs.

(From Mano & Ciletti)

56
 Example: Design Two 1s Detector (Moore Model)
• Design a clocked sequential circuit with one input x and
one output z. The output z is 1 if the input x was 1 during
the previous two clock cycles.
Present Next
Present Next State Input State
State Input State A B x A(t+1) B(t+1)
S0 0 S0 0 0 0 0 0
S0 1 S1 0 0 1 0 1
S1 0 S0 à 0 1 0 0 0
S1 1 S2 0 1 1 1 0
S2 0 S0 1 0 0 0 0
S2 1 S2 1 0 1 1 0
1 1 0 x x
Assignment1 1 1 1 x x
State Binary
AB z
S0 00 0
S1 01 0 àz =A
S2 10 1 57
 Example: Design Two 1s Detector (cont.)

– A(t+1) = DA(A,B,w) = Σ(3,5) + d(6,7)

– B(t+1) = DB(A,B,w) = m1+ d(6,7)
– z=A

58
 Design Using Mealy Model
• In a Mealy model machine, the output is a function
of the state and the inputs.
– Therefore, outputs are specified on the transition arcs.
– Output may change asynchronous to the clock.

(From Mano & Ciletti)

59
 Example: Design Two 1s detector (Mealy Model)
• State diagram: Yo
-
do
: IG 50 60
Si

VI .

• Sate table:
Present Next Present Next
State Input State Output State Input State Output
w z A w A z

So

··
So 0 O

So I 51 0
S1 O So O
Si I Su I
60
 Example: Design Two 1s detector (Mealy Model)
• Circuit diagram:

[I
·

Dr z

61
 State Reduction
In some sequential circuits, the numeric values of the states is not important.
Perhaps the circuit simply needs to produce a certain output sequence.
As long as the output sequence is correct, then if we can reduce the number
of states (and thus the number of flip-flops), then the final circuit can be
simplified.
Shown below are examples of such circuits.

ASCII
Code Converter EBCDIC Code
Code

Gray
Code Converter BCD Code
Code

Input Sequence Detector Output = 1 if correct

input sequence detected
Sequence (Digital Lock)
Output = 0 otherwise

Note: Reducing the number of states may not always reduce the number of
flip-flops. For example, if the number of states is reduced from 13 to 9, then 4
flip-flops are still required. However, the associated combinational logic
circuitry may be reduced. 62
 State Reduction – Procedure

1) Form the state table.

2) If 2 states are equivalent, eliminate one and replace all
references to it with the equivalent state.

-
Note: Two states are equivalent if for each input
combination they give identical outputs and have
the same next state or an equivalent next state.
3) Redraw the state table. Repeat steps 2 and 3 as many
times as possible.
4) Draw the final (reduced) state diagram.
5) Test the original and reduced state diagrams to ensure
that they produce the same result.

63
 State Reduction – Example
Example:
Use state reduction to reduce the state diagram below if possible. Draw the
reduced state diagram. Test the original state diagram and the reduced state
diagram with the input sequence 01010110100 to see if they produce the
same output sequence.

64
1) Form the state table.
2) If 2 states are equivalent, eliminate one and replace all references to it with the
equivalent state.
Note: Two states are equivalent if for each input combination they give identical
outputs and have the same next state or an equivalent next state.

State Transition Table

Next State Output
PS x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1

65
1) Form the state table.
2) If 2 states are equivalent, eliminate one and replace all references to it with the
equivalent state.
Note: Two states are equivalent if for each input combination they give identical
outputs and have the same next state or an equivalent next state.

State Transition Table

Next State Output
PS x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d I
0 0
df e ed f 0 1
e9 a d f 0 1

- f
g
g of
a f
0 1
0 1

65
3) Redraw the state table. Repeat Next State Output
steps 2 and 3 as many times as PS x=0 x=1 x=0 x=1
a a b 0 0
possible. b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f e f 0 1

66
4) Draw the final (reduced) state
diagram.

Next State Output

PS x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1

67
Example: (continued)
Test the original state diagram and the reduced state diagram with the input
sequence 01010110100 to see if they produce the same output sequence.

Original state diagram:

State a a b c d e ffgf g a

Input 0 1 0 1 0 1 1 0 1 0 0
Output 0000011 0 1 0 0

Reduced state diagram:

State a abcdedded ea
Input 0 1 0 1 0 1 1 0 1 0 0
Output 00000110100 68
 How do you analyze a sequential circuit?
• For a combinational circuit, we could find a truth
table which shows how the outputs are related to
the inputs.
• A state table is the sequential analog of a truth
table. It shows inputs and current states on the
left, and outputs and next states on the right.
– For a sequential circuit, the outputs are dependent
upon not only the inputs, but also the current state of
the flip-flops.
– In addition to finding outputs, we also need to find the
state of the flip-flops on the next clock cycle.

69
Analyzing a Sequential
Circuit
• A basic state table for our
example circuit is shown
below.
• Remember that there is one
Current State Input Next State output
input X, one output Z, and
Q1 Q0 X Q1 Q0 Z
two flip-flops Q1Q0.

·
0 0 0
• The present state Q1Q0 and 0 0 1
the input will determine the 0 1 0
next state and the output. 0 1 1
1 0 0
1
1
0
1
1
0
·
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1 1 1 D
 The outputs are easy

• The output depends on the

current state – Q0 and Q1 –
as well as the inputs.
• From the diagram, you can
Current State Input Next State output
see that
Q1 Q0 X Q1 Q0 Z
Z = Q1Q0X 0 0 0 0
0 0 1 0
0 1 0 0
Output at the current time
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
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1 1 1 1
 Flip-Flop Input Equations
• Finding the next states is harder. To do this, we must figure
out how the flip-flops are changing.
Step 1:
Find Boolean expressions for the flip-flop inputs.
i.e. How do the inputs (say, J & K) to the flipflops
depend on the current state and input.
Step 2:
Use these expressions to find the actual flip-flop input
values for each possible combination of present states and
inputs.
i.e. Fill in the state table (with new intermediate columns).
Step 3:
Use flip-flop characteristic tables or equations to find the
next states, based on the flip-flop input values and the
present states.
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 Step 1: Flip-flop Input Equations
• JK flip-flops each have
two inputs, J and K. (D
and T flip-flops have
one input each)
• For our example, the
flip-flop input
equations are:
J1 = X’Q0
K1 = X + Q0
J0 = X + Q1
K0 = X’

73
 Step 2: Flip-flop Input Values
• With these equations, we can make a table showing J1, K1, J0 and K0 for the
different combinations of present state Q1Q0 and input X.

J1 = X’Q0 J0 = X + Q 1
K 1 = X + Q0 K0 = X’
Current State Input Flip Flop Inputs

I
Q1 Q0 X J1 K1 J0 K0 Q(t + 1) Qo(t + 1)
·

·
0 0 0 0 0 0 1 O

g
0 0 1 0 1 1 0 ⑧

0 1 0 1 1 0 1

i
0 1 1 0 1 1 0
1 0 0

·
0 0 1 1
1 0 1 0 1 1 0
1 1 0 1 1 1 1
&

1 j
1 1 0 1 1 0 8 P 74
 Step 3: Concluded
• Finally, use the JK flip-flop characteristic tables or
equations to find the next state of each flip-flop,
based on its present state and inputs.
Current State Input Flip Flop Inputs Next State Output
Q1 Q0 X J1 K1 J0 K0 Q1(t+1) Q0(t+1) Z
0 0 0 0 0 0 1 0 0 0
0 0 1 0 1 1 0 0 1 0
0 1 0 1 1 0 1 1 0 0
0 1 1 0 1 1 0 0 1 0
1 0 0 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0 1 0
1 1 0 1 1 1 1 0 0 0
1 1 1 0 1 1 0 0 1 1
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 Getting the state table columns straight
• The table starts with Present State and Inputs.
– Present State and Inputs yield FF Inputs.
– Present State and FF Inputs yield Next State,
based on the flip-flop characteristic tables.
– Present State and Inputs yield Output.
• We only care about FF Inputs in order to find
the Next State.
• Note: the outputs occur this cycle and the
next state in the next cycle.

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 Exercise

• Complete the state table for the following

sequential circuit.

D A
X
CLK A’

D B

CLK
B’
CLK

77
 State Diagrams
• We can also represent the state table graphically with a state
diagram.
• A diagram corresponding to our example state table is shown
below.
input output
Present State Inputs Next State Outputs 0/0 1/0
Q1 Q0 X Q1 Q0 Z
0 0 0 0 0 0 1/0
0 0 1 0 1 0 00 01
0 1 0 1 0 0
0 1 1 0 1 0 1/1
0/0 1/0 0/0
1 0 0 1 1 0
1 0 1 0 1 0
0/0
1 1 0 0 0 0 11 10
1 1 1 0 1 1
state
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 Sizes of State Diagrams
• Always check the size of your state
diagrams.
– If there are n flip-flops, there
should be 2n nodes in the diagram.
– If there are m inputs, then each
0/0 1/0
node will have 2m outgoing arrows
from each state. 1/0
00 01
• In our example,
– We have two flip-flops, and thus 1/1
0/0 1/0 0/0
four states or nodes.
– There is one input, so each node 0/0
11 10
has two outgoing arrows.

79
 Exercise

• Draw the state diagram for the circuit in

Exercise 1.

80