▪ The 8086 (also called iAPX86) is a 16-bit microprocessor chip designed and introduced by Intel in 1978.

▪ The 8086 gave rise to the x86 architecture of Intel's future processors.Since its introduction, the architecture of
8086, the so-called x86 architecture, has undergone evolutionary stages.

▪ It was a 16-bit microprocessor housed in 40-pin dual in-line package (DIP) and operated with a single +5V
power supply.

▪ It has 20 address lines and capable of addressing 1 Mbyte memory space.

▪ The 8086 has a 16-bit I/O addressing mechanism that could address 64 K of I/O address space.

▪ The 8086 family consists of two types of 16-bit microprocessors, the 8086 and 8088.

▪ The 8088 is functionally similar to the 8086, except that it has an 8- bit external data bus.

▪ Its internal architecture and instruction set are identical with those of 8086.

Internal - General Use

 ▪ The internal architecture of the 8086 microprocessor is divided into two separate units: the Execution
Unit (EU) and the Bus Interface Unit (BIU). These two units are independent of each other.

Internal - General Use

 ▪ The EU decodes and executes instructions. The phases of execution an instruction are Fetch, Decode, Execute and Write.

▪ The fetch phase performs the fetching of the instructions from the Instruction Queue.

▪ The Decode phase performs the decoding of the instruction.

▪ The Execute phase performs actual operation on the data.

▪ The Write phase performs the operation of storing the computed result at the destination.

▪ Whenever EU is ready to execute a new instruction, it fetches the instruction code from the front end of the BIU's
Instruction Queue.

▪ The EU then executes the instruction in some definite number of clock cycles. The EU has no connection to the system
buses.

▪ If a memory or I/O device has to be accessed in course of execution of an instruction, the EU informs the BIU of its needs.

▪ The BIU executes an appropriate external access bus cycle in response to the EU's demand.

Internal - General Use

 The functional components of the Execution Unit are:

▪ Control circuitry and Instruction decoder

▪ Arithmetic and Logic Unit (ALU)

▪ Flag Register

▪ General purpose registers

▪ Pointer registers

▪ Index registers

Internal - General Use

 ▪ Control Circuitry and Instruction Decoder: The control circuit of the EU directs all the internal operations of the
processor. The Instruction Decoder in the EU translates the instruction fetched from memory into a series of
actions carried out by the EU.
▪ Arithmetic and Logic Unit: The ALU performs 8-bit or 16-bit mathematical operations such as addition,
subtraction, multiplication, division, data conversion and logical operations like logical NOT, OR, or AND. It also
performs register increment, decrement, and shift operations.

▪ Flag Register: The 8086 microprocessor has nine 1-bit flags to reflect the status of the processor. The 16-bit flag
register of 8086 stores the information about the status of the processor and the status of the instruction
executed most recently.

▪ General Purpose Registers: The 8086 microprocessor has four 16- bit general purpose registers. They are AX,
BX, CX, and DX. Each of these 16-bit registers can be considered as two 8-bit registers distinguished as high and
low order bytes of the respective 16-bit registers and referenced as AH, AL, BH, BL, CH, CL, DH, and DL.

▪ Pointer Registers: The 8086 microprocessor has two Pointer registers .The Stack Pointer (SP) and Base
Pointer(BP). The stack Pointer register points to the current top of the stack. The Base Pointer register can be
used as a pointer to a memory location.

▪ Index Register: The 8086 microprocessor has two Index registers- Source Index (SI) and Destination Index (DI).
Both these registers can be used as pointers to memory locations.

Internal - General Use

 ▪ The Bus Interface Unit (BIU) is responsible for transfer of instructions, addresses, and data on the
system bus to the Execution Unit.
▪ It handles the transfer of data between the processor, memory and I/O devices.
▪ It includes instruction fetch, data fetch, address transfer and computation of effective address of
the memory .Thus, the BIU provides all external operations.
The functional components of BIU are:

▪ Bus Control Logic

▪ Instruction Queue

▪ Segment registers

▪ Instruction pointer

Internal - General Use

 ▪ Bus Control Logic :the Bus Control Logic generates necessary control signals to drive
the system buses.
▪ Instruction Queue :The Instruction Queue is a First-In-First-Out(FIFO) group of
registers in which 6-bytes of instructions code are prefetched from memory ahead
of time. This is done in order to speed up program execution by overlapping
instruction fetch with execution. This mechanism is known as pipelining

▪ Segment Registers: The BIU contains four 16-bit segment registers: Code Segment
(CS). Data Segment (DS), Stack Segment (SS) and Extra Segment (ES). These registers
are used to store the 16-bit starting address of the four memory segments/The BIU
generates a 20-bit address using the segment and offset components of an address

▪ Instruction Pointer: Instruction Pointer (IP) always holds the offset address of
memory location of the next instruction to be executed. As the instruction is
executed, the IP is advanced to point to the next instruction in memory

Internal - General Use

Internal - General Use
 The 8086 microprocessor has four 16-bit General Purpose Registers (GPRS). These are AX, BX, CX
and DX. The 16-bit GPRS AX, BX, CX and DX can also be used as two 8-bit registers (AH, AL; BH, BL;
CH, CL; DH, DL). For example, the 16-bit register DX can be considered as two 8-bit registers DH
(High byte of DX) and DL (Low byte of DX).
▪ The AX Register: The register AX functions as accumulator. The AX register is called 16-bit
accumulator while AL is the 8-bit accumulator. All input/output operations are performed
through this register. In addition, string and arithmetic instructions make use of this register.
▪ The BX Register: The BX register is called the Base register. This is the only GPR whose contents
can be used for addressing 8086 memory.
▪ The CX Register: The CX register is known as the Counter register because some instructions
(e.g., SHIFT, REPEAT, LOOP) use contents of CX register as a counter.

▪ The DX Register: The DX register serves as the Data register. It is used in word multiply and
divide instructions as well as indirect I/O addressing.

Internal - General Use

 ▪ The 8086 microprocessor has two 16-bit pointer registers: Stack Pointer (SP) and Base Pointer (BP) registers.
Similarly, there are index registers: Source Index (SI) and Destination Index (DI) registers. These four registers
can be used as GPRS in arithmetic and logical operations.

▪ The SP and BP registers are used to access data in the stack segment. The SP acts as a stack pointer. The SP
register is dedicated for maintaining the stack.

▪ The stack is an area of memory into which data can be stored and retrieved on the basis of Last-In-First-Out
(LIFO).

▪ The stack is useful in implementing procedure calls, recursions, passing of parameters, etc In the 8086
microprocessor, there can be several stack segments in the memory. But only one of them can be active at
any given instant.

▪ The SP register points to the top of the active stack segment The SP is used as an offset from the current
stack segment during the execution of instructions tha involve the stack segment in external memory.

▪ The SP contents an automatically updated (incremented or decremented) due execution of POP or PUSH
instruction

Internal - General Use

 ▪ The 8086 microprocessor has 20-bit address bus.
▪ However, is Instruction Pointer is 16-bit wide and can hold a 16-bit address.
▪ The processor must be able to place a 20-bit address to access 1 Megabyte
memory.
▪ To enable this, the concept of segmentation is employed in the design of the 8086
microprocessor. The 806 Megabyte memory is segmented into segments of up to 64
K byte each. A segment can begin at any memory location that is divisible by 16.
▪ The 8086 can directly address four segments at a particular time. The BIU has four
segment registers for this purpose.
▪ These are the Code Segment (CS), Data Segment (DS). Stack Segment (SS) and Extra
Segment (ES) registers. The starting address of the currently active segments
contained in the segment registers.
▪ The CS, DS, SS and ES contain, respectively, the start of code, data stack and extra
segments
Internal - General Use
 ▪ The Instruction Pointer (IP) register always holds the offset memory address of the
next instruction to be executed.
▪ As the instruction is executed, IP is advanced to point to the instruction at the next
memory address.
▪ However, some instructions such as jump and procedure calls, can cause IP to be
loaded with new value, thereby branching to a new instruction.

Internal - General Use

 ▪ The flag register is a 16-bit register in the Intel 8086 microprocessor that contains information
about the state of the processor after executing an instruction.
▪ It is sometimes referred to as the status register because it contains various status flags that
reflect the outcome of the last operation executed by the processor.

Internal - General Use

 ▪ Two types
▪ (a) Status Flags – There are 6 flag registers in 8086 microprocessor which become set(1) or
reset(0) depending upon condition after either 8-bit or 16-bit operation.
▪ These flags are conditional/status flags. 5 of these flags are same as in case of 8085
microprocessor and their working is also same as in 8085 microprocessor.
▪ The sixth one is the overflow flag.

Internal - General Use

 ▪ (b) Control Flags – The control flags enable or disable certain operations of the
microprocessor.
▪ Directional Flag (D) – This flag is specifically used in string instructions. If directional flag is set
(1), then access the string data from higher memory location towards lower memory location.
If directional flag is reset (0), then access the string data from lower memory location towards
higher memory location.
▪ Interrupt Flag (I) – This flag is for interrupts. If interrupt flag is set (1), the microprocessor will
recognize interrupt requests from the peripherals. If interrupt flag is reset (0), the
microprocessor will not recognize any interrupt requests and will ignore them.
▪ Trap Flag (T) – This flag is used for on-chip debugging. Setting trap flag puts the
microprocessor into single step mode for debugging.

Internal - General Use

Internal - General Use
 ▪ Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a 5V DC
supply for its operation. The 8086 uses a 20-line address bus. It has a 16-line data bus.
AD0-AD15: Address/Data bus. These are low order address bus. They are multiplexed with
data. When AD lines are used to transmit memory address the symbol A is used instead of AD,
for example A0-A15. When data are transmitted over AD lines the symbol D is used in place of
AD, for example D0-D7, D8-D15 or D0-D15.

Internal - General Use

 ▪ A16-A19: High order address bus. These are multiplexed with status signals.
▪ S2, S1, S0: Status pins. These pins are active during T4, T1 and T2 states and is returned to
passive state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the 8288 bus
controller for generating all the memory and I/O operation) access control signals.
▪ HE’/S7: Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most
significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use
BHE (Active Low) signal.

Internal - General Use

 ▪ RD’: This is used for read operation. It is an output signal. It is active when low.
▪ READY : This is the acknowledgement from the memory or slow device that they have
completed the data transfer.
▪ INTR : Interrupt Request. This is triggered input. This is sampled during the last clock cycles of
each instruction for determining the availability of the request. If any interrupt request is
found pending, the processor enters the interrupt acknowledge cycle. This can be internally
masked after resulting the interrupt enable flag.

Internal - General Use

 ▪ NMI : Non maskable interrupt. This is an edge triggered input which results in a type II
interrupt.
▪ INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each interrupt
acknowledge cycle.
▪ RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters used to force
the microprocessor to release the bus.
▪ TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will
continue, else the processor remains in an idle state. The input is internally synchronized
during each of the clock cycle on leading edge of the clock.

Internal - General Use

 ▪ CLK : Clock Input. The clock input provides the basic timing for processing operation and bus
control activity.
▪ RESET : This pin requires the microprocessor to terminate its present activity immediately.
▪ Vcc : Power Supply( +5V D.C.)
▪ GND : Ground
▪ QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction
queue

Internal - General Use

 ▪ MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will operate in.
▪ LOCK’ : Its an active low pin. It indicates that other system bus masters have not been allowed to
gain control of the system bus while LOCK’ is active low(0). The LOCK signal will be active until the
completion of the next instruction.
▪ =DT/R : Data Transmit/Receive. This pin is required in minimum systems, that want to use an 8286
or 8287 data bus transceiver. The direction of data flow is controlled through the transceiver.
▪ DEN: Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum
system which uses transceiver. DEN is active low(0) during each memory and input-output access
and for INTA cycles.

Internal - General Use

 QS1 QS0 Status
0 0 No operation

First byte of op code

0 1
from queue

1 0 Empty the queue

Subsequent byte from

1 1
queue

Internal - General Use

 S2 S1 S0 Characteristics

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive state

Internal - General Use

 A17/S4 A16/S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

Internal - General Use

 ▪ Memory Segment :It is a portion of memory that is used to address the data and
instructions.
▪ Offset Address: it is a part of the address that is added to the segment address to
point to a specific location inside the segment.
For example: If the segment address is 1000H and offset address is 3000H then the memory
location becomes 13000H( 10*1000H + 3000H)
▪ Effective Address : It can be defined as the address of the data operand in the
memory. It can be calculated from the formula
( Effective Address = Segment Register + Offset Address). In 8086 the segment registers
are DS(Data segment), CS( code segment), ES( Extra Segment),SS (Stack segment).
▪ Physical Address : It is defined as the actual address of the data or instruction
where it is stored physically in the memory and calculated by (Physical Address =
10* segment Address + Offset Address).
▪ Segmentation : It is a process of dividing the memory into segments and each
segment can have a size of 64Kb( starting Address-0000H, last Address-FFFFH).

Internal - General Use

 In 8086 one megabyte is physically organized as an odd bank and an even bank,
each of 512Kbytes, addresses in parallel by a processor. Byte data with even address
transferred on D7-D0 , while byte data with odd address is transferred on D15-D8
bus lines. To select an even or odd bank its has BHE and Ao as selector lines.

Physical address PA = CS * 10 + DI +Displacement(if any)

Internal - General Use

 ▪ Segmentation is the process in which the main memory of the computer is
logically divided into different segments and each segment has its own base
address
▪ Code segment register (CS): is used for addressing memory location in the code
segment of the memory, where the executable program is stored.
▪ Data segment register (DS): points to the data segment of the memory where the
data is stored.
▪ Extra Segment Register (ES): also refers to a segment in the memory which is
another data segment in the memory.
▪ Stack Segment Register (SS): is used for addressing stack segment of the
memory. The stack segment is that segment of memory which is used to store stack
data.

Internal - General Use

Internal - General Use
 Segmentation process follows some rules as follows:
▪ The starting address of a segment should be such that it can be evenly divided by
16.
▪ Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.

Internal - General Use

 ▪ The 8086 microprocessor operates in minimum mode when MN/MX’ = 1.
▪ Minimum mode is indented for small and medium sized systems employing a
single processor.

Internal - General Use

 • All control signals are generated by the
microprocessor
• The minimum mode configuration consist of
• Three 8 bit latches (IC 8282)
• Two 8 bit transceivers(IC 8286)
• One control signal generator
• One clock generator (8284)

Latches – demultiplex the multiplexed lines AD0-AD15,A16/S3, A17/S4……

Transceivers – Separate data bus from data/address bus
Control signal generator – generates IOR’, IOW, MEMR’, MEMW’ control signals
Clock generator – generate clock signals and synchronize READY and RESET signals

Internal - General Use

 ▪ Designed for larger systems with and employees more than one processor
▪ Control signals must be externally generated – this requires an external bus
controller

Internal - General Use

 • Some of the control signals must be externally
generated
• For this purpose it contain an additional bus
controller

• Maximum mode configuration consist of

• Three 8-bit latches (IC 8282)
• Two 8-bit transceiver (ic 8286)
• One clock generator (82840
• Bus controller (8288)
• Interrupt controller (8259)

Internal - General Use

 1. Register and immediate modes
a)Register addressing mode
b)Immediate addressing mode
2.Memory Modes
a)Direct addressing mode
b)Register indirect addressing mode
c)Based addressing mode
d)Indexed addressing mode
e)Based indexed addressing mode
f)String addressing mode

Internal - General Use

 3)I/O Modes
4)Implied addressing mode

Internal - General Use

 Immediate Addressing Mode:
•The operand is specified explicitly within the instruction itself.
•Example: MOV AX, 1234H moves the immediate value 1234H into the AX register.

Register Addressing Mode:

•The operand is located in a register, and the instruction specifies this register.

•Example: MOV BX, AX copies the contents of the AX register into the BX register.

Internal - General Use

 Direct Addressing Mode:

•The instruction provides the effective address of the operand directly.

•Example: MOV AX, [1234H] moves the contents of memory location 1234H into the AX register.

Register Indirect Addressing Mode:

•The effective address of the operand is held in a register.

•Registers BX, SI, and DI are commonly used for this purpose.
•Example: MOV AX, [BX] moves the contents of the memory location pointed to by BX into the AX register.

Internal - General Use

 Based Addressing Mode:

•Combines a base register (BX or BP) with a displacement to calculate the effective address.
•Example: MOV AX, [BX + 5] adds 5 to the contents of BX to determine the memory address, then moves the

data from that address into AX.

Indexed Addressing Mode:

•Uses an index register (SI or DI) plus a displacement to determine the effective address.
•Example: MOV AX, [SI + 5] adds 5 to SI to calculate the memory address, then moves the data
from that address into AX.

Internal - General Use

 Based-Indexed Addressing Mode:
•Combines a base register with an index register to compute the effective address.
•Example: MOV AX, [BX + SI] adds the contents of BX and SI to get the memory
address, then moves the data from that address into AX.

Internal - General Use

 ▪ The Intel 8088 is a 16-bit microprocessor introduced in 1979. It is a modified
version of the Intel 8086, designed to be more cost-effective by using an 8-bit
external data bus
▪ 8-bit External Data Bus
▪ 16-bit Internal Architecture – The processor has 16-bit registers and ALU
▪ 20-bit Address Bus
▪ Clock Speeds – Available in 5 MHz, 8 MHz, 10 MHz, and 12 MHz versions.
▪ Segmented Memory Model – Uses segment and offset registers to address
memory efficiently, similar to the 8086.
▪ Interrupt System – Supports hardware and software interrupts
▪ Power Consumption – Lower than the 8086
▪ 40-Pin Dual In-Line Package (DIP)

Internal - General Use

Internal - General Use