What is Synchronous Transmission?

In Synchronous Transmission, data is sent in the form of blocks or

frames. This transmission is the full-duplex type. Between sender and
receiver, synchronization is compulsory. In Synchronous transmission,
There is no time gap present between data. It is more efficient and more
reliable than asynchronous transmission to transfer a large amount of
data.
Both the sender and receiver are synchronized with a common clock
signal. This means they operate at the same speed and know exactly
when to send and receive data. Data is sent in a continuous stream, with
each byte or chunk of data following the previous one without any gaps.
It’s efficient for sending large amounts of data quickly because there’s
less overhead (extra bits) needed to start and stop the transmission.

Example:
Chat Rooms
Telephonic Conversations
Video Conferencing

What is Asynchronous Transmission?

In Asynchronous Transmission, data is sent in form of byte or character.
This transmission is the half-duplex type transmission. In this
transmission start bits and stop bits are added with data. It does not
require synchronization. Asynchronous transmission is like sending
individual text messages without knowing exactly when the other person
will read them.
The sender and receiver do not share a common clock signal. Instead,
data is sent one byte or character at a time, with start and stop bits
indicating the beginning and end of each byte. Each piece of data is sent
independently, with gaps in between, allowing the receiver to process
each byte as it arrives. It’s flexible and simpler to implement, especially
useful for communications where data is sent intermittently.

Example:
Email
Forums
Letters

Difference Between Synchronous and Asynchronous

Transmission

Synchronous Transmission Asynchronous Transmission

In Synchronous transmission, data is In Asynchronous transmission, data is

sent in form of blocks or frames. sent in form of bytes or characters.

Synchronous transmission is fast. Asynchronous transmission is slow.

Asynchronous transmission is
Synchronous transmission is costly.
economical.
Synchronous Transmission Asynchronous Transmission

In Asynchronous transmission, the time

In Synchronous transmission, the time
interval of transmission is not constant,
interval of transmission is constant.
it is random.

In this transmission, users have to

Here, users do not have to wait for the
wait till the transmission is complete
completion of transmission in order to
before getting a response back from
get a response from the server.
the server.

In Synchronous transmission, there is In Asynchronous transmission, there is

no gap present between data. a gap present between data.

While in Asynchronous transmission,

Efficient use of transmission lines is
the transmission line remains empty
done in synchronous transmission.
during a gap in character transmission.

The start and stop bits are used in

The start and stop bits are not used in
transmitting data that imposes extra
transmitting data.
overhead.

Asynchronous transmission does not

Synchronous transmission needs
need synchronized clocks as parity bit
precisely synchronized clocks for the
is used in this transmission for
information of new bytes.
information of new bytes.

Errors are detected and corrected in Errors are detected and corrected when
real time. the data is received.

High latency due to processing time

Low latency due to real-time
and waiting for data to become
communication.
available.

Examples: Telephonic conversations, Examples: Email, File transfer,Online

Video conferencing, Online gaming. forms.
8051 UART
Introduction

8051 UART Serial vs Parallel Communication

Serial communication means to transfer data bit by bit serially at a time, whereas in
parallel communication, the number of bits that can be transferred at a time
depends upon the number of data lines available for communication.

Two methods of serial communication are

• Synchronous Communication: Transfer of bulk data in the framed structure at

a time
• Asynchronous Communication: Transfer of a byte data in the framed
structure at a time

8051 has built-in UART with RXD (serial data receive pin) and TXD (serial data
transmit pin) on PORT3.0 and PORT3.1 respectively.
Asynchronous communication
Asynchronous serial communication is widely used for byte-oriented transmission.

Frame structure in Asynchronous communication:

• START bit: It is a bit with which serial communication starts and it is always
low.
• Data bits packet: Data bits can be 5 to 9 bits packet. Normally we use 8 data
bit packet, which is always sent after the START bit.
• STOP bit: This is one or two bits. It is sent after the data bits packet to
indicate the end of the frame. The stop bit is always logic high.

In an asynchronous serial communication frame, the first START bit followed by the
data byte and at last STOP bit forms a 10-bit frame. Sometimes the last bit is also
used as a parity bit.

8051 Serial Frame Structure

Data transmission rate

The data transmission rate is measured in bits per second (bps). In the binary
system, it is also called a baud rate (number of signal changes per second).
Standard baud rates supported are 1200, 2400, 4800, 19200, 38400, 57600, and
115200. Normally most of the time 9600 bps is used when speed is not a big issue.

Interface standard

• 8051 serial communication has TTL voltage level which are 0 v for logic 0 and
5 v for logic 1.
• In computers and most of the old devices for serial communication, RS232
protocol with DB9 connector is used. RS232 serial communication has
different voltage levels than 8051 serial communication. i.e. +3 v to +25 v for
logic zero and -3 v to -25 v for logic 1.
 • So to communicate with RS232 protocol, we need to use a voltage level
converter like MAX232 IC.
• Although there are 9 pins in the DB9 connector, we don’t need to use all the
pins. Only 2nd Tx(Transmit), 3rd Rx(Receive), and 5th GND pin need to be
connected.

8051 Serial Interface Diagram

MAX232 interfacing With 8051 MCU

8051 UART Programming
Baud Rate calculation:

• To meet the standard baud rates generally crystal with 11.0592 MHz is used.
• As we know, 8051 divides crystal frequency by 12 to get a machine cycle
frequency of 921.6 kHz.
• The internal UART block of 8051 divides this machine cycle frequency by 32,
which gives the frequency of 28800 Hz which is used by UART.
• To achieve a baud rate of 9600, again 28800 Hz frequency should be divided
by 3.
• This is achieved by using Timer1 in mode-2 (auto-reload mode) by putting 253
in TH1 (8-bit reg.)
• So 28800 Hz will get divided by 3 as the timer will overflow after every 3
cycles.
• we can achieve different baud rates by putting the division factor in the TH1
register.

8051 Microcontroller Baud Rate calculation

Division factor to achieve different baud rates

Baud Rate TH1 (Hex)

9600 FD

4800 FA

2400 F4

1200 E8
8051 Serial communication Registers
SBUF: Serial Buffer Register

This is the serial communication data register used to transmit or receive data
through it.

SCON: Serial Control Register

Serial control register SCON is used to set serial communication operation modes.
Also it is used to control transmit and receive operations.

Bit 7:6 - SM0:SM1: Serial Mode Specifier

Mode SM0 SM1 Mode

0 0 0 1/12 of Osc frequency shift register mode fixed baud rate

1 0 1 8-bit UART with timer 1 determined baud rate

2 1 0 9-bit UART with 1/32 of Osc fixed baud rate

3 1 1 9-bit UART with timer 1 determined baud rate

Normally mode-1 (SM0 =0, SM1=1) is used with 8 data bits, 1 start bit, and 1 stop bit.

Bit 5 - SM2: for Multiprocessor Communication

This bit enables a multiprocessor communication feature in mode 2 & 3.

Bit 4 - REN: Receive Enable

1 = Receive enable

0 = Receive disable

Bit 3 - TB8: 9th Transmit Bit

 This is the 9th bit which is to be transmitted in mode 2 & 3 (9-bit mode)

Bit 2 - RB8: 9th Receive Bit

This is the 9th received bit in mode 2 & 3 (9-bit mode), whereas in mode 1 if SM2 = 0
then RB8 hold the stop bit that received

Bit 1 - TI: Transmit Interrupt Flag

This bit indicates the transmission is complete and gets set after transmitting the
byte from the buffer. Normally TI (Transmit Interrupt Flag) is set by hardware at the
end of the 8th bit in mode 0 and at the beginning of stop bit in other modes.

Bit 0 – RI: Receive Interrupt Flag

This bit indicates reception is complete and gets set after receiving the complete
byte in the buffer. Normally RI (Receive Interrupt Flag) is set by hardware in receiving
mode at the end of the 8th bit in mode 0 and at the stop bit receive time in other
modes.

8051 Microcontroller Programming steps

1. Configure Timer 1 in auto-reload mode.
2. Load TH1 with value as per required baud rate e.g. for 9600 baud rate load
0xFD. (-3 in decimal)
3. Load SCON with serial mode and control bits. e.g. for mode 1 and enable
reception, load 0x50.
4. Start timer1 by setting TR1 bit to 1.
5. Load transmitting data in the SBUF register.
6. Wait until loaded data is completely transmitted by polling the TI flag.
7. When the TI flag is set, clear it, and repeat from step 5 to transmit more data.

Example

Let's Program 8051 (here AT89C51) to send character data “test” serially at 9600
baud rate in mode 1

8051 Serial Program for serial data transmit

/*

* 8051_Serial_UART

* http://www.electronicwings.com
*/

#include <reg51.h> /* Include x51 header file */

void UART_Init()
{

TMOD = 0x20; /* Timer 1, 8-bit auto reload mode */

TH1 = 0xFD; /* Load value for 9600 baud rate */
SCON = 0x50; /* Mode 1, reception enable */
TR1 = 1; /* Start timer 1 */
}

void Transmit_data(char tx_data)

{

SBUF = tx_data; /* Load char in SBUF register */

while (TI==0); /* Wait until stop bit transmit */
TI = 0; /* Clear TI flag */
}

void String(char *str)

{

int i;
for(i=0;str[i]!=0;i++) /* Send each char of string till the NULL */
{

Transmit_data(str[i]); /* Call transmit data function */

}
}

void main()
{

UART_Init(); /* UART initialize function */

String("test"); /* Transmit 'test' */
while(1);
}

8051 Serial Interrupt

8051 UART has a serial interrupt. Whenever data is transmitted or received, serial
interrupt flags TI and RI are activated respectively.

8051 serial interrupt has a vector address (0023H) where it can jump to serve ISR
(Interrupt service routine) if the global and serial interrupt is enabled.

Let's see how the serial interrupt routine will be used in serial communication
programming.

Programming steps

1. Set timer 1 in auto-reload mode.

2. Load TH1 with value as per required baud rate e.g. for 9600 baud rate load
0xFD.
3. Load SCON with serial mode and control bits. e.g. for mode 1 and enable
reception load 0x50.
4. Start timer1 by setting TR1 bit to 1.
5. Enable Global and serial interrupt bit, i.e. EA = 1 and ES = 1.
6. Now whenever data is received or transmitted, the interrupt flag will set and
the controller will jump to serial ISR.
7. Note that, TI/RI flag must be cleared by software in ISR.

Note: For transmission and reception interrupt, the same interrupt vector address is
assigned, so when the controller jumps to the ISR, we have to check whether it is Tx
interrupt or Rx interrupt by TI and RI bits status.
 High-Level Data Link Control (HDLC)

High-level Data Link Control (HDLC) is a group of communication protocols of the data link
layer for transmitting data between network points or nodes. Since it is a data link protocol,
data is organized into frames. A frame is transmitted via the network to the destination that
verifies its successful arrival. It is a bit - oriented protocol that is applicable for both point -
to - point and multipoint communications.

Transfer Modes
HDLC supports two types of transfer modes, normal response mode and asynchronous
balanced mode.
• Normal Response Mode (NRM) − Here, two types of stations are there, a primary
station that send commands and secondary station that can respond to received
commands. It is used for both point - to - point and multipoint communications.

• Asynchronous Balanced Mode (ABM) − Here, the configuration is balanced, i.e. each
station can both send commands and respond to commands. It is used for only point
- to - point communications.
HDLC Frame
HDLC is a bit - oriented protocol where each frame contains up to six fields.
The structure varies according to the type of frame. The fields of a HDLC frame
are −
• Flag − It is an 8-bit sequence that marks the beginning and the end of the frame. The
bit pattern of the flag is 01111110.
• Address − It contains the address of the receiver. If the frame is sent by the primary
station, it contains the address(es) of the secondary station(s). If it is sent by the
secondary station, it contains the address of the primary station. The address field
may be from 1 byte to several bytes.
• Control − It is 1 or 2 bytes containing flow and error control information.
• Payload − This carries the data from the network layer. Its length may vary from one
network to another.
• FCS − It is a 2 byte or 4 bytes frame check sequence for error detection. The standard
code used is CRC (cyclic redundancy code)

Explore our latest online courses and learn new skills at your own pace. Enroll and become
a certified expert to boost your career.
Types of HDLC Frames
There are three types of HDLC frames. The type of frame is determined by the
control field of the frame −
• I-frame − I-frames or Information frames carry user data from the network layer.
They also include flow and error control information that is piggybacked on user data.
The first bit of control field of I-frame is 0.
• S-frame − S-frames or Supervisory frames do not contain information field. They are
used for flow and error control when piggybacking is not required. The first two bits
of control field of S-frame is 10.
• U-frame − U-frames or Un-numbered frames are used for myriad miscellaneous
functions, like link management. It may contain an information field, if required. The
first two bits of control field of U-frame is 11.

PARALLEL PORT DEVICES

https://www.dauniv.ac.in/public/frontassets/coursematerial/embeddedsystems/Chap_5L0
6Emsys3EPArallelPortDevices.pdf
8051 Connections to RS-232
https://youtu.be/-UXpfAggE5Q?si=sG0DGeITx6oF8xB0

8051 intra-inter process communication and synchronization of

processes using on-chip timers/counters

https://youtube.com/playlist?list=PLgwJf8NK-
2e7K1ld0H8O_OEyPvjSd6uxx&si=T8vA6xQr0OMuEBln

OR

8051 Timers and Counters

Copied from https://www.geeksforgeeks.org/8051-timers-and-counters/

8051 microcontrollers are mainly used to speed up our tasks because

they are very easy to use and they are also fast to complete tasks easily.
These microcontrollers have one main feature which is Timers and
counters. This feature is widely used in microcontrollers to measure the
time and as well as to count the events or tasks. By learning about these
timers and counters ,we can make good embedded systems. In this article
let us see how these counters and timers work in microcontrollers.
Table of Content
• 8051 Timers and Counters
• Types
• What is Timer 0 (T0) ?
• What is Timer 1 (T1) ?
• TCON and TMOD
• Timer Counter Modes
• What is Counter Mode ?

8051 Timers and Counters

Timers and counters are one of the best feature that is provided
by microcontrollers. Timers are used to measure the time and for creating
time delays . Counters are used to count the events or tasks that are taking
place outside the microcontrollers. We can setup these timers and
counters with the microcontrollers to make our tasks in different ways to
fit in different tasks.

Types of 8051 Timers and Counters

The 8051 microcontroller mainly has two timers they are Timer
0 and Timer 1. These are used as both timers as well as counters. They
are 16-bit long but the format of the microcontroller is 8-bit, due to that
the Timers or counters are divided into two 8-bit parts a low byte and
a high byte. Let’s see one by one,

What is Timer 0 (T0) ?

Timer 0 is one of the main timers/counters in the 8051 microcontroller,
used for doing timing operations and counting events. It is divided into two
8-bit registers they are TL0 (Timer 0 Low byte) and TH0 (Timer 0 High
byte). By combining both, these form a 16-bit timer/counter.
TL0 (Timer 0 Low Byte)
• TL0 is the lower 8-bit register of Timer 0.
• It stores the lower byte of the count value.
• When timer 0 functions as a 16-bit timer, TL0 increases first,
and TH0 increases by one following an overflow (when 255 is
achieved).
TH0 (Timer 0 High Byte)
• TH0 is the upper 8-bit register of Timer 0.
• It stores the higher byte of the count value.
• When TL0 overflows, Timer 0 can count up to 65,535 (FFFFH)
before spilling since TH0 is increased.
Structure of Timer 0
Given below is the Structure of Timer 0.
Timer0
What is Timer 1 (T1) ?
Timer 1 is also one of the main timers/counters in the 8051
microcontroller, used for doing timing operations and counting events. It is
also divided into two 8-bit registers they are TL1 (Timer 1 Low
byte) and TH1 (Timer 1 High byte). By combining both, these form a 16-
bit timer/counter
TL1 (Timer 1 Low Byte)
• Timer 1's bottom 8-bit register is designated as TL1.
• It contains the count value's bottom byte.
• When using a 16-bit timer, TL1 increases first and then TH1 by
1 once TL1 reaches its maximum value of 255.
TH1 (Timer 1 High Byte)
• Timer 1's upper 8-bit register is designated as TH1.
• It contains the count value's higher byte.
• When TL1 overflows, TH1 increments, allowing Timer 1 to
count up to 65,535 (FFFFH) before overflowing.
Structure of Timer 1
Given below is the Structure of Timer 1.
Timer1

Timer Control Registers-TCON and TMOD

TCON and TMOD are the special function registers in the 8051
microcontroller. These are used to control the timers and counters.
1. TCON (Timer Control Register): The timers' start and stop are
aided by this register. It additionally indicates whether the timer
is done counting.
2. TMOD (Timer Mode Register): The timers' mode is adjusted
using this register. It selects whether the timers will record
events occurring outside of the microcontroller or record time.
So, to make the timers and counters work, you need to set up TCON and
TMOD properly. In this way, you can use the timers to measure time or
count events, depending on what you need for your task. Let's we see one
by one,
TCON (Timer Control Register)
The 8051 microcontroller has a unique function register called the TCON
(Timer Control Register). In order to provide precise output, timers and
counters are controlled by it. The data in the registers may overflow if
these timers and counters are not under control. Thus, the TCON is utilized
to control the timers and counters. The structure in detail is displayed
below.
Structure of TCON
The TCON register is an 8-bit register, where each bit has a specific
function:

TCON

Here's what each bit represents:

Bit Bit Name Description

TF1 (Timer 1
7 Set to 1 when Timer 1 overflows else 0.
Overflow Flag)

TR1 (Timer 1 Run Set to 1 to start Timer 1, and set to 0 to stop Timer
6
Control Bit) 1.

TF0 (Timer 0
5 Set to 1 when Timer 0 overflows else 0.
Overflow Flag)

TR0 (Timer 0 Run Set to 1 to start Timer 0, and set to 0 to stop Timer
4
Control Bit) 0.
Bit Bit Name Description

IE1 (Interrupt 1 Set to 1 when an external interrupt 1 occurs else

3
Edge Flag) 0.

IT1 (Interrupt 1 Set to 1 to configure external interrupt 1 as edge-

2
Type Control Bit) triggered, and set to 0 for level-triggered.

IE0 (Interrupt 0 Set to 1 when an external interrupt 0 occurs else

1
Edge Flag) 0.

IT0 (Interrupt 0 Set to 1 to configure external interrupt 0 as edge-

0
Type Control Bit) triggered, and set to 0 for level-triggered.

TMOD (Timer Mode Register)

The TMOD (Timer Mode Register) is a special function register in the
8051 microcontroller. Timer 0 and Timer 1 are the modes of operation
that it is utilized to set. Whether a timer or counter needs to be set, it is
done so using this register. The structure in detail is displayed below.
Structure of TMOD Register
The eight bits of the TMOD register are split into two sections: Timer 0 is
controlled by the lower four bits, and Timer 1 is controlled by the upper
four bits. Similar bit fields in each component set the timers' mode and
behavior.
TMOD

Here's what each bit represents:

Bit Bit Name Description

7 or 3 Gate (0 or 1) Gate Control Bit

6 or 2 C/Tx Counter/Timer Select Bit

5 or 1 TxM1 Timer Select Bits for Mode1

4 or 0 TxM0 Timer Select Bits for Mode0

Let's see each bit's one by one,

1. GATE (Gate Control Bit): When set to 1, the timer/counter is
enabled only while the INT pin is high and TR control bit is set.
When cleared to 0, the timer is enabled whenever the TR
control bit is set.
2. C/T (Counter/Timer Select Bit): When set to 1, the timer
operates as a counter (counts external events). When cleared to
0, it operates as a timer (measuring time).
3. M1 and M0 (Mode Select Bits):
M0 M1 Mode Description

0 0 Mode 0 13-bit Timer mode (8 Bit of THx and 5 Bit of TLx).

0 1 Mode 1 16-bit Timer mode.

8-bit Auto-reload mode (TLx reload with the THx

1 0 Mode 2
value each time when TLx overflows).

Split Timer mode - Split 16 bit timer into two 8 bit

1 1 Mode 3
timers(THx and TLx).

Timer Counter Modes

The modes are divided into four as shown below.

Timer Counter Modes

What is Timer Mode ?

The Modes which are used to create time delays , measure time intervals,
or generate precise time-based signals are known as Timer modes. The
modes that acts as timers are given below,
Timer Modes
Mode 0: 13-bit Timer Mode
• Description: In Mode 0, 0 or 1 timer functions as a 13-bit timer.
It counts from 0 to 8191 counts, or from 0000H to 1FFFH. It
 makes use of all eight bits of TH0 or TH1, and five bits of TL0 or
TL1.
• Working Principle: TLx counts in steps of 0 to 31, resets to 0,
and then increases THx. Out of the two timer bytes, only 13 bits
are used.
• Usage: Because of the narrow count range of 8192 values, it is
rarely utilized.
• Example: It is used for Generating Short Delays
The Block Diagram for Mode 0 is shown below.

Mode 0

Mode 1: 16-bit Timer Mode

• Description: Timer 0 and Timer 1 are set up as 16-bit timers in
Mode 1. They use the 0000H to FFFFH count range (0 to
65535).
• Working Principle: TLx uses all 16 bits to count from 0 to 255,
resets to 0, and then increases THx.
• Usage: Because of its larger range of values, it is frequently
utilized for a variety of timing jobs.
• Example: It is used for Timing Events or
Generating PWM Signals.
The Block Diagram for Mode 1 is shown below.
Mode 1

What is Counter Mode ?

The Modes which are used to count the number of events or pulses that
are happening outside the microcontroller are known as Counter
modes. The modes that acts as counters are given below,

Counter Modes
Mode 2: 8-bit Auto-Reload Mode
• Description: The configuration of Timer 0 in Mode 2 is an 8-bit
auto-reload timer. It counts from 00H to FFH (0 to 255) and
then loads the starting value automatically.
• Working Principle: TLx starts at 0 and increases to 255, but
instead of returning to 0, it reloads with the value from THx.
• Usage: Good for jobs like setting baud rates, when the timer
needs to continuously reload with a set value.
• Example: Used for Frequency Measurement.
The Block Diagram for Mode 2 is shown below.
Mode 2

Mode 3: Split Timer Mode

• Description: Timer 0 is divided into two 8-bit timers in Mode 3,
which enables Timer 0 to function as two independent timers
while Timer 1 continues to function as a 16-bit timer as usual.
• Working Principle: Both timers separately count from 0 to 255,
then overflow back to 0. The control bits of Timer 1 are
connected to TH0.
• Usage: helpful when two independent timers are required.
• Example: Used in Real-time Clock with Alarm Functionality.
The Block Diagram for Mode 3 is shown below.

Mode 3
Conclusion
In order to create time delays, measure time intervals, and count
events in embedded systems, 8051 timers and counters are necessary
components. To fully utilize them in a variety of applications, it is crucial
to comprehend how they operate and are configured.

Microcontrollers - 8051 Interrupts

8051 Microcontroller is a widely used embedded system, that

incorporates a robust interrupt system which are important for external
communications and real-time applications. Interrupts are the important
feature of a microcontroller which enables the microcontroller to respond
to the external events and requests, which enhances the multitasking
abilities of the microcontroller. An interrupt is an external or internal
event/command that interrupts the normal processing of an event and
informs the microcontroller that a device needs its service. Whenever a
device needs its service, the device sends an interrupt signal to the
microcontroller to send a notification. Upon receiving the interrupt signal,
the microcontroller stops its existing program and serves the external
device request. The program which is associated with the interrupt is
known as interrupt Service Routine (IRS) or interrupt handler.

The 8051 features two main types of interrupts, i.e. Hardware interrupts
and software interrupts. The hardware interrupts are triggered by external
signal such as peripheral events or external devices. The microcontroller
can be configured to respond to specific events, allowing for efficient
event-driven programming. Whereas, the Software interrupts, are initiated
by specific instructions in the program code. They provide a mechanism for
the programmer to force the microcontroller to interrupt its normal
execution and execute a predefined routine.

The address of the corresponding interrupt service routine (ISR) is included

in the suitable interrupt vector associated with every interrupt source in
the 8051. The microcontroller automatically maintains its state on
interrupt, fetches the interrupt vector's ISR address, and executes the ISR's
operation. Once the ISR is finished, the microcontroller restarts the task
which has been interrupted.
Table of Content
• 8051 Microcontroller
• 8051 Microcontroller Interrupt
• Types of Interrupts
• Interrupt Vector Table
• Applications
• Solved Examples
• Advantages
• Disadvantages
What is an 8051 Microcontroller?
8051 microcontroller is an 8-bit data bus and 16-bit address bus
Microcontroller. A 64K (216) byte code memory space and an additional
64K byte data memory space can be addressed using the 16-bit address
bus. It has 40 pins and 4K on-chip read only code memory and 128 bytes
of internal RAM. It also has various Special Function Registers (SFR) such
as the accumulator, the B register, and many other control registers. At a
time, the ALU executes an 8-bit operation. It also has two 16-bit counter
timers and 3 internal interrupts and 2 external interrupts and four 8 bit I/O
ports.

8051 Microcontroller Interrupt

The timer and serial interrupts are internally generated by the
microcontroller whereas, the external interrupts are generated by
additional peripheral devices or switches that are connected to
the microcontroller externally. There are two types of external interrupts:
edge-triggered and level-triggered. The interrupt service routine is
carried out by the microcontroller as a reaction to an interrupt, enabling
memory locations to coincide with interrupts.

Interrupt structure of 8051 Microcontroller

All of the interrupts are disabled by "RESET" thus software is required to
enable all of these interrupts. If any one of these five interrupts or all five
are activated, the relevant interrupt flags are set. The priority, which is
managed by the IP interrupt priority register, determines which of these
interrupts can be set or cleared bit by bit in a specific function register that
is Interrupt Enabled (IE).
Interrupt handle flowchart.

Two SFRs controls the function of interrupts in 8051 microcontrollers. IE

is Responsible for disable/enable the function and IP is Responsible for
priority assignment: The priority list offers 3 levels of interrupt priority:
Reset: When a reset request arrives, everything is stopped and the
microcontroller restarts. Reset can be used to disable the interrupt priority
1. Interrupt priority 0 can be disabled by both Reset and interrupt.
Some of the registers used in this microcontroller are :
• IE (Interrupt Enable) Register
• IP (Interrupt Priority) Register
• TCON (Timer Control) Register
IE (Interrupt Enable) Register
Interrupts can be enabled and disabled using IE Register. It is a register in
the 8051 microcontroller that controls interrupt prioritization and
triggering. It includes many bits, such as:

EA-Global Interrupt Enable/Disable - When it is set it enables all

interrupt, if cleared disables all interrupts
• 0- Disables all interrupt requests
• 1- Enables all interrupt requests
ES (Serial Communication Interrupt Enable)- This bit enables or disables
the interrupt for serial communication.
• 1- Interrupt is enabled by UART system
• 0-Interrupt cannot be generated by UART system
ET0- Bit enables or disables timer 0 interrupt.
• 1-Timer 0 is enables an interrupt
• 0-Interrupt cannot be generated by the timer 0
ET1- Bit enables or disables timer 1 interrupt.
• 1- Interrupt is enabled by timer 1
• 0-Interrupt is disabled by timer 1
EX0 and EX1 (External Interrupt 0 and External Interrupt 1 Enable)
• These bits control the interrupts from external devices.
• EX0 - bit enables or disables external 0 interrupt: 0 - change of
the INT1 pin logic state cannot generate an interrupt and 1 -
enables an external interrupt on the pin INT1 state change.
• EX1 - bit enables or disables external 1 interrupt: 0 - change of
the pin INT0 logic state cannot generate an interrupt and 1 -
enables an external interrupt on the pin INT0 state change.
IT0 and IT1 (External Interrupt 0 and External Interrupt 1 Type)- These
bits determine the type of trigger for external interrupts (level or edge-
triggered).

IE (Interrupt Enable) Register

IP (Interrupt Priority) Register
One cannot predict when one may receive an interrupt request. If multiple
interrupts are enabled, it can happen that a request for another interrupt
is made while the first one is ongoing. There is a priority list that tells the
microcontroller what to do in order to determine whether to respond to a
new interrupt request or to carry on with existing operations. The
microcontroller restarts once everything stops in response to a reset
request. Only Reset has the ability to disable Interrupt priority 1. Both
Reset and interrupt priority 1 have the ability to disable interrupt priority
0. The interrupt priority register, or IP Register, indicates which of the
current interrupt sources is more significant than other. The program's
start typically defines the interrupt priority. An interrupt will be
immediately paused and given preference over any other interrupt if the
one with greater priority comes while the other is still in progress.
Whenever two interrupt requests that have different priorities
occurs simultaneously, the higher priority interrupt is handled first. If two
interrupt requests with the same priority level arise one after the other, the
subsequent request needs to wait until the entire process is accomplished.
Bit0 (PX0)- External0 interrupt priority bit
• 0- Sets low priority to external 0 interrupt
• 1- Sets high priority to external 0 interrupt
Bit1 (PT0)- Timer 0 interrupt priority bit
• 0- Assigns low priority to Timer0 interrupt
• 1- Assigns high priority to Timer0 interrupt
Bit2 (PX1)- External1 interrupt priority bit
• 0- Sets low priority to external1 interrupt
• 1- Sets high priority to external1 interrupt
Bit3 (PT1)- Timer1 interrupt priority bit
• 0- Sets low priority to timer1 interrupt
• 1- Sets high priority to timer1 interrupt
Bit4 (PS)- Serial Input priority bit
• 0- Assigns low priority to serial interrupt
• 1- Assigns high priority to serial interrupt
Bit 5,6 & 7- These bits are called as the Reserved bits.
IP (Interrupt Priority) Register

TCON (Timer Control) Register

The interruptions that the microcontroller interfaces with (external)
devices are known as external interrupts. They are received by the
controller's INTx pins. These may be triggered by edges or levels. Interrupt
is enabled for a low at the INTx pin when it is level triggered, and for a
high to low transition at the INTx pin when it is edge triggered. The TCON
register determines whether the triggering is edge or level trigger. The
INTx pin for a level trigger interrupt needs to remain low until the interrupt
begins and needs to go back to high prior to the interrupt terminating. An
interrupt won't be produced if the low at the INTx pin rises to a high value
before the ISR begins. Additionally, the interrupt will be created once more
if the INTx pin is low even after the ISR has ended. The level trigger
interrupt (low) at the INTx pin must therefore be four machine cycles long,
neither longer nor shorter than this.
• IE0- External interrupt 0 edge flag- When an external interrupt
edge is detected, hardware sets it. Cleared by the device upon
processing the interrupt.
• IE1- External interrupt 1 edge flag-Set by hardware when
external interrupt edge is detected. Cleared by hardware when
the interrupt is processed.
• TF0- Timer 0 overflow flag-This bit is set whenever timer 0
overflows and is processed by the hardware.
• TF1- Timer 1 overflow flag - This bit is set whenever timer 1
overflows and is processed by the hardware.
 • TR0- Timer 0 Run Control- Set this bit to start Timer 0 and
clear it to stop the timer. This is important because the timer
needs to be running for it to generate interrupts.
• TR1 Timer 1 Run Control - Similar to TR0, this bit controls the
running state of Timer 1.
• IT0- Interrupt 0 type control bit- Set/cleared by the device or
software to indicate falling edge/low-level triggered external
interrupts.
• IT1- Interrupt 1 type control bit- Set/cleared by the device or
software to indicate falling edge/low-level triggered external
interrupts. Whenever the IT0 and IT1 bits are set, the
external interrupts 0 and 1 edge-triggered respectively. These
bits are cleared by default, which causes the external interrupt
to be level triggered.

TCON (TIMER CONTROL) REGISTER

Types of 8051 Microcontroller Interrupts

8051 Microcontroller suffers five different types of interrupts that hampers
the main program execution. These five types of interrupts are:
• Timer 0 overflow interrupt- TF0
• Timer 1 overflow interrupt-TF1
• External hardware interrupt- INT0
• External hardware interrupt- INT1
• Serial communication interrupt- RI/TI
External Hardware Interrupt- (INT0 & INT1)
The 8051 microcontrollers are able to respond to external events through
its external interrupts, INT0 and INT1.
External Interrupt 0 (INT0)
• It is connected to the 8051's pin PORT3.2.
 • An interrupt request is issued when this pin transitions from low
to high in response to an external signal.
• It is possible to program the microcontroller to carry out a
particular Interrupt Service Routine (ISR) in response to this
interrupt.
• Set the IE (Interrupt Enable) bit for INT0 in the TCON register
and configure the IT0 (Interrupt Type 0) bit in the TCON register
corresponding to the desired triggering condition (edge or level-
triggered) in order to enable and configure INT0.
External Interrupt 1 (INT1)
• It is connected to the 8051's pin PORT3.3
• When that particular pin encounters a low-to-high transitions,
INT1, like INT0, creates an interrupt request.
• By configuring the IT1 (Interrupt Type 1) bit in the TCON
register and setting the IE bit for INT1 in the TCON register,
one can enable and configure INT1.
• A specific ISR can be executed by the microcontroller in
response to INT1.
Timer Interrupts (Timer0 and Timer1)
Timer 0 and Timer 1 are hardware timers with internal timer interrupts
featured in the 8051 microcontrollers. In microcontroller applications,
these timers are used to measure time intervals and generate precise
delays. The interrupt system of the microcontroller enables it to react
quickly to outside events. Interrupts for Timer 0 and Timer 1 are produced
when their respective timers exceed their limit. The microcontroller will
run the interrupt service routine (ISR) for that timer if the related interrupt
is enabled, and the associated interrupt flag is set upon overflow.
Timer0 Interrupt
• Since Timer 0 is an 8-bit timer, its count range is 0 to 255.
• There are two modes of operation for it, 13-bit and 16-bit. It
employs the TH0 (Timer 0 High) and TL0 (Timer 0 Low)
registers in 13-bit mode and only the TH0 register in 16-bit
mode.
• It is possible to set timer 0 to interrupt when it approaches zero
instead of staying at its maximum value. The microcontroller can
perform a particular interrupt service routine (ISR) in response to
the interrupt request that this overflow generates.
Timer1 Interrupt
• Timer 1 is a 16-bit timer with a counting range of 0 to 65,535.
• It can operate in 16- or 8-bit mode. It employs the TL1 (Timer 1
Low) and TH1 (Timer 1 High) registers in 8-bit mode and only
the TH1 register in 16-bit mode.
• Timer 1 can be set up to produce an interrupt when it overflows,
just like Timer 0. This interruption may cause a certain ISR to be
executed.
Serial Communication Interrupts (UART)
UART (Universal Asynchronous Receiver/Transmitter) is a serial
communication protocol used with 8051 microcontrollers. Data is sent
over a single cable, bit by bit, in serial transmission. In this sense,
"interrupts" refers to the processes that enable the microcontroller to react
quickly to external events.
Addressing UART communication with the 8051's interrupts:
• Initialization of UART- Set the data format, baud rate, and
enable the UART module by configuring the UART registers.
• Interrupt Enable- Depending on the operation you wish to
interrupt for, enable the UART's transmit interrupt (TI) or receive
interrupt (RI).
• ISR (interrupt service routine)- To handle the interrupt, write
an ISR. The ISR in UART communication normally verifies
whether the transmit buffer is ready (TI) or whether data has
been received (RI).
• Clearing the Flag- To recognize the interrupt and get ready for
the next one, in the ISR, clear the associated interrupt flag (RI or
TI).
Interrupt Vector Table
The addresses of different interrupt service routines (ISRs) are stored in a
table called the Interrupt Vector Table (IVT) in an 8051 microcontroller. It
is a vital aspect of the interrupt handling mechanism in the microcontroller.
When an interrupt occurs the interrupt specific ISR is executed by jumping
the program counter to the corresponding address in the IVT. There are
memory areas set aside specifically for the IVT in the
8051 microprocessors. Every interrupt has a specific place in the IVT, and
the addresses kept there point to the program memory's associated ISR's
start. By guiding the program flow to the proper place, the IVT enables the
microcontroller to respond to external events like hardware interrupts or
external signals quickly and effectively.
Interrupt Vector
Interrupt Flag Address

Reset - 0000H

INT0 (External
IE0 0003H
Interrupt 0)

Timer0 TF0 000BH

INT1 (External
IE1 0013H
Interrupt 1)

Timer 1 TF1 001BH

Serial Interrupt TI/RI 0023H

Applications of 8051 Interrupts

• In real-time systems, interrupts are essential for speedy
responses to external occurrences. Due to its ability to swap
tasks fast through interrupts, the 8051 is a good choice for
applications that need exact timing.
• Interrupts serve in the control of incoming data in
communication applications, assuring timely transmission or
rapid handling of received information.
• In embedded systems, 8051 interrupts are frequently utilized for
activities like sensor interfacing, where the microcontroller must
react quickly to environmental changes.
• Interruptions assist in ensuring timely data sampling and
processing in situations when data must be obtained
from sensors or external devices.
• By enabling instantaneous reactions to sensor triggers or alarm
situations, interrupts in security systems can ensure prompt
alerting and suitable responses.
Solved Examples on 8051 Microcontroller Interrupts
1. Write an 8051 program to enable external interrupts’0’ and ‘1’,
configure it to receive edge triggered interrupt request and keep
waiting for the interrupt.
ORG 0x00; Start of program memory
MOV P1, #00H; Initialize Port 1
MOV IE, #10001011B; Enable external interrupts (EX0 and EX1)
MOV IT0, #0; Configure INT0 for edge-triggered interrupt
MOV IT1, #0; Configure INT1 for edge-triggered interrupt
MAIN:
NOP; No operation, just wait for interrupts
SJMP MAIN; Jump back to main loop
ORG 0x03; Interrupt Vector for External Interrupt 0 (INT0)
INT0_ISR:
; Your interrupt service routine code for INT0 here
RETI; Return from interrupt
ORG 0x0B; Interrupt Vector for External Interrupt 1 (INT1)
INT1_ISR:
; Your interrupt service routine code for INT1 here
RETI; Return from interrupt

SERIAL COMMMUNICATION

Refer this
https://www.codrey.com/embedded-systems/serial-communication-basics/

"Serial communication" in its most simple form means that data bits travel through a single line,
one by one like ducks in a row. In contrast, in parallel communication you'd have multiple lines
and the transferred bits are evenly distributed over the lines. You may want to picture a street
with one lane vs. a street with many lanes.One might think that parallel is better because you
have more lanes to use. But this is not the case because the bits on the data lines need to be
synchronized. Picture a street with 8 lanes where cars are not allowed to overtake each other but
instead need to arrive at exactly the same time.

There are many different serial protocols for instance

• RS232 / RS485 / RS422

• CAN
• LIN
• SPI
 • I2C
• USB
• PCI Express
• Ethernet

UART is actually not a protocol but more a term for a piece of hardware capable of performing
simple protocols like RS232 or RS485

All these protocols are all standardized and they differ greatly in their scope and what they can
do. The most important features from an end-user point of view would be throughput (bits/sec)
and maximum cable length.

RS232 is one of the simplest protocols. It only describes how a single byte with 8 bits can be
transferred over a wire. Nothing more. RS232 is very primitive and can reach speeds up to
~1MBit/sec. Typical speed is slower, around 112KBit/sec.

On the other hand, we have complex protocols like USB3 or PCIExpress. They have many more
features such as:

• Auto detection of communication partners

• Auto negotiation of communication speed
• Combining data into packets
• Routing of packets through a network or tree of devices
• Directly accessing remote memory through data packets

Theses protocols are insanely powerful and fast. USB 3.x can reach up to 20 GBit/sec, USB 4.x up
to 40 GBit/sec. The protocols are very complex. I have a PCI Express book on my table and it has
around 1.300 pages

8255A - Programmable Peripheral Interface

The 8255A is a general purpose programmable I/O device designed to transfer the data
from I/O to interrupt I/O under certain conditions as required. It can be used with almost
any microprocessor.
It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured as per
the requirement.

Ports of 8255A

8255A has three ports, i.e., PORT A, PORT B, and PORT C.

• Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
• Port B is similar to PORT A.
• Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper
(PC7-PC4) by the control word.
These three ports are further divided into two groups, i.e. Group A includes PORT A and
upper PORT C. Group B includes PORT B and lower PORT C. These two groups can be
programmed in three different modes, i.e. the first mode is named as mode 0, the second
mode is named as Mode 1 and the third mode is named as Mode 2.

Operating Modes

8255A has three different operating modes −

Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C
as two 4-bit ports. Each port can be programmed in either input mode or
output mode where outputs are latched and inputs are not latched. Ports
do not have interrupt capability.

Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can
be configured as either input or output ports. Each port uses three lines
from port C as handshake signals. Inputs and outputs are latched.

Mode 2 − In this mode, Port A can be configured as the bidirectional port

and Port B either in Mode 0 or Mode 1. Port A uses five signals from Port
C as handshake signals for data transfer. The remaining three signals
from Port C can be used either as simple I/O or as handshake for port B.

Features of 8255A
• The prominent features of 8255A are as follows −
• It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
• Address/data bus must be externally demux'd.
• It is TTL compatible.
• It has improved DC driving capability.

8255 Architecture
The following figure shows the architecture of 8255A −
 8255A - Pin Description

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data
bus. Data is transmitted or received by the buffer as per the instructions by the CPU. Control
words and status information is also transferred using this bus.

Read/Write Control Logic

This block is responsible for controlling the internal/external transfer of data/control/status
word. It accepts the input from the CPU address and control buses, and in turn issues
command to both the control groups.

CS
It stands for Chip Select. A LOW on this input selects the chip and enables the
communication between the 8255A and the CPU. It is connected to the decoded address, and
A0 & A1 are connected to the microprocessor address lines.
Their result depends on the following conditions −
CS A1 A0 Result

0 0 0 PORT A

0 0 1 PORT B

0 1 0 PORT C

0 1 1 Control Register

1 X X No Selection

WR
It stands for write. This control signal enables the write operation. When this signal goes low,
the microprocessor writes into a selected I/O port or control register.

RESET
This is an active high signal. It clears the control register and sets all ports in the input mode.

RD
It stands for Read. This control signal enables the Read operation. When the signal is low, the
microprocessor reads the data from the selected I/O port of the 8255.

A0 and A1
These input signals work with RD, WR, and one of the control signal. Following is the table
showing their various signals with their result.
A1 A0 RD WR CS Result

Input Operation
0 0 0 1 0
PORT A → Data Bus

0 1 0 1 0 PORT B → Data Bus

 1 0 0 1 0 PORT C → Data Bus

Output Operation
0 0 1 0 0
Data Bus → PORT A

0 1 1 0 0 Data Bus → PORT A

1 0 1 0 0 Data Bus → PORT B

1 1 1 0 0 Data Bus → PORT D

Print Page

Programmable Interrupt Controller

Intel 8259 is a Programmable Interrupt Controller (PIC). There are 5

hardware interrupts and 2 hardware interrupts in Intel 8085 and Intel
8086 microprocessors respectively. But by connecting Intel 8259 with
these microprocessors, we can increase their interrupt handling
capability. Intel 8259 combines the multi-interrupt input sources into a
single interrupt output. Interfacing of single PIC provides 8 interrupts
inputs from IR0-IR7. For example, Interfacing of 8085 and 8259
increases the interrupt handling capability of 8085 microprocessor from
5 to 8 interrupt levels.
Features of Intel 8259 PIC are as follows:
1. Intel 8259 is designed for Intel 8085 and Intel 8086
microprocessor.
2. It can be programmed either in level triggered or in edge
triggered interrupt level.
3. We can mask individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt
level by cascading further 8259 PICs.
5. Clock cycle is not required.
Pin Diagram of 8259 – We can see through above diagram that there
are total 28 pins in Intel 8259 PIC where Vcc : 5V Power supply and Gnd
: ground. Other pins use are explained below. Block Diagram of 8259
PIC microprocessor –
The Block Diagram consists of 8 blocks which are – Data Bus Buffer,
Read/Write Logic, Cascade Buffer Comparator, Control Logic, Priority
Resolver and 3 registers- ISR, IRR, IMR.
1. Data bus buffer – This Block is used as a mediator between
8259 and 8085/8086 microprocessor by acting as a buffer. It
takes the control word from the 8085 (let say) microprocessor
and transfer it to the control logic of 8259 microprocessor. After
selection of Interrupt by 8259 microprocessor (based on priority
of the interrupt), it transfer the opcode of the selected Interrupt
and address of the Interrupt service sub routine to the other
connected microprocessor. The data bus buffer consists of 8 bits
represented as D0-D7 in the block diagram. Thus, shows that a
maximum of 8 bits data can be transferred at a time.
2. Read/Write logic – This block works only when the value of pin
CS is low (as this pin is active low). This block is responsible for
the flow of data depending upon the inputs of RD and WR.
These two pins are active low pins used for read and write
operations.
 3. Control logic – It is the center of the PIC and controls the
functioning of every block. It has pin INTR which is connected
with other microprocessor for taking interrupt request and pin
INT for giving the output. If 8259 is enabled, and the other
microprocessor Interrupt flag is high then this causes the value
of the output INT pin high and in this way 8259 responds to the
request made by other microprocessor.
4. Interrupt request register (IRR) – It stores all the interrupt level
which are requesting for Interrupt services.
5. Interrupt service register (ISR) – It stores the interrupt level
which are currently being executed.
6. Interrupt mask register (IMR) – It stores the interrupt level
which have to be masked by storing the masking bits of the
interrupt level.
7. Priority resolver – It examines all the three registers and set the
priority of interrupts and according to the priority of the
interrupts, interrupt with highest priority is set in ISR register.
Also, it reset the interrupt level which is already been serviced in
IRR.
8. Cascade buffer – To increase the Interrupt handling capability,
we can further cascade more number of pins by using cascade
buffer. So, during increment of interrupt capability, CSA lines are
used to control multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in
master mode else in slave mode. In Non Buffered mode, SP/EN pin is
used to specify whether 8259 work as master or slave and in Buffered
mode, SP/EN pin is used as an output to enable data bus.

Advantages:

Interrupt Management: The 8259 PIC is designed to handle interrupts

efficiently and effectively, allowing for faster and more reliable
processing of interrupts in a system.
Flexibility: The 8259 PIC is programmable, meaning that it can be
customized to suit the specific needs of a given system, including the
number and type of interrupts that need to be managed.
Compatibility: The 8259 PIC is compatible with a wide range of
microprocessors, making it a popular choice for managing interrupts in
many different systems.
Multiple Interrupt Inputs: The 8259 PIC can manage up to 8 interrupt
inputs, allowing for the management of complex systems with multiple
devices.
Ease of Use: The 8259 PIC includes simple interface pins and registers,
making it relatively easy to use and program.

Disadvantages:

Cost: While the 8259 PIC is relatively affordable, it does add cost to a
system, particularly if multiple PICs are required.
Limited Number of Interrupts: The 8259 PIC can manage up to 8
interrupt inputs, which may be insufficient for some applications.
Complex Programming: Although the interface pins and registers of the
8259 PIC are relatively simple, programming the 8259 can be complex,
requiring careful attention to interrupt prioritization and other
parameters.
Limited Functionality: While the 8259 PIC is a useful peripheral for
interrupt management, it does not include more advanced features, such
as DMA (direct memory access) or advanced error correction.

Operating modes of 8259 PIC

•
Need .For PIC in 8085 and 8086 :
• In 8086 we have two pins for interrupt handling i.e. NMI and
INTR. If we use NMI for data corruption or non-recoverable
hardware errors and one interrupt pin, INTR for other software
interrupts.
• In a system when we have multiple interrupts from different
input or output devices, then we need a PIC(priority interrupt
controller) that can handle multiple interrupts from different
devices and prioritize them according to system requirements,
and sends them to a single interrupt pin on the processor.
Characteristics of 8259 :
• A single 8259 handles 8 interrupts, while a cascaded
configuration of it in which 1 master and 8 slaves can handle up
to 64 interrupts.
• It can handle both edge-level triggering interrupts.
• Its priority structure can be easily altered.
• In 8259, interrupts can be masked individually.
• The vector address of the interrupts is easily programmed.
• It must be initialized by giving commands, to determine various
properties like vector numbers, priority, masking, triggering etc.

Operating modes of 8259 :

The different modes of operation of 8259 can be programmed by altering
the bits of ICW or OCW commands of 8259.

Fully nested mode :

• It is the default mode of operation of 8259.
• Here, IR0 has the highest priority and IR7 has the lowest priority.
When any interrupt requests occurs then the highest priority
interrupt request is serviced first and its vector address is placed
on data bus and its corresponding bit in ISR register is set until
the processor executes the EOI command before returning the
interrupt service routine or AEOI(Automatic end of interrupt bit
is set) until the falling of the last INTA’.
• When the ISR bit is set for an interrupt, then all the equal and
lower priority interrupts are masked, but a higher level interrupt
request can occur and which will be acknowledged only if the
microprocessor interrupt enables flag IF= 1.
• It is suitable for a single 8259 configuration.
• The priority mechanism can be easily programmed.

Special fully nested mode (SFNM) :

This mode is used by master 8259 in a cascaded mode. Its priority
structure is fixed and is the same as fully nested mode (i.e. IR0 has the
highest priority and IR7 has the lowest priority).
In a special fully nested mode, the master will only serve higher priority
interrupt from a slave, whose another interrupt is currently in service.
Rotating priority modes :
There are two rotating priority modes –
1. Automatic rotation mode
• It is used when various interrupt sources are of the same
priority. In this mode, after a device is serviced, it gets the lowest
priority. All other priorities rotate according to it.
• Example: If IR4 has just been serviced, it will get the lowest
priority.
2. Specific Rotation Mode
• Here, the programmer can alter priorities by programming the
lowest priority and thus fixing all other priorities.
• For example: If IR6 is programmed as the lowest priority, then
IR7 will have the highest priority.
Special mask mode (SMM) :
• In SMM, 8259 enables interrupts of all levels (lower or higher)
except the one that is currently in service.
• Because we are especially masking the request of the priority
level of interrupt, which is the same as the current interrupt
priority level, therefore it is called special mask mode.
Poll mode :
Here the INT pin of 8259 is not used, so, 8259 cannot interrupt the µp.
Instead, the µP will provide a poll command to 8259 using OCW3. In
response, 8259 provides a poll word to the µP. The poll word indicates
the highest priority interrupt which needs service from µP. Thereafter, the
µP services the interrupt.
Advantage :
The µP’s program is not interrupted. It can be used when ISR is common
for many interrupts. It can be used to increase the number of interrupts
beyond 64(i.e. in case of a cascaded configuration).
Drawback :
If the polling interval is long, then the interrupts will be serviced after a
long period. If the polling interval is short, then the time may be wasted
on unnecessary polls.
EOI – (End Of Interrupt) :
When the microprocessor acknowledges an interrupt request by sending
the first INTA signal, the 8259 sets the corresponding bit in the In Service
Register (ISR). This starts the service of the interrupt.
When this bit in the ISR is cleared, then it is known as the end of
interrupt (EOI).
EOI Modes:
1. Normal EOI Mode –
Here, an EOI command is compulsory. The EOI command is written by
the programmer at the end of the ISR. It makes 8259 to reset the bit from
ISR. Further EOI command is of two types :
• Non Specific EOI Command Here the programmer doesn’t
specify the bit number to be reset in the ISR. 8259 itself resets
the highest priority bit from ISR.
• Specific EOI Command: Here the programmer determines the
bit number to be reset from ISR.
2. Automatic EOI mode (AEOI) –
In this mode, the EOI command is not required. Instead, 8259 will itself
clear the corresponding bit from ISR at the end of the 2nd INTA pulse.
Edge and level-triggered mode :
If the LTIM bit of ICW1 =0 then the edge-triggered interrupt mode is set,
otherwise the interrupts are level triggered.
Reading 8259 Status :
The status of the registers can be read by this mode. Here, the OCW3 is
used to read IRR and ISR and OCW1 is used to read IMR.
Buffered Mode :
8259 sends a buffer enabled signal on the SP’/ EN’ pin when data is
placed on the data bus.
Programmable Timer.
A Programmable Timer in the context of embedded systems, particularly for the 8051
microcontroller, is a hardware module that can generate precise time delays, measure time
intervals, or count external events. The 8051 microcontroller includes two 16-bit
programmable timers/counters (Timer 0 and Timer 1), which are widely used for tasks like
generating time delays, scheduling tasks, synchronizing processes, and handling periodic
interrupts. Below, I’ll provide a detailed explanation of programmable timers in the 8051,
their operation, configuration, modes, and applications, tailored to your Embedded Systems
Unit 4 syllabus.

Overview of Programmable Timers in 8051

The 8051’s timers/counters are versatile peripherals that can function as:

• Timers: Count internal clock pulses (derived from the system clock) to measure time
or generate delays.
• Counters: Count external events (pulses) applied to specific pins (T0 or T1).

Each timer (Timer 0 and Timer 1) is a 16-bit register that increments with each clock cycle or
external pulse. When the timer overflows (reaches 0xFFFF and resets to 0x0000), it can
trigger an interrupt or set a flag, making it useful for precise timing and synchronization in
embedded systems.

Key Features of 8051 Programmable Timers

1. Two 16-bit Timers/Counters:

o Timer 0: Controlled by registers TL0 (low byte) and TH0 (high byte).
o Timer 1: Controlled by registers TL1 (low byte) and TH1 (high byte).
2. Four Operating Modes:
o Mode 0: 13-bit timer/counter (less commonly used).
o Mode 1: 16-bit timer/counter (most common for general-purpose timing).
o Mode 2: 8-bit auto-reload mode (automatically reloads a preset value upon
overflow).
o Mode 3: Split timer mode (Timer 0 splits into two 8-bit timers; Timer 1 is
halted or used differently).
3. Clock Source:
o Internal: System clock divided by 12 (fosc/12).
o External: Pulses on T0 (P3.4) or T1 (P3.5) pins for counter mode.
4. Interrupt Capability:
o Timer 0 overflow triggers interrupt at vector 0x000B.
o Timer 1 overflow triggers interrupt at vector 0x001B.
5. Control Registers:
o TMOD: Configures timer mode and operation (timer or counter).
o TCON: Controls timer start/stop and overflow flags.
o IE: Enables/disables timer interrupts.
Key Registers for Programmable Timers

1. TMOD (Timer Mode Register):

o Address: 0x89 (not bit-addressable).
o Bits:
§ GATE: Gating control (1 = timer runs only when INT0/INT1 is high;
0 = timer runs when TRx is set).
§ C/T: Counter/Timer select (0 = timer, 1 = counter).
§ M1, M0: Mode select (00 = Mode 0, 01 = Mode 1, 10 = Mode 2, 11 =
Mode 3).
o Example: TMOD = 0x01 sets Timer 0 to Mode 1 (16-bit timer).
2. TCON (Timer Control Register):
o Address: 0x88 (bit-addressable).
o Relevant bits:
§ TR0 (bit 4): Timer 0 run control (1 = start, 0 = stop).
§ TR1 (bit 6): Timer 1 run control.
§ TF0 (bit 5): Timer 0 overflow flag (set on overflow, cleared by
hardware/software).
§ TF1 (bit 7): Timer 1 overflow flag.
o Example: TCON = 0x10 starts Timer 0 (TR0 = 1).
3. Timer Registers:
o TH0, TL0: High and low bytes of Timer 0 (16-bit count).
o TH1, TL1: High and low bytes of Timer 1.
o Example: To set a starting count of 0xFC00 for Timer 0: TH0 = 0xFC; TL0 =
0x00.
4. IE (Interrupt Enable Register):
o Address: 0xA8 (bit-addressable).
o Relevant bits:
§ ET0 (bit 1): Enable Timer 0 interrupt.
§ ET1 (bit 3): Enable Timer 1 interrupt.
§ EA (bit 7): Global interrupt enable.
o Example: IE = 0x82 enables Timer 0 interrupt and global interrupts.

Timer Modes

1. Mode 0 (13-bit Timer/Counter):

o Uses 5 bits of TLx and 8 bits of THx (total 13 bits).
o Rarely used due to limited resolution.
o Maximum count: 2^13 = 8192.
2. Mode 1 (16-bit Timer/Counter):
o Full 16-bit timer (TLx + THx).
o Maximum count: 2^16 = 65,536.
o Commonly used for long delays or event counting.
o On overflow, TFx flag is set, and the timer resets to 0x0000.
3. Mode 2 (8-bit Auto-Reload):
o Uses TLx as an 8-bit counter; THx holds the reload value.
o On overflow, TLx is automatically reloaded with THx’s value.
 o Ideal for generating periodic interrupts or baud rates for UART.
o Maximum count: 2^8 = 256.
4. Mode 3 (Split Timer Mode):
o Timer 0 splits into two 8-bit timers (TL0 and TH0).
o TL0 operates as a timer/counter; TH0 as a timer only.
o Timer 1 is stopped or used for other purposes (e.g., baud rate generation).
o Used for applications needing multiple independent timers.