Exp. No.

: 1(a)
Design of basic combinational circuits
using HDL

AIM:

To design, simulate and implement basic combinational circuits using Verilog HDL

SOFTWARE REQUIRED:

Xilinx ISE Design Suite 12.1

THEORY:

HALF ADDER:

The half adder consists of two input variables designated as Augends and Addend bits. Output
variables produce the Sum and Carry. The ‘carry’ output is 1 only when both inputs are 1 and
sum is 1 if any one input is 1. The Boolean expression is given by,

sum = x ^ y carry = x & y

FULL ADDER:

A Full adder is a combinational circuit that focuses the arithmetic sum of three bits. It consists
of 3 inputs and 2 outputs. The third input is the carry from the previous Lower Significant
Position. The two outputs are designated as Sum (S) and Carry (C). The binary variable S
gives the value of the LSB of the Sum. The output S=1 only if odd number of 1’s are present
in the input and the output C=1 if two or three inputs are 1.

sum = x ^ y ^ z

carry= (x & y) | (y & z) | (x & z)

PROCEDURE:
Software part
1. Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilizatio n summary by double Clicking
on thesynthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output can be observed by using ISIM Simulator.
Half Adder:

Program :

Module Half add(a,b,sum,carry);

input a,b;
output sum,carry;
xor (sum,a,b);
and (carry,a,b);
endmodule

Truth table:

Half Adder

Input1 Input2 Carry Sum

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
RTL SCHEMATIC:

TECHNOLOGIC SCHEMATIC:

OUTPUT WAVEFORM:
Full Adder:

Program:

module fulladd (sum, carry, a, b, c);

input a, b, c;
output sum, carry;
wire w1, w2, w3;
xor (sum,a,b,c);
and (w1,a,b);
and(w2,b,c);
and(w3,c,a);
or(carry,w1,w2,w3);
endmodule

Truth Table:

a b c carry Sum
- -
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
----- -
RTL SCHEMATIC:

TECHNOLOGIC SCHEMATIC:

OUTPUT WAVEFORM:
 HALF SUBTRACTOR:

Program:
module halfSub(a, b, diff, borr);
input a, b;
output diff, borr;
wire s;
not (s, a);
xor (diff, a, b);
and (borr, s, b);
endmodule

Truth Table:

- -
Input1 Input2 Borrow Difference
-
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

RTL SCHEMATIC
TECHNOLOGIC SCHEMATIC

Output Wave:

FULL SUBTRACTOR:

Program:

module fullsub (a, b, cin, diff, borr);

input a, b, cin;
output diff, borr;
wire w1, w2, w3, w4, w5;
not n1(w1, a);
 not n2(w4, w3);
xor x1(w3, a, b);
xor x2(diff, w3, cin);
and a1(w2, w1, b);
and a2(w5,w4,cin);
or g1(borr, w5, w2);
endmodule

Truth Table:

A B Cin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

RTL Schematic
TEHNOLOGICAL SCHEMATIC

Output Wave:

Result:

Thus the basic combinational circuits was simulated and implemented successfully.
 Exp. No.: 1(b) Design of basic sequential circuits using
HDL

AIM:

To implement the basic sequential circuits using Verilog HDL.

SOFTWARE REQUIRED:

Xilinx ISE Design Suite 12.1

PROCEDURE:
Software part
 Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of PC.
 Write the Verilog code by choosing HDL as top level source module.
 Check syntax, view RTL schematic and note the device utilizatio n summary by double Clicking
on thesynthesis in the process window.
 Perform the functional simulation using Xilinx ISE simulator.
 The output can be observed by using ISIM Simulator.

D-FLIPFLOP:
 PROGRAM:

Module DFF(Clock, Reset, d, q);

input Clock;
input Reset;
input d;
output q;
reg q;
always@(posedge Clock or negedge Reset)
if (~Reset)
q=1'b0;
else
q=d;
endmodule

Truth Table:

D FlipFlop
-
Clock Reset Input (d) Output q(~q)

0 0 0 0(1)
1 0 0 0(1)
0 0 1 0(1)
1 0 1 0(1)
0 0 0 0(1)
1 0 0 0(1)
0 1 1 0(1)
1 1 1 1(0)
0 1 0 1(0)
1 1 0 0(1)
0 1 1 0(1)
1 1 1 1(0)
0 0 0 0(1)
1 0 0 0(1)
0 0 0 0(1)

OUTPUT:
T-FLIPFLOP:

PROGRAM:

Module TFF(Clock, Reset, t, q);

input Clock;
input Reset;
input t;
output q;
reg q;
always@(posedge Clock , negedge Reset)
if(~Reset) q=0;
else if (t) q=~q;
else q=q;
endmodule

TRUTH TABLE:
-
Clock Reset Input (t) Output q(~q)

0 0 0 0(1)
1 0 0 0(1)
0 0 1 0(1)
1 0 1 0(1)
0 0 0 0(1)
1 0 0 0(1)
0 1 1 0(1)
1 1 1 1(0)
0 1 0 1(0)
1 1 0 1(0)
0 1 1 1(0)
1 1 1 0(1)
0 0 0 0(1)
1 0 0 0(1)
0 0 0 0(1)
OUTPUT WAVEFORM:

RESULT:
Thus the basic sequential circuits are designed, simulated and implemented successfully.
 Exp. No.: 2(a) DESIGN 8-BIT ADDERS U SIN G HD L

AIM:
To design and to implement 8-bit adders usingVerilog HDL.

SOFTWARE REQUIRED:

Xilinx ISE Design Suite 12.1

PROCEDURE:
Software part
 Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of PC.
 Write the Verilog code by choosing HDL as top level source module.
 Check syntax, view RTL schematic and note the device utilizatio n summary by double Clicking
on thesynthesis in the process window.
 Perform the functional simulation using Xilinx ISE simulator.
 The output can be observed by using ISIM Simulator.

RIPPLE CARRY ADDER:

PROGRAM:
Main program:
module sw(a, b, c, sum, carry);
input [7:0]a;
input [7:0]b;
input c;
output [7:0]sum;
output carry;
wire [6:0]c;
gk fa0(a[0],b[0],c,sum[0],c1);
gk fa1(a[1],b[1],c1,sum[1],c2);
gk fa2(a[2],b[2],c2,sum[2],c3);
gk fa3(a[3],b[3],c3,sum[3],c4);
gk fa4(a[4],b[4],c4,sum[4],c5);
gk fa5(a[5],b[5],c5,sum[5],c6);
gk fa6(a[6],b[6],c6,sum[6],c7);
gk fa7(a[7],b[7],c7,sum[7],carry);
endmodule

Sub-Program

module fulladd (sum, carry, a, b, c);

input a, b, c;
output sum, carry;
wire w1, w2, w3;
xor (sum,a,b,c);
and (w1,a,b);
and(w2,b,c,);
and(w3,c,a);
or(carry,w1,w2,w3);
endmodule
RTL SCHEMATIC:
 TECHNOLOGICAL SCHEMATIC:

OUTPUT WAVEFORM:

RESULT:

Thus 8-bit adder was designed and implemented successfully.

 Exp. No.: 2(b) DESIGN A MULTIPLIER USING HDL

AIM:

To implement a multiplier using Verilog HDL.

SOFTWARE REQUIRED:

Xilinx ISE Design Suite 12.1

PROCEDURE:

 Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of PC.
 Write the Verilog code by choosing HDL as top level source module.
 Check syntax, view RTL schematic and note the device utilization summary by double Clicking
on the synthesis in the process window.
 Perform the functional simulation using Xilinx ISE simulator.
 The output can be observed by using ISIM Simulator.

4 BIT MULTIPLIER:

module unsignedmult (out, a, b);

Output [7:0] out;
Input [3:0] a;
Input [3:0] b;
Assign out=a*b;
endmodule
TRUTH TABLE:

--------------------------------------------------------

A B RES

---------------------------------------------------------

1000 1001 1000

----------------------------------------------------------
RTL SCHEMATIC:

TECHNOLOGICAL SCHEMATIC:

OUTPUT WAVE:
ARRAY MULTIPLIER:

Program:

module HA (sout,cout,a,b);
input a,b;
output sout,cout;
assign sout=(a^b);
assign cout=(a&b);
endmodule

module FA (sout,cout,a,b,cin);
input a,b,cin;
output sout,cout;
assign sout=(a^b^cin);
assign cout=((a&b)|(b&cin)|(cin&a));
endmodule
module bitmul (m,x,y);
output [7:0]m;
input [3:0]x;
input [3:0]y;
assign m[0]=(x[0]&y[0]);
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
HA HA1 (m[1],x1,(x[1]&y[0]),(x[0]&y[1]));
FA FA1 (x2,x3,(x[1]&y[1]),(x[0]&y[2]),x1);
FA FA2 (x4,x5,(x[1]&y[2]),(x[0]&y[3]),x3);
HA HA2 (x6,x7,(x[1]&y[3]),x5);
HA HA3 (m[2],x15,x2,(x[2]&y[0]));
FA FA5 (x14,x16,x4,(x[2]&y[1]),x15);
FA FA4 (x13,x17,x6,(x[2]&y[2]),x16);
FA FA3 (x9,x8,x7,(x[2]&y[3]),x17);
HA HA4 (m[3],x12,x14,(x[3]&y[0]));
FA FA8 (m[4],x11,x13,(x[3]&y[1]),x12);
FA FA7 (m[5],x10,x9,(x[3]&y[2]),x11);
FA FA6 (m[6],m[7],x8,(x[3]&y[3]),x10);
endmodule

RTL SCHEMATIC:

TECHNOLOGICAL SCHEMATIC:
OUTPUT WAVEFORM:

Result:

Thus the multiplier was implemented successfully

EXP.NO: 3
SIMULATION OF UNIVERSAL SHIFT REGISTER
DATE:

AIM:
To write a verilog program for Universal Shift Register and to synthesize, simulate it using Xilinx
software tool.

TOOLS REQUIRED:
Software:
1. Xilinx ISE Design Suite 12.1

THEORY :
UNIVERSAL SHIFT REGISTER:
A Unidirectional shift register is a register that can capable of transferring data in only one direction. Whereas
the register that is capable of transferring data in both left and right direction is called a
„bidirectional shift register.‟ Now let we have a register which can capable to transfer data in both the shift-
right and shift- left, along with the necessary input and output terminals for parallel transfer, then it is called
a shift register with parallel load or „universal shift register.‟
A shift-right control to enable the shift-right operation and the serial input and output lines associated
with the shift-right.
A shift- left control to enable the shift- left operation and the serial input and output lines associated with
the shift- left.
A parallel- load control to enable a parallel transfer and the n input lines associated with the parallel
transfer.
n parallel output lines.
A clear control to clear the register to 0.
A CLK input for clock pulses to synchronize all operations.
A control state that leaves the information in the register unchanged even though clock pulses are
continuously applied.
PROCEDURE:
Software part
6. Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of PC.
7. Write the Verilog code by choosing HDL as top level source module.
8. Check syntax, view RTL schematic and note the device utilizatio n summary by double Clicking on the
synthesis in the process window.
9. Perform the functional simulation using Xilinx ISE simulator.
10. The output can be observed by using ISIM Simulator.
PROGRAM:

REGISTER
S1 S0
OPERATION

0 0 No changes

0 1 Shift right

1 0 Shift left

1 1 Parallel load

module universal shift(a,s,clk,p);

input [3:0]a;
input [1:0]s;
input clk;
output reg [3:0]p;
initial
p<=4'b0110;
always@(posedge clk)
begin
case (s)
2'b00:
begin
p[3]<=p[3];
p[2]<=p[2];
p[1]<=p[1];
p[0]<=p[0];
end
2'b01:
begin
p[3]<=p[0];
p[2]<=p[3];
p[1]<=p[2];
p[0]<=p[1];
end
2'b10:
begin
p[0]<=p[3];
p[1]<=p[0];
p[2]<=p[1];
p[3]<=p[2];
end
2'b11:
begin
p[0]<=a[0];
p[1]<=a[1];
p[2]<=a[2];
p[3]<=a[3];
end
endcase
end
endmodule

RESULT

The universal shift register is designed and simulated successfully.

EXP.NO: 4
SIMULATION AND DESIGN OF MEMORIES
DATE:

AIM:
To write a Verilog program for a 16x4 memory and to synthesize, simulate it using Xilinx software
tool.

TOOLS REQUIRED:
Software:
1. Xilinx ISE Design Suite 12.1

THEORY:
MOD 10 COUNTERS:

The memory block diagram is shown in above figure. It takes a few assumptions into consideration for
easing the operations of the circuit. While data input pin and address pin may have any value depending on
the specifications of memory used and your need, clock used in the circuit is active high.
Enable pin triggers the circuit when it is active high, and read operation is performed when read/write pin
is high, while write operation is performed when read/write pin is active low.
PROCEDURE:
Software part
1. Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double clicking on the
synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output can be observed by using ISIM Simulator.
PROGRAM:
module memory_16x4(op,ip,rd_wr,clk,address);
output reg [3:0] op;
input [3:0] ip;
input [3:0] address;
input rd_wr,clk;
reg [3:0] memory[0:15];
always @(posedge clk)
begin
if (rd_wr)
op=memory[address];
else
begin
memory[address]=ip;
end
end
endmodule // memory_16x4

RESULT:

Thus the memories are designed using Verilog HDL and simulated successfully.
Exp. No.: 5(a) DESIGN OF FINITE STATE MACHINE
(MOORE MACHINE)

AIM:

To implement finite state machine (moore machine) using Verilog HDL

SOFTWARE REQUIRED:

Xilinx ISE Design Suite 12.1

PROCEDURE:
Software part
 Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of PC.
 Write the Verilog code by choosing HDL as top level source module.
 Check syntax, view RTL schematic and note the device utilizatio n summary by double Clicking
on thesynthesis in the process window.
 Perform the functional simulation using Xilinx ISE simulator.
 The output can be observed by using ISIM Simulator.

MOORE MACHINE:

PROGRAM:

module moore( clk, rst, inp, outp);

input clk, rst, inp;

output outp;

reg [1:0] state;

reg outp;
 always @( posedge clk, posedge rst )
begin
if( rst )
state <= 2'b00;
else

begin

case( state )

2'b00:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end

2'b01:
begin
if( inp ) state <= 2'b11;
else state <= 2'b10;
end

2'b10:
begin
if( inp ) state <= 2'b01;
else state <= 2'b11;
end

2'b11:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
endcase
end
end
always @(posedge clk, posedge rst)
begin
if( rst )
outp <= 0;
else if( state == 2'b11 )
outp <= 1;
else outp <= 0;

end

endmodule
 RTL SCHEMATIC:

TECHNOLOGICAL SCHEMATIC:

OUTPUT WAVEFORM:

RESULT:

Thus the finite state machine (moore machine) has been simulated and verified and
implemented.
 Exp. No.: 5(b) DESIGN OF FINITE STATE MACHINE
(MEALY MACHINE)

AIM:

To implement finite state machine (mealy machine) using Verilog HDL

SOFTWARE REQUIRED:

Xilinx ISE Design Suite 12.1

PROCEDURE:
Software part
 Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of PC.
 Write the Verilog code by choosing HDL as top level source module.
 Check syntax, view RTL schematic and note the device utilizatio n summary by double Clicking
on thesynthesis in the process window.
 Perform the functional simulation using Xilinx ISE simulator.
 The output can be observed by using ISIM Simulator.

MEALY MACHINE: State diagram

PROGRAM:
module mealy( clk, rst, inp, outp);

input clk, rst, inp;

output outp;

reg [1:0] state;

reg outp;

always @( posedge clk, posedge rst ) begin

if( rst ) begin
state <= 2'b00;
outp <= 0;
end

else begin

case( state )
2'b00: begin
if( inp ) begin
state <= 2'b01;
outp <= 0;
end
else begin
state <= 2'b10;
outp <= 0;
end
end

2'b01: begin
if( inp ) begin
state <= 2'b00;
outp <= 1;
end
else begin
state <= 2'b10;
outp <= 0;
end
end

2'b10: begin
if( inp ) begin
state <= 2'b01;
outp <= 0;
 end
else begin
state <= 2'b00;
outp <= 1;
end

end

default: begin
state <= 2'b00;
outp <= 0;
end
endcase
end
end

endmodule

RTL SCHEMATIC:

TECHNOLOGICAL SCHEMATIC:
OUTPUT WAVEFORM:

RESULT:

Thus the finite state machine (Mealy machine) has been simulated and verified
and implemented.
Exp. No.: 6
DESIGN OF SYNCHRONOUS
UP/ DOWN COUNTER

AIM:

To implement synchoronous up/down counters using Verilog HDL

SOFTWARE REQUIRED:

Xilinx ISE Design Suite 12.1

PROCEDURE:
Software part
 Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of PC.
 Write the Verilog code by choosing HDL as top level source module.
 Check syntax, view RTL schematic and note the device utilizatio n summary by double Clicking
on thesynthesis in the process window.
 Perform the functional simulation using Xilinx ISE simulator.
 The output can be observed by using ISIM Simulator.

UP COUNTER:
PROGRAM:

module upcounterr(clk,clr,q);
input clk, clr;
output [3:0]q;
reg [3:0]tmp;
always@(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4'b0000;
else
tmp <= tmp + 1'b1;
end
assign q = tmp;
endmodule

RTL SCHEMATIC:

TECHNOLOGICAL SCHEMATIC:
OUTPUT WAVEFORM:

DOWN COUNTER:

PROGRAM:

module downcounterr(clk,clr,q);
input clk, clr;
output [3:0]q;
reg [3:0]tmp;
always@(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4'b1111;
else
tmp <= tmp - 1'b1;
end
assign q = tmp;
endmodule
RTL SCHEMATIC:

TECHNOLOGICAL SCHEMATIC:

OUTPUT WAVEFORM:

RESULT:
Thus the synchronous up / down counter is designed and simulated successfully.
Exp. No.: 7
DESIGN OF ASYNCHRONOUS
UP/ DOWN COUNTER

AIM :
To implement synchoronous up/down counters using Verilog HDL

SOFTWARE REQUIRED:

Xilinx ISE Design Suite 12.1

PROCEDURE:
Software part
 Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of PC.
 Write the Verilog code by choosing HDL as top level source module.
 Check syntax, view RTL schematic and note the device utilizatio n summary by double Clicking on the
synthesis in the process window.
 Perform the functional simulation using Xilinx ISE simulator.
 The output can be observed by using ISIM Simulator.

UP COUNTER :

PROGRAM :
module counter(clk,rst,count);
input clk,rst;
output[3:0]count;
reg[3:0]count;
always@(negedge clk)
if(rst)
count[0]<=1’b0;
else
count[0]<=~count[0];
always @(negedge count[0])
if(rst)
count[1]<=1’b0;
else
count[1]<=~count[1];
always @(negedge count[1])
if(rst)
count[2]<=1’b0;
else
count[2]<=~count[2];
always @(negedge count[2])
if (rst)
count[3]<=1’b0;
else
count[3]<=~count[3];
endmodule

RESULT:
Thus the asynchronous is designed and simulated successfully.
EXP.NO: 8(a)
DESIGN AND SIMULATION OF CMOS GATES
DATE:

AIM:
To perform the functional verification of the CMOS gates through schematic entry.

FACILITIES REQUIRED AND PROCEDURE

a) Facilities required to do the experiment

S.No. SOFTWARE REQUIREMENTS QUANTITY

1 S-Edit, W-Edit, T-Edit using Tanner Tool. 1

b) Procedure for doing the experiment

S.NO DETAILS OF THE STEP

1 Draw the schematic of CMOS Gates using S-edit

2 Perform Transient Analysis of the CMOS Inverter

3 Obtain the output wave form from W-edit

4 Obtain the spice code using T-edit

c) THEORY: (CMOS NOT)

 Inverter consists of nMOS and pMOS transistor in series connected between VDD and GND.
 The gate of the two transistors are shorted and connected to the input. When the input to the inverter
A =0, nMOS transistor is OFF and pMOS transistor is ON. The output is pull- up to VDD.When the
input A=1, nMOS transistor is ON and pMOS transistor is OFF. The Output is Pull-down to GND.
 CMOS NOT
SCHEMATIC DIAGRAM:

OUTPUT WAVEFORM:
NETLIST:
********* Simulation Settings - General Section *********
.lib "C:\Documents and Settings\ece01\My Documents\Tanner EDA\Tanner Tools
v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" TT

*-------- Devices With SPICE.ORDER == 0.0 --------

***** Top Level*****
MNMOS_2_5v_1 Y A Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $
$x=4293
+$y=3300 $w=414 $h=600
MPMOS_2_5v_1 Y A Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
+$x=4293 $y=4500 $w=414 $h=600

*-------- Devices With SPICE.ORDER > 0.0 --------

VVdd_4 Vdd Gnd DC 5 $ $x=1200 $y=3800 $w=400 $h=600
VVdd_5 A Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=2800 $y=3500 $w=400 $h=600
.PRINT TRAN V(A) $ $x=3250 $y=4650 $w=300 $h=1500 $r=270
.PRINT TRAN V(Y) $ $x=5350 $y=4650 $w=300 $h=1500 $r=270

********* Simulation Settings - Analysis Section *********

.tran 10ns 1000ns
********* Simulation Settings - Additional SPICE Commands *********
.end
 CMOS NAND
SCHEMATIC DIAGRAM:

OUTPUT WAVEFORM:
NETLIST:

********* Simulation Settings - General Section *********

.lib "C:\Documents and Settings\ece01\My Documents\Tanner EDA\Tanner Tools
v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" TT

*-------- Devices With SPICE.ORDER == 0.0 --------

***** Top Level*****
MNMOS_2_5v_1 Y B N_1 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $
$x=5993
+$y=3200 $w=414 $h=600
MNMOS_2_5v_2 N_1 A Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $
+$x=5993 $y=2200 $w=414 $h=600
MPMOS_2_5v_1 Y B Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
+$x=5993 $y=4700 $w=414 $h=600
MPMOS_2_5v_2 Y A Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
+$x=4493 $y=4700 $w=414 $h=600

*-------- Devices With SPICE.ORDER > 0.0 --------

VVdd_4 Vdd Gnd DC 5 $ $x=1200 $y=3800 $w=400 $h=600
VVoltageSource_1 A Gnd BIT({0101} ) $ $x=3300 $y=2100 $w=400 $h=600
VVoltageSource_2 B Gnd BIT({0011} ) $ $x=4900 $y=3000 $w=400 $h=600
.PRINT TRAN V(A) $ $x=2650 $y=3150 $w=1500 $h=300 $r=180
.PRINT TRAN V(B) $ $x=2650 $y=4050 $w=1500 $h=300 $r=180
.PRINT TRAN V(Y) $ $x=7050 $y=4850 $w=300 $h=1500 $r=270
********* Simulation Settings - Analysis Section *********
.tran 10ns 100ns
********* Simulation Settings - Additional SPICE Commands *********
.end
 CMOS NOR

SCHEMATIC DIAGRAM:

OUTPUT WAVEFORM:
NETLIST:

********* Simulation Settings - General Section *********

.lib "C:\Documents and Settings\ece01\My Documents\Tanner EDA\Tanner Tools
v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" TT

*-------- Devices With SPICE.ORDER == 0.0 --------

***** Top Level*****
MNMOS_1 Y A Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=4493
+$y=2300 $w=414 $h=600
MNMOS_2 Y B Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5993
+$y=2200 $w=414 $h=600
MPMOS_1 Y B N_3 Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $ $x=5993
+$y=3600 $w=414 $h=600
MPMOS_2 N_3 A Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $ $x=5993
+$y=4500 $w=414 $h=600

*-------- Devices With SPICE.ORDER > 0.0 --------

VVdd_4 Vdd Gnd DC 5 $ $x=700 $y=3800 $w=400 $h=600
Vv1 A Gnd BIT({0101} ) $ $x=2800 $y=2100 $w=400 $h=600
VV2 B Gnd BIT({0011} ) $ $x=3500 $y=2100 $w=400 $h=600
.PRINT TRAN V(A) $ $x=2150 $y=3150 $w=1500 $h=300 $r=180
.PRINT TRAN V(B) $ $x=2750 $y=3850 $w=1500 $h=300 $r=180
.PRINT TRAN V(Y) $ $x=7050 $y=3650 $w=300 $h=1500 $r=270

********* Simulation Settings - Analysis Section *********

.tran 10ns 100ns
********* Simulation Settings - Additional SPICE Commands *********
.end

RESULT

Thus the functional verification of the CMOS gates are done successfully.
EXP.NO: 8(b)
DESIGN AND SIMULATE A FLIP-FLOP
DATE:

AIM:
To perform the functional verification of a D- flip flop through schematic entry.

FACILITIES REQUIRED AND PROCEDURE

a) Facilities required to do the experiment

S.No. SOFTWARE REQUIREMENTS QUANTITY

1 S-Edit, W-Edit, T-Edit using Tanner Tool. 1

b) Procedure for doing the experiment

S.NO DETAILS OF THE STEP

1 Draw the schematic of D- flipflop using S-edit

2 Perform Transient Analysis of D-flipflop

3 Obtain the spice code using T-edit

4 Obtain the output wave form from W-edit

c) THEORY: (D-FLIP FLOP)

The D flip- flop tracks the input, making transitions with match those of the input D. The D standsfor
"data"; this flip- flop stores the value that is on the data line. It can be thought of as a basic memory
cell. A D flip- flop can be made from a set/reset flip- flop by tying the set to the reset through an
inverter. The result may be clocked.
SCHEMATIC ENTRY:

OUTPUT WAVEFORM:
NETLIST:
Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version 13.00 ;

* TDB File: Layout1

* Cell: Core Version 1.01

* Extract Definition File: lights.ext

* Extract Date and Time: 12/12/2019 - 09:47

.include lights.md

* NODE NAME ALIASES

* 1 = U1/NAND2C_5/Out2 (78 , 54)

* 2 = U1/NAND2C_4/Out2 (44 , 54)

* 3 = U1/NAND2C_3/Out2 (10 , 54)

* 6 = q (100 , 12.5)

* 6 = U1/NAND2C_3/Out1 (2 , 52)

* 6 = U1/NAND2C_4/A (20 , 70)

* 7 = Vdd (-101 , 4)

* 7 = U1/NAND2C_1/Vdd (-51 , 86)

* 7 = U1/NAND2C_2/Vdd (-17 , 86)

* 7 = U1/NAND2C_3/Vdd (-17 , 86)

* 7 = U1/NAND2C_4/Vdd (51 , 86)

* 7 = U1/NAND2C_5/Vdd (85 , 86)

* 8 = d (-101 , 106.5)

* 8 = U1/NAND2C_1/A (-82 , 70)

* 8 = U1/NAND2C_5/A (54 , 70)

* 8 = U1/NAND2C_5/B (62 , 63)

* 9 = U1/NAND2C_1/Out1 (-66 , 52)

* 9 = U1/NAND2C_3/A (-14 , 70)

* 10 = U1/NAND2C_2/Out1 (-32 , 52)

* 10 = U1/NAND2C_4/B (28 , 63)

* 11 = U1/NAND2C_2/B (-40 , 63)

* 11 = U1/NAND2C_5/Out1 (70 , 52)

* 12 = clk (-101 , 4.5)

* 12 = U1/NAND2C_1/B (-74 , 63)

* 12 = U1/NAND2C_2/A (-48 , 70)

* 13 = U1/NAND2C_2/Out2 (-24 , 54)

* 14 = U1/NAND2C_1/Out2 (-58 , 54)

* 17 = Gnd (92 , 4)

* 17 = U1/NAND2C_1/Gnd (-51 , 28)

* 17 = U1/NAND2C_2/Gnd (-17 , 28)

* 17 = U1/NAND2C_3/Gnd (-17 , 28)

* 17 = U1/NAND2C_4/Gnd (51 , 28)

* 17 = U1/NAND2C_5/Gnd (85 , 28)

* 18 = qbar (100 , 98.5)

* 18 = U1/NAND2C_3/B (-6 , 63)

* 18 = U1/NAND2C_4/Out1 (36 , 52)

M1 Vdd d U1/NAND2C_2/B Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p PS=34u

M2 U1/NAND2C_2/B d Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p PS=68u

M3 U1/NAND2C_5/Out2 U1/NAND2C_2/B Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u

AS=84p PS=34u

M4 Vdd U1/NAND2C_2/Out1 qbar Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p PS=34u

M5 qbar q Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p PS=68u

M6 U1/NAND2C_4/Out2 qbar Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u AS=84p PS=34u

M7 Vdd qbar q Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p PS=34u

M8 U1/NAND2C_3/Out2 q Vdd Vdd PMOS L=2u W=28u AD=148p PD=68u AS=84p PS=34u

M9 Gnd d 5 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u

M10 5 d U1/NAND2C_2/B Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p PS=68u
M11 U1/NAND2C_5/Out2 U1/NAND2C_2/B Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u
AS=122p PS=47u

M12 Gnd U1/NAND2C_2/Out1 4 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u

M13 4 q qbar Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p PS=68u

M14 U1/NAND2C_4/Out2 qbar Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u AS=122p
PS=47u

M15 U1/NAND2C_3/Out2 q Gnd Gnd NMOS L=2u W=28u AD=148p PD=68u AS=122p PS=47u

M16 q U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p PS=68u

M17 Vdd U1/NAND2C_2/B U1/NAND2C_2/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u
AS=84p PS=34u

M18 U1/NAND2C_2/Out1 clk Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p PS=68u

M19 U1/NAND2C_2/Out2 U1/NAND2C_2/Out1 Vdd Vdd PMOS L=2u W=28u AD=148p

PD=68u AS=84p PS=34u

M20 Vdd clk U1/NAND2C_1/Out1 Vdd PMOS L=2u W=28u AD=84p PD=34u AS=84p PS=34u

M21 U1/NAND2C_1/Out1 d Vdd Vdd PMOS L=2u W=28u AD=84p PD=34u AS=144p PS=68u

M22 U1/NAND2C_1/Out2 U1/NAND2C_1/Out1 Vdd Vdd PMOS L=2u W=28u AD=148p

PD=68u AS=84p PS=34u

M23 Gnd qbar 19 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u

M24 19 U1/NAND2C_1/Out1 q Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p PS=68u

M25 Gnd U1/NAND2C_2/B 16 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u

M26 16 clk U1/NAND2C_2/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p PS=68u

M27 U1/NAND2C_2/Out2 U1/NAND2C_2/Out1 Gnd Gnd NMOS L=2u W=28u AD=148p

PD=68u AS=122p PS=47u

M28 Gnd clk 15 Gnd NMOS L=2u W=28u AD=122p PD=47u AS=28p PS=30u

M29 15 d U1/NAND2C_1/Out1 Gnd NMOS L=2u W=28u AD=28p PD=30u AS=148p PS=68u

M30 U1/NAND2C_1/Out2 U1/NAND2C_1/Out1 Gnd Gnd NMOS L=2u W=28u AD=148p

PD=68u AS=122p PS=47u

* Total Nodes: 19

* Total Elements: 30
* Total Number of Shorted Elements not written to the SPICE file: 10

* Output Generation Elapsed Time: 0.000 sec

* Total Extract Elapsed Time: 1.875 sec

.END

RESULT:

Thus the functional verification of the flipflop is done successfully.

EXP.NO: 9
DESIGN AND SIMULATION OF 4-BIT COUNTER
DATE: USING FLIPFLOPS

AIM:
To perform the functional verification of the 4-bit counter circuit through schematic entry.

FACILITIES REQUIRED AND PROCEDURE

a) Facilities required for doing the experiment

S.No. SOFTWARE REQUIREMENTS QUANTITY

1 S-Edit, W-Edit, T-Edit using Tanner Tool. 1

b) Procedure for doing the experiment

S.NO DETAILS OF THE STEP

1 Draw the schematic of 4-bit counter using S-edit

2 Perform Transient Analysis of the 4-bit counter

3 Obtain the spice code using T-edit

4 Obtain the output wave form from W-edit

c) THEORY: (COUNTER)

A counter that can change state in either direction, under the control of an up or down selector input, is
known as an up/down counter. When the selector is in the up state, the counter increments its value. When
the selector is in the down state, the counter decrements the count. Likewise the counter counts in both the
directions continuously until attaining the end of the count. The count is init iated by the positive clock pulse.
The counter counts from 0000 to 1111 for up count and 1111 to 0000 for down count.
 4-BIT COUNTER
SCHEMATIC DIAGRAM:
OUTPUT WAVEFORM:
NETLIST:

********* Simulation Settings - General Section *********

.lib "C:\Documents and Settings\ece01\My Documents\Tanner EDA\Tanner Tools
v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" TT
*************** Subcircuits *****************
.subckt DFFC Clk Clr Data Q QB Gnd Vdd
*-------- Devices With SPICE.ORDER < 0.0 --------
* Design: Generic_250nm_LogicGates / Cell: DFFC / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: D Flip-Flop with Clear
* Date: 10/15/2008 12:04:43 PM
* Revision: 144 $ $x=7600 $y=600 $w=3600 $h=1200
* Design: Generic_250nm_LogicGates / Cell: DFFC / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: D Flip-Flop with Clear
* Date: 10/15/2008 12:04:43 PM
* Revision: 144 $ $x=7600 $y=600 $w=3600 $h=1200

*-------- Devices With SPICE.ORDER == 0.0 --------

MM1p CB Clk Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=1293
+$y=1800 $w=414 $h=600
MM2n CB Clk Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=1293
+$y=1000 $w=414 $h=600
MM3p C CB Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $ $x=2693
+$y=1800 $w=414 $h=600
MM4n C CB Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=2693
$y=1000
+$w=414 $h=600
MM5p 3 Data Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=3993
+$y=5600 $w=414 $h=600
MM6p 4 C 3 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $ $x=3993
+$y=4700 $w=414 $h=600
MM7n 4 CB 5 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=3993
$y=3900
+$w=414 $h=600
MM8n 5 Data Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=3993
+$y=3100 $w=414 $h=600
MM9p 6 10 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=5693
+$y=5600 $w=414 $h=600
MM10p 4 CB 6 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $ $x=6107
+$y=4700 $w=414 $h=600 $m
MM11n 4 C 7 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5693
$y=3900
+$w=414 $h=600
MM12n 7 10 8 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5693
$y=3100
+$w=414 $h=600
MM13n 8 Clr Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5693
+$y=2300 $w=414 $h=600
MM14p 9 Clr Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=7293
+$y=5600 $w=414 $h=600
MM15p 4 CB 9 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $ $x=7293
+$y=4700 $w=414 $h=600
MM16p 10 4 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=7193
+$y=3400 $w=414 $h=600
MM17n 10 4 Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=7193
+$y=2600 $w=414 $h=600
MM18p 11 10 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=1393
+$y=5200 $w=414 $h=600
MM19p 12 CB 11 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=1393
+$y=4400 $w=414 $h=600
MM20An 12 Clr 15 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=1393
+$y=3600 $w=414 $h=600
MM20n 15 C 13 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=1393
+$y=2800 $w=414 $h=600
MM21n 13 10 Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=1393
+$y=2000 $w=414 $h=600
MM22p 17 Clr Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=3093
+$y=5200 $w=414 $h=600
MM23p 12 C 17 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=3093
+$y=4400 $w=414 $h=600
MM24n 12 CB 17 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=3093
+$y=3600 $w=414 $h=600
MM25Ap Q 17 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=5293
+$y=4400 $w=414 $h=600
MM25p 17 16 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=4493
+$y=5200 $w=414 $h=600
MM26An Q 17 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5293
+$y=3600 $w=414 $h=600
MM26n 17 Clr 14 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=4493
+$y=2800 $w=414 $h=600
MM27n 14 16 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3 u $ $x=4493
+$y=2000 $w=414 $h=600
MM28Ap QB 16 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=8193
+$y=4300 $w=414 $h=600
MM28p 16 12 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=6693
+$y=4400 $w=414 $h=600
MM29An QB 16 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $
$x=8193
+$y=3500 $w=414 $h=600
MM29n 16 12 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=6693
+$y=3600 $w=414 $h=600
.ends
.subckt INV A Out Gnd Vdd
*-------- Devices With SPICE.ORDER < 0.0 --------
* Design: Generic_250nm_LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
* Date: 5/30/2008 4:06:39 PM
* Revision: 13 $ $x=7600 $y=600 $w=3600 $h=1200
*-------- Devices With SPICE.ORDER == 0.0 --------
MM1n Out A Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=4593
+$y=2600 $w=414 $h=600
MM2p Out A Vdd Vdd PMOS25 W=3u L=250n M=2 AS=1.125p PS=3.75u AD=1.95p PD=7.3u $
+$x=4593 $y=3600 $w=414 $h=600
.ends

*-------- Devices With SPICE.ORDER == 0.0 --------

***** Top Level*****
XDFFC_1 clk N_1 N_2 D N_2 Gnd Vdd DFFC $ $x=3100 $y=3400 $w=800 $h=1000
XDFFC_2 D N_1 N_4 C N_4 Gnd Vdd DFFC $ $x=4900 $y=3400 $w=800 $h=1000
XDFFC_3 C N_1 N_5 B N_5 Gnd Vdd DFFC $ $x=6700 $y=3400 $w=800 $h=1000
XDFFC_4 B N_1 N_6 A N_6 Gnd Vdd DFFC $ $x=8700 $y=3400 $w=800 $h=1000
XINV_1 rst N_1 Gnd Vdd INV $ $x=2300 $y=4100 $w=600 $h=400

*-------- Devices With SPICE.ORDER > 0.0 --------

Vv1 Vdd Gnd DC 5 $ $x=800 $y=6000 $w=400 $h=600
Vv2 rst Gnd PULSE(0 5 0 1n 1n 95n 10u) $ $x=700 $y=3500 $w=400 $h=600
Vv3 clk Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=2200 $y=2700 $w=400 $h=600
.PRINT TRAN V(A) $ $x=9550 $y=4550 $w=300 $h=1500 $r=270
.PRINT TRAN V(B) $ $x=7950 $y=4450 $w=300 $h=1500 $r=270
.PRINT TRAN V(C) $ $x=5950 $y=4550 $w=300 $h=1500 $r=270
.PRINT TRAN V(clk) $ $x=1650 $y=2550 $w=300 $h=1500 $r=90
.PRINT TRAN V(D) $ $x=4250 $y=4450 $w=300 $h=1500 $r=270
.PRINT TRAN V(rst) $ $x=950 $y=4550 $w=1500 $h=300 $r=180
********* Simulation Settings - Analysis Section *********
.tran 1u 5u
********* Simulation Settings - Additional SPICE Commands *********
.end

RESULT:

Thus the 4 - bit counter is designed and verified successfully.

EXP.NO: 10
DESIGN AND SIMULATE A CMOS INVERTING AMPLIFIER
DATE:

AIM:
To perform the functional verification of a CMOS inverting amplifier circuit through
schematic entry.

FACILITIES REQUIRED AND PROCEDURE

a) Facilities required to do the experime nt

S.No. SOFTWARE REQUIREMENTS QUANTITY

1 S-Edit, W-Edit, T-Edit using Tanner Tool. 1

b) Procedure for doing the experiment

S.NO DETAILS OF THE STEP

1 Draw the schematic of CMOS inverting amplifier using S-edit

2 Perform Transient Analysis of CMOS inverting amplifier circuit

3 Obtain the spice code using T-edit

4 Obtain the output wave form from W-edit

c) THEORY:

CMOS Inverter consists of nMOS and pMOS transistor in series connected between VDD
and GND. The gate of the two transistors are shorted and connected to the input.

When the input to the inverter A = 0, nMOS transistor is OFF and pMOS transistor is ON.
The output is pull- up to VDD.

When the input A = 1, nMOS transistor is ON and pMOS transistor is OFF. The Output is
Pull-down to GND.
SCHEMATIC ENTRY:

OUTPUT WAVEFORM:
NETLIST:
SPICE export by: SEDIT 13.12

* Export time: Wed Dec 11 11:43:07 2019

* Design: adm705-1

* Cell: Cell3

* View: view0

* Export as: top- level cell

* Export mode: hierarchical

* Exclude .model: no

* Exclude .end: no

* Expand paths: yes

* Wrap lines: no

* Root path: C:\Documents and Settings\Administrator\Desktop\adm705-1

* Exclude globalpins: no

* Control property name: SPICE

********* Simulation Settings - General section *********

.lib "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools

v13.1\Libraries\Models\Generic_025.lib" TT

********* Simulation Settings - Parameters and SPICE Options *********

*-------- Devices: SPICE.ORDER > 0 --------

MNMOS_1 Out N_2 Gnd N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MPMOS_1 Out N_2 Vdd N_3 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

VVoltageSource_1 Vdd Gnd DC 5

VVoltageSource_2 N_2 Gnd PULSE(0 5 0 5n 5n 95n 200n)

.PRINT TRAN V(Out)

.PRINT TRAN V(N_2)

********* Simulation Settings - Analysis section *********

.tran 350ns 500ns

.dc lin source VVoltageSource_1 0 5 0.5

.print dc v(MNMOS_1,Gnd)

********* Simulation Settings - Additional SPICE commands *********

.end

RESULT:

Thus the functional verification of a CMOS inverting amplifier circuit is designed and simulated successfully.
EXP.NO: 11(a)
DESIGN AND SIMULATION OF COMMON SOURCE AMPLIFIER
DATE:

AIM:
To perform the Design and Simulation of Common Source Amplifier circuit through
schematic entry.

FACILITIES REQUIRED AND PROCEDURE

a) Facilities required to do the experime nt

S.No. SOFTWARE REQUIREMENTS QUANTITY

1 S-Edit, W-Edit, T-Edit using Tanner Tool. 1

b) Procedure for doing the experiment

S.NO DETAILS OF THE STEP

1 Draw the schematic of Common Source Amplifier using S-edit

2 Perform Transient Analysis of Common Source Amplifier circuit

3 Obtain the spice code using T-edit

4 Obtain the output wave form from W-edit

c) THEORY:

In electronics, a common-source amplifier is one of three basic single-stage field-effect transistor

(FET) amplifier topologies, typically used as a voltage or transconductance amplifier. The easiest way
to tell if a FET is common source, common drain, orcommon gate is to examine where the signal
enters and leaves. The remaining terminal is what is known as "common". In this example, the signal
enters the gate, and exits the drain. The only terminal remaining is the source. This is a common-
source FET circuit. The analogous bipolar junction transistor circuit is the common-emitter amplifier.

The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a voltage

amplifier. (See classification of amplifiers).
As a transconductance amplifier, the input voltage is seen as modulating the current going to the load.
As a voltage amplifier, input voltage modulates the amount of current flowing through the FET,
changing the voltage across the output resistance according to Ohm's law. However, the FET device's
output resistance typically is not high enough for a reasonable transconductance amplifier (ideally
infinite), nor low enough for a decent voltage amplifier (ideally zero). Another major drawback is the
amplifier's limited high- frequency response.

SCHEMATIC ENTRY:

OUTPUT WAVEFORM:
NETLIST:

********* Simulation Settings - General Section *********

.lib "C:\Documents and Settings\ece01\My Documents\Tanner EDA\Tanner Tools
v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" TT
*************** Subcircuits *****************
.subckt DFFC Clk Clr Data Q QB Gnd Vdd
*-------- Devices With SPICE.ORDER < 0.0 --------
* Design: Generic_250nm_LogicGates / Cell: DFFC / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: D Flip-Flop with Clear
* Date: 10/15/2008 12:04:43 PM
* Revision: 144 $ $x=7600 $y=600 $w=3600 $h=1200
* Design: Generic_250nm_LogicGates / Cell: DFFC / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: D Flip-Flop with Clear
* Date: 10/15/2008 12:04:43 PM
* Revision: 144 $ $x=7600 $y=600 $w=3600 $h=1200

*-------- Devices With SPICE.ORDER == 0.0 --------

MM1p CB Clk Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=1293
+$y=1800 $w=414 $h=600
MM2n CB Clk Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=1293
+$y=1000 $w=414 $h=600
MM3p C CB Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $ $x=2693
+$y=1800 $w=414 $h=600
MM4n C CB Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=2693
$y=1000
+$w=414 $h=600
MM5p 3 Data Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=3993
+$y=5600 $w=414 $h=600
MM6p 4 C 3 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $ $x=3993
+$y=4700 $w=414 $h=600
MM7n 4 CB 5 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=3993
$y=3900
+$w=414 $h=600
MM8n 5 Data Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=3993
+$y=3100 $w=414 $h=600
MM9p 6 10 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=5693
+$y=5600 $w=414 $h=600
MM10p 4 CB 6 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=6107
+$y=4700 $w=414 $h=600 $m
MM11n 4 C 7 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5693
$y=3900
+$w=414 $h=600
MM12n 7 10 8 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5693
$y=3100
+$w=414 $h=600
MM13n 8 Clr Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5693
+$y=2300 $w=414 $h=600
MM14p 9 Clr Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=7293
+$y=5600 $w=414 $h=600
MM15p 4 CB 9 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=7293
+$y=4700 $w=414 $h=600
MM16p 10 4 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=7193
+$y=3400 $w=414 $h=600
MM17n 10 4 Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=7193
+$y=2600 $w=414 $h=600
MM18p 11 10 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=1393
+$y=5200 $w=414 $h=600
MM19p 12 CB 11 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=1393
+$y=4400 $w=414 $h=600
MM20An 12 Clr 15 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $
$x=1393
+$y=3600 $w=414 $h=600
MM20n 15 C 13 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=1393
+$y=2800 $w=414 $h=600
MM21n 13 10 Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=1393
+$y=2000 $w=414 $h=600
MM22p 17 Clr Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=3093
+$y=5200 $w=414 $h=600
MM23p 12 C 17 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=3093
+$y=4400 $w=414 $h=600
MM24n 12 CB 17 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=3093
+$y=3600 $w=414 $h=600
MM25Ap Q 17 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=5293
+$y=4400 $w=414 $h=600
MM25p 17 16 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=4493
+$y=5200 $w=414 $h=600
MM26An Q 17 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5293
+$y=3600 $w=414 $h=600
MM26n 17 Clr 14 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=4493
+$y=2800 $w=414 $h=600
MM27n 14 16 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3 u $ $x=4493
+$y=2000 $w=414 $h=600
MM28Ap QB 16 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=8193
+$y=4300 $w=414 $h=600
MM28p 16 12 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=6693
+$y=4400 $w=414 $h=600
MM29An QB 16 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $
$x=8193
+$y=3500 $w=414 $h=600
MM29n 16 12 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=6693
+$y=3600 $w=414 $h=600
.ends
.subckt INV A Out Gnd Vdd
*-------- Devices With SPICE.ORDER < 0.0 --------
* Design: Generic_250nm_LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
* Date: 5/30/2008 4:06:39 PM
* Revision: 13 $ $x=7600 $y=600 $w=3600 $h=1200
*-------- Devices With SPICE.ORDER == 0.0 --------
MM1n Out A Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=4593
+$y=2600 $w=414 $h=600
MM2p Out A Vdd Vdd PMOS25 W=3u L=250n M=2 AS=1.125p PS=3.75u AD=1.95p PD=7.3u $
+$x=4593 $y=3600 $w=414 $h=600
.ends

*-------- Devices With SPICE.ORDER == 0.0 --------

***** Top Level*****
XDFFC_1 clk N_1 N_2 D N_2 Gnd Vdd DFFC $ $x=3100 $y=3400 $w=800 $h=1000
XDFFC_2 D N_1 N_4 C N_4 Gnd Vdd DFFC $ $x=4900 $y=3400 $w=800 $h=1000
XDFFC_3 C N_1 N_5 B N_5 Gnd Vdd DFFC $ $x=6700 $y=3400 $w=800 $h=1000
XDFFC_4 B N_1 N_6 A N_6 Gnd Vdd DFFC $ $x=8700 $y=3400 $w=800 $h=1000
XINV_1 rst N_1 Gnd Vdd INV $ $x=2300 $y=4100 $w=600 $h=400

*-------- Devices With SPICE.ORDER > 0.0 --------

Vv1 Vdd Gnd DC 5 $ $x=800 $y=6000 $w=400 $h=600
Vv2 rst Gnd PULSE(0 5 0 1n 1n 95n 10u) $ $x=700 $y=3500 $w=400 $h=600
Vv3 clk Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=2200 $y=2700 $w=400 $h=600
.PRINT TRAN V(A) $ $x=9550 $y=4550 $w=300 $h=1500 $r=270
.PRINT TRAN V(B) $ $x=7950 $y=4450 $w=300 $h=1500 $r=270
.PRINT TRAN V(C) $ $x=5950 $y=4550 $w=300 $h=1500 $r=270
.PRINT TRAN V(clk) $ $x=1650 $y=2550 $w=300 $h=1500 $r=90
.PRINT TRAN V(D) $ $x=4250 $y=4450 $w=300 $h=1500 $r=270
.PRINT TRAN V(rst) $ $x=950 $y=4550 $w=1500 $h=300 $r=180
********* Simulation Settings - Analysis Section *********
.tran 1u 5u
********* Simulation Settings - Additional SPICE Commands *********
.end

RESULT:

Thus the Common Source Amplifier is designed and simulated successfully.

EXP.NO: 11(b)
DESIGN AND SIMULATION OF COMMON DRAIN AMPLIFIER
DATE:

AIM:
To perform the Design and Simulation of Common drain amplifier circuit through schematic
entry.

FACILITIES REQUIRED AND PROCEDURE

a) Facilities required to do the experime nt

S.No. SOFTWARE REQUIREMENTS QUANTITY

1 S-Edit, W-Edit, T-Edit using Tanner Tool. 1

b) Procedure for doing the experiment

S.NO DETAILS OF THE STEP

1 Draw the schematic of Common drain amplifier using S-edit

2 Perform Transient Analysis of Common drain amplifier circuit

3 Obtain the spice code using T-edit

4 Obtain the output wave form from W-edit

c) THEORY:

Common drain amplifier is a source follower or buffer amplifier circuit using a MOSFET. The output
is simply equal to the input minus about 2.2V. The advantage of this circuit is that the MOSFET can
provide current and power gain; the MOSFET draws no current from the input. It provides low output
impedance to any circuit using the output of the follower, meaning that the output will not drop under
load.Its output impedance is not as low as that of an emitter follower using a bipolar transistor (as you
can verify by connecting a resistor from the output to -15V), but it has the advantage that the input
impedance is infinite.The MOSFET is in saturation, so the current across it is determined by the gate-
source voltage. Since a current source keeps the current constant, the gate-source voltage is also
constant.
SCHEMATIC ENTRY:

OUTPUT WAVEFORM:
NETLIST:

********* Simulation Settings - General Section *********

.lib "C:\Documents and Settings\ece01\My Documents\Tanner EDA\Tanner Tools
v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" TT
*************** Subcircuits *****************
.subckt DFFC Clk Clr Data Q QB Gnd Vdd
*-------- Devices With SPICE.ORDER < 0.0 --------
* Design: Generic_250nm_LogicGates / Cell: DFFC / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: D Flip-Flop with Clear
* Date: 10/15/2008 12:04:43 PM
* Revision: 144 $ $x=7600 $y=600 $w=3600 $h=1200
* Design: Generic_250nm_LogicGates / Cell: DFFC / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: D Flip-Flop with Clear
* Date: 10/15/2008 12:04:43 PM
* Revision: 144 $ $x=7600 $y=600 $w=3600 $h=1200

*-------- Devices With SPICE.ORDER == 0.0 --------

MM1p CB Clk Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=1293
+$y=1800 $w=414 $h=600
MM2n CB Clk Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=1293
+$y=1000 $w=414 $h=600
MM3p C CB Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $ $x=2693
+$y=1800 $w=414 $h=600
MM4n C CB Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=2693
$y=1000
+$w=414 $h=600
MM5p 3 Data Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=3993
+$y=5600 $w=414 $h=600
MM6p 4 C 3 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $ $x=3993
+$y=4700 $w=414 $h=600
MM7n 4 CB 5 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=3993
$y=3900
+$w=414 $h=600
MM8n 5 Data Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=3993
+$y=3100 $w=414 $h=600
MM9p 6 10 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=5693
+$y=5600 $w=414 $h=600
MM10p 4 CB 6 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=6107
+$y=4700 $w=414 $h=600 $m
MM11n 4 C 7 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5693
$y=3900
+$w=414 $h=600
MM12n 7 10 8 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5693
$y=3100
+$w=414 $h=600
MM13n 8 Clr Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5693
+$y=2300 $w=414 $h=600
MM14p 9 Clr Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=7293
+$y=5600 $w=414 $h=600
MM15p 4 CB 9 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=7293
+$y=4700 $w=414 $h=600
MM16p 10 4 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=7193
+$y=3400 $w=414 $h=600
MM17n 10 4 Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=7193
+$y=2600 $w=414 $h=600
MM18p 11 10 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=1393
+$y=5200 $w=414 $h=600
MM19p 12 CB 11 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=1393
+$y=4400 $w=414 $h=600
MM20An 12 Clr 15 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $
$x=1393
+$y=3600 $w=414 $h=600
MM20n 15 C 13 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=1393
+$y=2800 $w=414 $h=600
MM21n 13 10 Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=1393
+$y=2000 $w=414 $h=600
MM22p 17 Clr Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=3093
+$y=5200 $w=414 $h=600
MM23p 12 C 17 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=3093
+$y=4400 $w=414 $h=600
MM24n 12 CB 17 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=3093
+$y=3600 $w=414 $h=600
MM25Ap Q 17 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=5293
+$y=4400 $w=414 $h=600
MM25p 17 16 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=4493
+$y=5200 $w=414 $h=600
MM26An Q 17 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5293
+$y=3600 $w=414 $h=600
MM26n 17 Clr 14 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=4493
+$y=2800 $w=414 $h=600
MM27n 14 16 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3 u $ $x=4493
+$y=2000 $w=414 $h=600
MM28Ap QB 16 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=8193
+$y=4300 $w=414 $h=600
MM28p 16 12 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=6693
+$y=4400 $w=414 $h=600
MM29An QB 16 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $
$x=8193
+$y=3500 $w=414 $h=600
MM29n 16 12 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=6693
+$y=3600 $w=414 $h=600
.ends
 .subckt INV A Out Gnd Vdd
*-------- Devices With SPICE.ORDER < 0.0 --------
* Design: Generic_250nm_LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
* Date: 5/30/2008 4:06:39 PM
* Revision: 13 $ $x=7600 $y=600 $w=3600 $h=1200
*-------- Devices With SPICE.ORDER == 0.0 --------
MM1n Out A Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=4593
+$y=2600 $w=414 $h=600
MM2p Out A Vdd Vdd PMOS25 W=3u L=250n M=2 AS=1.125p PS=3.75u AD=1.95p PD=7.3u $
+$x=4593 $y=3600 $w=414 $h=600
.ends

*-------- Devices With SPICE.ORDER == 0.0 --------

***** Top Level*****
XDFFC_1 clk N_1 N_2 D N_2 Gnd Vdd DFFC $ $x=3100 $y=3400 $w=800 $h=1000
XDFFC_2 D N_1 N_4 C N_4 Gnd Vdd DFFC $ $x=4900 $y=3400 $w=800 $h=1000
XDFFC_3 C N_1 N_5 B N_5 Gnd Vdd DFFC $ $x=6700 $y=3400 $w=800 $h=1000
XDFFC_4 B N_1 N_6 A N_6 Gnd Vdd DFFC $ $x=8700 $y=3400 $w=800 $h=1000
XINV_1 rst N_1 Gnd Vdd INV $ $x=2300 $y=4100 $w=600 $h=400

*-------- Devices With SPICE.ORDER > 0.0 --------

Vv1 Vdd Gnd DC 5 $ $x=800 $y=6000 $w=400 $h=600
Vv2 rst Gnd PULSE(0 5 0 1n 1n 95n 10u) $ $x=700 $y=3500 $w=400 $h=600
Vv3 clk Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=2200 $y=2700 $w=400 $h=600
.PRINT TRAN V(A) $ $x=9550 $y=4550 $w=300 $h=1500 $r=270
.PRINT TRAN V(B) $ $x=7950 $y=4450 $w=300 $h=1500 $r=270
.PRINT TRAN V(C) $ $x=5950 $y=4550 $w=300 $h=1500 $r=270
.PRINT TRAN V(clk) $ $x=1650 $y=2550 $w=300 $h=1500 $r=90
.PRINT TRAN V(D) $ $x=4250 $y=4450 $w=300 $h=1500 $r=270
.PRINT TRAN V(rst) $ $x=950 $y=4550 $w=1500 $h=300 $r=180
********* Simulation Settings - Analysis Section *********
.tran 1u 5u
********* Simulation Settings - Additional SPICE Commands *********
.end

RESULT:

Thus the Common Drain Amplifier is designed and simulated successfully.

EXP.NO: 11(c)
DESIGN AND SIMULATION OF COMMON GATE AMPLIFIER
DATE:

AIM:
To perform the Design and Simulation of Common drain amplifier circuit through schematic
entry.

FACILITIES REQUIRED AND PROCEDURE

a) Facilities required for doing the experiment

S.No. SOFTWARE REQUIREMENTS QUANTITY

1 S-Edit, W-Edit, T-Edit using Tanner Tool. 1

b) Procedure for doing the experiment

S.NO DETAILS OF THE STEP

1 Draw the schematic of Common drain amplifier using S-edit

2 Perform Transient Analysis of Common drain amplifier circuit

3 Obtain the spice code using T-edit

4 Obtain the output wave form from W-edit

c) THEORY:

In common source amplifier and source follower circuits, the input signal are applied to the gate of a
MOSFET. It is also possible to apply the input signal to the source terminal by keeping common
gate terminal. This type of amplifier is called as common gate amplifier.

Figure below shows the CG amplifier in which the input signal is sensed at the source terminal and
the output is produced at the drain terminal. The gate terminal is connected to V B i.e. dc potential
which will maintain the proper operating conditions.
SCHEMATIC ENTRY:

OUTPUT WAVEFORM:
NETLIST:

********* Simulation Settings - General Section *********

.lib "C:\Documents and Settings\ece01\My Documents\Tanner EDA\Tanner Tools
v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" TT
*************** Subcircuits *****************
.subckt DFFC Clk Clr Data Q QB Gnd Vdd
*-------- Devices With SPICE.ORDER < 0.0 --------
* Design: Generic_250nm_LogicGates / Cell: DFFC / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: D Flip-Flop with Clear
* Date: 10/15/2008 12:04:43 PM
* Revision: 144 $ $x=7600 $y=600 $w=3600 $h=1200
* Design: Generic_250nm_LogicGates / Cell: DFFC / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: D Flip-Flop with Clear
* Date: 10/15/2008 12:04:43 PM
* Revision: 144 $ $x=7600 $y=600 $w=3600 $h=1200

*-------- Devices With SPICE.ORDER == 0.0 --------

MM1p CB Clk Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=1293
+$y=1800 $w=414 $h=600
MM2n CB Clk Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=1293
+$y=1000 $w=414 $h=600
MM3p C CB Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $ $x=2693
+$y=1800 $w=414 $h=600
MM4n C CB Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=2693
$y=1000
+$w=414 $h=600
MM5p 3 Data Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=3993
+$y=5600 $w=414 $h=600
MM6p 4 C 3 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $ $x=3993
+$y=4700 $w=414 $h=600
MM7n 4 CB 5 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=3993
$y=3900
+$w=414 $h=600
MM8n 5 Data Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=3993
+$y=3100 $w=414 $h=600
MM9p 6 10 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=5693
+$y=5600 $w=414 $h=600
MM10p 4 CB 6 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=6107
+$y=4700 $w=414 $h=600 $m
MM11n 4 C 7 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5693
$y=3900
+$w=414 $h=600
MM12n 7 10 8 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5693
$y=3100
+$w=414 $h=600
MM13n 8 Clr Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5693
+$y=2300 $w=414 $h=600
MM14p 9 Clr Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=7293
+$y=5600 $w=414 $h=600
MM15p 4 CB 9 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=7293
+$y=4700 $w=414 $h=600
MM16p 10 4 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=7193
+$y=3400 $w=414 $h=600
MM17n 10 4 Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=7193
+$y=2600 $w=414 $h=600
MM18p 11 10 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=1393
+$y=5200 $w=414 $h=600
MM19p 12 CB 11 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=1393
+$y=4400 $w=414 $h=600
MM20An 12 Clr 15 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $
$x=1393
+$y=3600 $w=414 $h=600
MM20n 15 C 13 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=1393
+$y=2800 $w=414 $h=600
MM21n 13 10 Gnd 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=1393
+$y=2000 $w=414 $h=600
MM22p 17 Clr Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=3093
+$y=5200 $w=414 $h=600
MM23p 12 C 17 Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=3093
+$y=4400 $w=414 $h=600
MM24n 12 CB 17 0 NMOS25 W=1.50u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=3093
+$y=3600 $w=414 $h=600
MM25Ap Q 17 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=5293
+$y=4400 $w=414 $h=600
MM25p 17 16 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=4493
+$y=5200 $w=414 $h=600
MM26An Q 17 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=5293
+$y=3600 $w=414 $h=600
MM26n 17 Clr 14 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=4493
+$y=2800 $w=414 $h=600
MM27n 14 16 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3 u $ $x=4493
+$y=2000 $w=414 $h=600
MM28Ap QB 16 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=8193
+$y=4300 $w=414 $h=600
MM28p 16 12 Vdd Vdd PMOS25 W=3.00u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u $
$x=6693
+$y=4400 $w=414 $h=600
MM29An QB 16 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $
$x=8193
+$y=3500 $w=414 $h=600
MM29n 16 12 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=6693
+$y=3600 $w=414 $h=600
.ends
.subckt INV A Out Gnd Vdd
*-------- Devices With SPICE.ORDER < 0.0 --------
* Design: Generic_250nm_LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
* Date: 5/30/2008 4:06:39 PM
* Revision: 13 $ $x=7600 $y=600 $w=3600 $h=1200
*-------- Devices With SPICE.ORDER == 0.0 --------
MM1n Out A Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u $ $x=4593
+$y=2600 $w=414 $h=600
MM2p Out A Vdd Vdd PMOS25 W=3u L=250n M=2 AS=1.125p PS=3.75u AD=1.95p PD=7.3u $
+$x=4593 $y=3600 $w=414 $h=600
.ends

*-------- Devices With SPICE.ORDER == 0.0 --------

***** Top Level*****
XDFFC_1 clk N_1 N_2 D N_2 Gnd Vdd DFFC $ $x=3100 $y=3400 $w=800 $h=1000
XDFFC_2 D N_1 N_4 C N_4 Gnd Vdd DFFC $ $x=4900 $y=3400 $w=800 $h=1000
XDFFC_3 C N_1 N_5 B N_5 Gnd Vdd DFFC $ $x=6700 $y=3400 $w=800 $h=1000
XDFFC_4 B N_1 N_6 A N_6 Gnd Vdd DFFC $ $x=8700 $y=3400 $w=800 $h=1000
XINV_1 rst N_1 Gnd Vdd INV $ $x=2300 $y=4100 $w=600 $h=400

*-------- Devices With SPICE.ORDER > 0.0 --------

Vv1 Vdd Gnd DC 5 $ $x=800 $y=6000 $w=400 $h=600
Vv2 rst Gnd PULSE(0 5 0 1n 1n 95n 10u) $ $x=700 $y=3500 $w=400 $h=600
Vv3 clk Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=2200 $y=2700 $w=400 $h=600
.PRINT TRAN V(A) $ $x=9550 $y=4550 $w=300 $h=1500 $r=270
.PRINT TRAN V(B) $ $x=7950 $y=4450 $w=300 $h=1500 $r=270
.PRINT TRAN V(C) $ $x=5950 $y=4550 $w=300 $h=1500 $r=270
.PRINT TRAN V(clk) $ $x=1650 $y=2550 $w=300 $h=1500 $r=90
.PRINT TRAN V(D) $ $x=4250 $y=4450 $w=300 $h=1500 $r=270
.PRINT TRAN V(rst) $ $x=950 $y=4550 $w=1500 $h=300 $r=180
********* Simulation Settings - Analysis Section *********
.tran 1u 5u
********* Simulation Settings - Additional SPICE Commands *********
.end

RESULT:

Thus the Common Gate Amplifier is designed and simulated successfully.

EXP.NO: 12
DESIGN AND SIMULATION OF DIFFERENTIAL AMPLIFER
DATE:

AIM:
To calculate the gain, bandwidth and CMRR of a differential amplifier through schematic
entry using Tanner EDA tool.

FACILITIES REQUIRED AND PROCEDURE

a) Facilities required for doing the experiment

S.No. SOFTWARE REQUIREMENTS Quantity

1 S-Edit, W-Edit, T-Edit using Tanner Tool. 1

b) Procedure for doing the experiment

S.No Details of the step

Draw the schematic of differential amplifier using S-edit and generate the
1 Symbol.

Draw the schematic of differential amplifier circuit using the generated

2
Symbol.

3 Perform AC Analysis of the differential amplifier.

4 Obtain the frequency response from W-edit.

5 Obtain the spice code using T-edit.

PROCEDURE:
 Enter the schematic of differential amplifier using S-Edit.
 Perform AC Analysis of the differential amplifier.
 Go to „setup‟ in that select „spice simulation‟. Choose „ac analysis‟ and give the following
values.
 Set „Start frequency =10‟,‟ Stop frequency=10meg‟, „No. of frequency=25‟, „Sweep type =
dec‟. Click on „general‟ type and give path to Generic_250nm.lib.Then Click OK.
 RUN Simulation to get output.
 Obtain the frequency response from W-Edit.
 Obtain the spice code using T-Edit.
SCHEMATICDIAGRAM:

DIFFERENTIAL MODE:

DIFFERENTIAL MODE OUTPUT:

NETLIST:

********* Simulation Settings - General Section *********

.lib "C:\Documents and Settings\ece01\My Documents\Tanner EDA\Tanner Tools
v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" TT
*-------- Devices With SPICE.ORDER == 0.0 --------
***** Top Level*****
MNMOS_2_5v_1 N_1 N_3 N_4 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f
PD=4.3u
+$ $x=3793 $y=4300 $w=414 $h=600
MNMOS_2_5v_2 Out N_5 N_4 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u
+$ $x=6607 $y=4300 $w=414 $h=600 $m
MNMOS_2_5v_3 N_4 N_6 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f
PD=4.3u
+$ $x=5507 $y=3000 $w=414 $h=600 $m
MPMOS_2_5v_1 N_1 N_1 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p
PD=7.3u
+$ $x=4207 $y=5300 $w=414 $h=600 $m
MPMOS_2_5v_2 Out N_1 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p
PD=7.3u
+$ $x=6193 $y=5300 $w=414 $h=600

*-------- Devices With SPICE.ORDER > 0.0 --------

VV3 Vdd Gnd DC 5 $ $x=1200 $y=3800 $w=400 $h=600
VVbias N_6 Gnd DC 700m $ $x=6500 $y=2600 $w=400 $h=600
VV1 N_3 Gnd DC 0 AC 1 0 $ $x=3200 $y=2800 $w=400 $h=600
VV2 N_5 Gnd DC 0 AC 1 180 $ $x=7200 $y=2900 $w=400 $h=600
.PRINT AC Vdb(Out) $ $x=8350 $y=4050 $w=1500 $h=300
.PRINT AC Vp(Out) $ $x=8350 $y=4450 $w=1500 $h=300
.MEASURE AC AC_Measure_Gain_1 MAX vdb(Out) ON $ $x=8250 $y=5600 $w=1500 $h=200
.MEASURE AC AC_Measure_GainBandwidthProduct_1_Gain MAX vdb(Out) OFF
.MEASURE AC AC_Measure_GainBandwidthProduct_1_UGFreq WHEN Vdb(Out)=0 OFF
.MEASURE AC AC_Measure_GainBandwidthProduct_1
PARAM='AC_Measure_GainBandwidthProduct_1_Gain*AC_Measure_GainBandwidthProduct_1_
UGFreq' +ON $ $x=8250 $y=5200 $w=1500 $h=200
********* Simulation Settings - Analysis Section *********
.ac dec 25 10 10X
********* Simulation Settings - Additional SPICE Commands *********
.end
SCHEMATICDIAGRAM:

COMMON MODE:
COMMON MODE OUTPUT:

NETLIST:

********* Simulation Settings - General Section *********

.lib "C:\Documents and Settings\ece01\My Documents\Tanner EDA\Tanner Tools

v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib" TT

*-------- Devices With SPICE.ORDER == 0.0 --------

***** Top Level*****

MNMOS_2_5v_1 N_1 N_2 N_3 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f
PD=4.3u

+$ $x=3793 $y=4300 $w=414 $h=600

MNMOS_2_5v_2 Out N_2 N_3 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u

+$ $x=6607 $y=4300 $w=414 $h=600 $m

MNMOS_2_5v_3 N_3 N_5 Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f
PD=4.3u

+$ $x=5507 $y=3000 $w=414 $h=600 $m

MPMOS_2_5v_1 N_1 N_1 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p
PD=7.3u

+$ $x=4207 $y=5300 $w=414 $h=600 $m

MPMOS_2_5v_2 Out N_1 Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p
PD=7.3u

+$ $x=6193 $y=5300 $w=414 $h=600

*-------- Devices With SPICE.ORDER > 0.0 --------

VV3 Vdd Gnd DC 5 $ $x=1200 $y=3800 $w=400 $h=600

VVbias N_5 Gnd DC 700m $ $x=6500 $y=2600 $w=400 $h=600

VV1 N_2 Gnd DC 0 AC 1 0 $ $x=3200 $y=2800 $w=400 $h=600

.PRINT AC Vdb(Out) $ $x=8350 $y=4050 $w=1500 $h=300

.PRINT AC Vp(Out) $ $x=8350 $y=4450 $w=1500 $h=300

.MEASURE AC AC_Measure_Gain_1 MAX vdb(Out) ON $ $x=8250 $y=5600 $w=1500 $h=200

.MEASURE AC AC_Measure_GainBandwidthProduct_1_Gain MAX vdb(Out) OFF

.MEASURE AC AC_Measure_GainBandwidthProduct_1_UGFreq WHEN Vdb(Out)=0 OFF

.MEASURE AC AC_Measure_GainBandwidthProduct_1
PARAM='AC_Measure_GainBandwidthProduct_1_Gain*AC_Measure_GainBandwidthProduct_1_
UGFreq'

+ON $ $x=8250 $y=5200 $w=1500 $h=200

********* Simulation Settings - Analysis Section *********

.ac dec 25 10 10X

********* Simulation Settings - Additional SPICE Commands *********

.end
MEASUREMENT RESULT SUMMARY:

DIFFERNTIAL AMPLIFIER

COMMOM MODE DIFFERNTIAL MODE

AC_Measure_Gain Ac= Ad=

AC_Measure_Gain Bandwidth
Product

CMRR = Ad / Ac

RESULT

Thus the differential amplifier is designed and simulated successfully.

EXP: NO:
SIMULATION OF MULTIPLEXER AND DEMULTIPLEXER
DATE:

AIM:
To write a verilog program for multiplexer and demultiplexer to synthesize and simulate
using Xilinx software tool.

TOOLS REQUIRED:

SOFTWARE:
1. Xilinx ISE Design Suite 12.1

ALGORITHM:
1. Start the program.
2. Declare the input and output variables.
3. Declare the output as register data type.
4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code.
5. Terminate the program.

THEORY:

MULTIPLEXER

A Multiplexer is a Combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. The set of selection of a particular line is controlled
by selection lines. Normally there are 2 n input lines and n selection lines whose bit combinations
determine which input is selected.
The 4:1 MUX has four inputs I0, I1, I 2 and I 3 and select lines S0 and S1. The select lines s0
and s1 are decoded to select a particular AND gate. The outputs of the AND gates are applied to a
single OR gate that provides the one line output Y.
DEMULTIPLEXER

A Demultiplexer is a Combinational circuit that selects binary information from one of

input line and directs it to many output line. The set of selection of a particular output is controlled
by selection lines. Normally there are 1 input line and 2 n selection lines whose bit combinations
determine the output.
The 1:4 DEMUX has one input and select lines S0 and S1. The select lines s0 and s1 are
decoded to select a particular AND gate. The outputs of the AND gates provides the various line
output Y 1, Y2 , Y3 and Y4 .

PROCEDURE: (SAME FOR BOTH MUX & DEMUX)

Software part

1. Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of
PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double
clicking on the synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output can be observed using model sim.

PROGRAM:

Verilog code for Multiplexer

module mux4to1(s0,s1,t0,t1,t2,t3,out);
input s0,s1,t0,t1,t2,t3;
output out;
wire s0n,s1n,n1,n2,n3,n4;
not(s0n,s0);
not(s1n,s1);
and(n1,s0n,s1n,t0);
and(n2,s0,s1n,t1);
and(n3,s0n,s1,t2);
and(n4,s0,s1,t3);
or(out,n1,n2,n3,n4);
endmodule

SIMULATION REPORT: (FOR MUX)

VERILOG CODE FOR DEMULTIPLEXER

module demux1to4(s0,s1,s0n,s1n,in,t0,t1,t2,t3);
input s0,s1,in;
output s0n,s1n,t0,t1,t2,t3;
wire s0n,s1n;
not(s0n,s0);
not(s1n,s1);
and(t0,s0n,s1,in);
and(t1,s0n,s1n,in);
and(t2,s0,s1,in);
and(t3,s0,s1n,in);
endmodule
SIMULATION REPORT: (FOR DEMUX)

RESULT:

Thus the multiplexer and demultiplexer are designed and simulated successfully.
EXP: NO:
SIMULATION OF ENCODER AND DECODER
DATE:

AIM:
To write a verilog program for encoder and decoder to synthesize and simulate using Xilinx
software tool.

TOOLS REQUIRED:
SOFTWARE:
1. Xilinx ISE Design Suite 12.1

ALGORITHM:
1. Start the program.
2. Declare the input and output variables.
3. Declare the output as register data type.
4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code.
5. Terminate the program.

THEORY:

ENCODER
An Encoder is a digital circuit that has 2 n (or fewer) input lines and n output lines. The
output lines generate the binary the binary code corresponding to the input value. In encoder it is
assumed that only one input has a value of 1 at any given time.

DECODER
Discrete quantities of information are represented in digital systems by binary codes. A
binary code of n bits is capable of representing up to 2n distinct elements of coded information. A
decoder is a combinational circuit that converts binary information from n input lines to a
maximum of 2n unique output lines. If the n bit coded information unused combinations. The
decoder may have fewer than 2 n outputs.
The decoder are also called ‘n’ to ‘m’ line decoders, where is less than or equal to 2 n. Their
purpose is to generate the 2 n (or fewer) minterms of input variables. The name decoder is also used
in conjunction with other code converters such as BCD to SEVEN SEGMENT decoder.
PROCEDURE: (FOR ENCODER & DECODER)

Software part

1. Click on the Xilinx ISE Design Suite 12.1 or Xilinx Project navigator icon on the desktop of
PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double
clicking on the synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output can be observed using model sim.

PROGRAM:

Verilog code for Encoder

module encoder(a,b,c,d,s0,s1);
input a,b,c,d;
output s0,s1;
or(s0,c,d);
or(s1,b,d);
endmodule

SIMULATION REPORT: (FOR ENCODER)

VERILOG CODE FOR DECODEER

module decoder(s0,s1,t0,t1,t2,t3);
input s0,s1;
output t0,t1,t2,t3;
wire s0n,s1n;
not(s0n,s0);
not(s1n,s1);
and(t0,s0n,s1n);
and(t1,s0n,s1);
and(t2,s0,s1n);
and(t3,s0,s1);
endmodule

SIMULATION REPORT: (FOR DECODER)

RESULT:

Thus the encoder and decoder are designed and simulated successfully.
VIVA VOCE QUESTION &ANSWERS

1. What are four generations of Integration Circuits?

1) SSI (Small Scale Integration) 2)MSI (Medium Scale Integration)

3)LSI (Large Scale Integration) 4) VLSI (Very Large Scale Integration)

2)
2. Give the advantages of IC?

1) Size is less 2)High Speed 3)Less Power Dissipation

3. Give the variety of Integrated Circuits?

1) More Specialized Circuits 2) Application Specific Integrated Circuits(ASICs)

Systems-On-Chips

4. Give the basic process for IC fabrication ?

Silicon wafer Preparation, Epitaxial Growth, Oxidation, Photolithography, Diffusion

Ion Implantation, Isolation technique, Metallization, Assembly processing & Packaging

5. What are the various Silicon wafer Preparation?

Crystal growth & doping, Ingot trimming & grinding, Ingot slicing, Wafer polishing & etching,
Wafer cleaning.

6. Different types of oxidation?

Dry & Wet Oxidation

7. What is the transistors CMOS technology provides?

n-type transistors & p-type transistors.

8. What are the different layers in MOS transistors?

Drain , Source & Gate

9. What is Enhancement mode transistor?

The device that is normally cut-off with zero gate bias.

10. What is Depletion mode Device?

The Device that conduct with zero gate bias.

11. When the channel is said to be pinched –off?

If a large Vds is applied this voltage with deplete the Inversion layer .This Voltage
effectively pinches off the channel near the drain.

12. Give the different types of CMOS process?

p-well process, n-well process, Silicon-On-Insulator Process, Twin-
tub Process

13. What are the steps involved in twin-tub process?

Tub Formation, Thin-oxide Construction, Source & Drain Implantation, Contact cut
definition, Metallization.

14. What are the advantages of Silicon-on-Insulator process?

No Latch-up, Due to absence of bulks transistor structures are denser than bulk silicon.

15. Define Short Channel devices?

Transistors with Channel length less than 3- 5 microns are termed as Short channel

devices. With short channel devices the ratio between the lateral & vertical dimensions

are reduced. Non- Saturated Region Saturated Region

16. Define Threshold voltage in CMOS?

The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied

between the gate and the source of the MOS transistor below which the drain to source

current, IDS effectively drops to zero.

17. What is Body effect?

The threshold voltage VT is not a constant w. r. to the voltage difference between the

substrate and the source of MOS transistor. This effect is called substrate-bias effect or

body effect.

18. What is Verilog?

Verilog is a general purpose hardware descriptor language. It is similar in syntax

to the C programming language. It can be used to model a digital system at many

levels of abstraction ranging from the algorithmic level to the switch level.
19. What are the various modeling used in Verilog

1. Gate-level modeling 2. Data-flow modeling 3. Switch-level modeling 4. Behavioral modeling

20. What is the structural gate-level modeling?

Structural modeling describes a digital logic networks in terms of the components that make up the system.
Gate-level modeling is based on using primitive logic gates and specifying how they are wired together.

21. What is Switch-level modeling?

Verilog allows switch-level modeling that is based on the behavior of MOSFETs.Digital circuits at the
MOS-transistor level are described using the MOSFET switches.

22. What are identifiers?

Identifiers are names of modules, variables and other objects that we can reference in the design.
Identifiers consists of upper and lower case letters, digits 0 through 9, the underscore character(_) and the
dollar sign($). It must be a single group of characters.

Examples: A014, a ,b, in_o, s_out