### Generate Xilinx IP (Generate Xilinx IP) ###

### Synthesize - Vivado (Synthesize - Vivado) ###

WARNING: Default location for XILINX_VIVADO_HLS not found:

WARNING: Default location for XILINX_HLS not found:

****** Vivado v2021.1 (64-bit)

**** SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021
**** IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

# package require struct::list

# package require struct::set
# set_param synth.elaboration.rodinMoreOptions "rt::set_parameter max_loop_limit
1000000;"
# read_vhdl [glob *.\[vV\]\[hH\]\[dD\]]
# set_property top "toplevel_gen" [current_fileset]
# auto_detect_xpm
auto_detect_xpm: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak
= 1165.082 ; gain = 0.000
# if {[llength [glob -nocomplain *.\[xX\]\[dD\]\[cC\]]] > 0} {
# set CoreXDCFilesFH [open CoreXDCList.txt r]
# set xdc_files_xci [split [read $CoreXDCFilesFH] "\n"]
# close $CoreXDCFilesFH
# set xdc_files_all [glob *.\[xX\]\[dD\]\[cC\]]
# set explicit_synthesis_xdc_files {}
# set explicit_non_synthesis_xdc_files {}
# set xdc_files_not_from_xci [::struct::set difference $xdc_files_all
$xdc_files_xci]
# set xdc_files_source [::struct::set difference $xdc_files_not_from_xci
$explicit_non_synthesis_xdc_files]
# set xdc_files_source [::struct::set union $explicit_synthesis_xdc_files
$xdc_files_source]
# set xdc_files [read_xdc $xdc_files_source]
# foreach xdc_file $xdc_files_xci {
# if {[file exists $xdc_file]} {
# lappend xdc_files [read_xdc -ref [file rootname $xdc_file] $xdc_file]
# }
# }
# set_property PROCESSING_ORDER {LATE} [get_files $xdc_files]
# }
# read_edif [glob *.\[nN\]\[gG\]\[cC\]]
# read_edif [glob *.\[eE\]\[dD\]\[fFnN\]]
# read_edif [glob *.\[eE\]\[dD\]\[iI\]\[fF\]]
# set_msg_config -id "Synth 8-3431" -suppress
# synth_design -keep_equivalent_registers -top "toplevel_gen" -part
"xc7a100tcsg324-1" -flatten_hierarchy "full"
Command: synth_design -keep_equivalent_registers -top toplevel_gen -part
xc7a100tcsg324-1 -flatten_hierarchy full
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2
processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado
processes
INFO: [Synth 8-7075] Helper process launched with PID 7052
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory
(MB): peak = 1165.082 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_sdpram'
[C:/NIFPGA/programs/Vivado2021_1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8435]
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base'
[C:/NIFPGA/programs/Vivado2021_1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs
Vivado Synthesis to choose the memory primitive type. Depending on their values,
other XPM_MEMORY parameters may preclude the choice of certain memory primitive
types. Review XPM_MEMORY documentation and parameter values to understand any
limitations, or set MEMORY_PRIMITIVE to a different value.
[C:/NIFPGA/programs/Vivado2021_1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:490]
INFO: [Synth 8-6157] synthesizing module 'asym_bwe_bb'
[C:/NIFPGA/programs/Vivado2021_1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8067]
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base' (91#1)
[C:/NIFPGA/programs/Vivado2021_1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_sdpram' (92#1)
[C:/NIFPGA/programs/Vivado2021_1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:8435]
INFO: [Synth 8-638] synthesizing module 'CrioPassthroughSidebandController'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioPassthroughSidebandController.vhd:189]
INFO: [Synth 8-638] synthesizing module 'CrioSbSlotControl'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbSlotControl.vhd:162]
Parameter kEnableModPresenceOverride bound to: 1 - type: bool
Parameter kImportingOClk bound to: 0 - type: bool
Parameter kIsRsi bound to: 0 - type: bool
INFO: [Synth 8-638] synthesizing module 'CrioRunDoneToReqAck'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioRunDoneToReqAck.vhd:72]
INFO: [Synth 8-256] done synthesizing module 'CrioRunDoneToReqAck' (461#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioRunDoneToReqAck.vhd:72]
INFO: [Synth 8-256] done synthesizing module 'CrioSbSlotControl' (462#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbSlotControl.vhd:162]
INFO: [Synth 8-638] synthesizing module 'CrioSbLineControl'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbLineControl.vhd:221]
Parameter kControlSleep bound to: 1 - type: bool
Parameter kEnableBidirMode bound to: 0 - type: bool
INFO: [Synth 8-256] done synthesizing module 'CrioSbLineControl' (463#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbLineControl.vhd:221]
INFO: [Synth 8-638] synthesizing module 'CrioSbOutputEnableDelay'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbOutputEnableDelay.vhd:88]
Parameter kNumEnables bound to: 10 - type: integer
Parameter kClkMultiplier bound to: 1 - type: integer
INFO: [Synth 8-256] done synthesizing module 'CrioSbOutputEnableDelay' (464#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbOutputEnableDelay.vhd:88]
INFO: [Synth 8-638] synthesizing module 'CrioSbEngineArbiter'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbEngineArbiter.vhd:65]
Parameter kNumRequesters bound to: 3 - type: integer
Parameter kLowLatencyMode bound to: 0 - type: bool
INFO: [Synth 8-638] synthesizing module 'CrioArbSerializeAccess'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioArbSerializeAccess.vhd:50]
Parameter kNumAccessors bound to: 3 - type: integer
INFO: [Synth 8-638] synthesizing module 'CrioArbPowerOf2'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioArbPowerOf2.vhd:49]
Parameter kWidth bound to: 3 - type: integer
INFO: [Synth 8-256] done synthesizing module 'CrioArbPowerOf2' (465#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioArbPowerOf2.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'CrioArbSerializeAccess' (466#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioArbSerializeAccess.vhd:50]
INFO: [Synth 8-256] done synthesizing module 'CrioSbEngineArbiter' (467#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbEngineArbiter.vhd:65]
INFO: [Synth 8-256] done synthesizing module 'CrioPassthroughSidebandController'
(468#1) [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioPassthroughSidebandController.vhd:189]
INFO: [Synth 8-226] default block is never used
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/PkgCrioSideband.vhd:629]
INFO: [Synth 8-638] synthesizing module 'CrioSidebandEngineCore'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSidebandEngineCore.vhd:134]
INFO: [Synth 8-638] synthesizing module 'CrioSbEngineLogic'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbEngineLogic.vhd:124]
Parameter kEnableSpiPackets bound to: 0 - type: bool
INFO: [Synth 8-256] done synthesizing module 'CrioSbEngineLogic' (469#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbEngineLogic.vhd:124]
INFO: [Synth 8-638] synthesizing module 'CrioSbPacketSender'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbPacketSender.vhd:70]
Parameter kEnableSpiPackets bound to: 0 - type: bool
WARNING: [Synth 8-5639] ignoring null variable initialization
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/PkgCrioSideband.vhd:461]
INFO: [Synth 8-256] done synthesizing module 'CrioSbPacketSender' (470#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbPacketSender.vhd:70]
INFO: [Synth 8-638] synthesizing module 'CrioSbSerialTransmitter'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbSerialTransmitter.vhd:115]
INFO: [Synth 8-256] done synthesizing module 'CrioSbSerialTransmitter' (471#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbSerialTransmitter.vhd:115]
INFO: [Synth 8-638] synthesizing module 'CrioSbPacketReceiver'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbPacketReceiver.vhd:71]
Parameter kTestbench bound to: 0 - type: bool
Parameter kEnableSpiPackets bound to: 0 - type: bool
INFO: [Synth 8-256] done synthesizing module 'CrioSbPacketReceiver' (472#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbPacketReceiver.vhd:71]
INFO: [Synth 8-638] synthesizing module 'CrioSbSerialReceiver'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbSerialReceiver.vhd:107]
Parameter DDR_CLK_EDGE bound to: OPPOSITE_EDGE - type: string
Parameter INIT_Q1 bound to: 1'b0
Parameter INIT_Q2 bound to: 1'b0
Parameter SRTYPE bound to: ASYNC - type: string
INFO: [Synth 8-3491] module 'IDDR' declared at
'C:/NIFPGA/programs/Vivado2021_1/scripts/rt/data/unisim_comp.v:53631' bound to
instance 'IDDRx' of component 'IDDR'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbSerialReceiver.vhd:154]
INFO: [Synth 8-6157] synthesizing module 'IDDR'
[C:/NIFPGA/programs/Vivado2021_1/scripts/rt/data/unisim_comp.v:53631]
Parameter DDR_CLK_EDGE bound to: OPPOSITE_EDGE - type: string
Parameter INIT_Q1 bound to: 1'b0
Parameter INIT_Q2 bound to: 1'b0
Parameter SRTYPE bound to: ASYNC - type: string
INFO: [Synth 8-6155] done synthesizing module 'IDDR' (473#1)
[C:/NIFPGA/programs/Vivado2021_1/scripts/rt/data/unisim_comp.v:53631]
INFO: [Synth 8-638] synthesizing module 'CrioSbDataCaptureDataPath'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbDataCaptureDataPath.vhd:57]
INFO: [Synth 8-256] done synthesizing module 'CrioSbDataCaptureDataPath' (474#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbDataCaptureDataPath.vhd:57]
INFO: [Synth 8-256] done synthesizing module 'CrioSbSerialReceiver' (475#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbSerialReceiver.vhd:107]
INFO: [Synth 8-256] done synthesizing module 'CrioSidebandEngineCore' (476#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSidebandEngineCore.vhd:134]
INFO: [Synth 8-638] synthesizing module 'CrioSidebandClkResCore'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSidebandClkResCore.vhd:169]
INFO: [Synth 8-113] binding component instance 'SbClk80InBufIo' to cell 'BUFIO'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSidebandClkResCore.vhd:308]
Parameter BUFR_DIVIDE bound to: BYPASS - type: string
INFO: [Synth 8-113] binding component instance 'SbClk80InBufR' to cell 'BUFR'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSidebandClkResCore.vhd:313]
INFO: [Synth 8-638] synthesizing module 'CrioSbRxSpiSlave'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbRxSpiSlave.vhd:78]
Parameter kSbRxSpiMessageLength bound to: 4 - type: integer
INFO: [Synth 8-256] done synthesizing module 'CrioSbRxSpiSlave' (535#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbRxSpiSlave.vhd:78]
INFO: [Synth 8-638] synthesizing module 'CrioSbShiftReg'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbShiftReg.vhd:47]
Parameter kInitialValue bound to: 4'b1100
Parameter INIT bound to: 2'b10
INFO: [Synth 8-3491] module 'LUT1' declared at
'C:/NIFPGA/programs/Vivado2021_1/scripts/rt/data/unisim_comp.v:59102' bound to
instance 'delay1' of component 'LUT1'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbShiftReg.vhd:84]
INFO: [Synth 8-6157] synthesizing module 'LUT1'
[C:/NIFPGA/programs/Vivado2021_1/scripts/rt/data/unisim_comp.v:59102]
Parameter INIT bound to: 2'b10
INFO: [Synth 8-6155] done synthesizing module 'LUT1' (536#1)
[C:/NIFPGA/programs/Vivado2021_1/scripts/rt/data/unisim_comp.v:59102]
Parameter INIT bound to: 2'b10
INFO: [Synth 8-3491] module 'LUT1' declared at
'C:/NIFPGA/programs/Vivado2021_1/scripts/rt/data/unisim_comp.v:59102' bound to
instance 'delay2' of component 'LUT1'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbShiftReg.vhd:88]
Parameter INIT bound to: 2'b10
INFO: [Synth 8-3491] module 'LUT1' declared at
'C:/NIFPGA/programs/Vivado2021_1/scripts/rt/data/unisim_comp.v:59102' bound to
instance 'delay3' of component 'LUT1'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbShiftReg.vhd:92]
Parameter INIT bound to: 2'b10
INFO: [Synth 8-3491] module 'LUT1' declared at
'C:/NIFPGA/programs/Vivado2021_1/scripts/rt/data/unisim_comp.v:59102' bound to
instance 'delay4' of component 'LUT1'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbShiftReg.vhd:96]
INFO: [Synth 8-256] done synthesizing module 'CrioSbShiftReg' (537#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbShiftReg.vhd:47]
Parameter kSim bound to: 0 - type: bool
INFO: [Synth 8-3491] module 'CrioSbDataCaptureControl' declared at
'C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbDataCaptureControl.vhd:56' bound to instance
'CrioSbDataCaptureControlx' of component 'CrioSbDataCaptureControl'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSidebandClkResCore.vhd:549]
INFO: [Synth 8-638] synthesizing module 'CrioSbDataCaptureControl'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbDataCaptureControl.vhd:83]
Parameter kSim bound to: 0 - type: bool
INFO: [Synth 8-638] synthesizing module 'CrioSymmetricDelay'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSymmetricDelay.vhd:32]
Parameter INIT bound to: 2'b10
INFO: [Synth 8-3491] module 'LUT1' declared at
'C:/NIFPGA/programs/Vivado2021_1/scripts/rt/data/unisim_comp.v:59102' bound to
instance 'delay1' of component 'LUT1'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSymmetricDelay.vhd:65]
Parameter INIT bound to: 2'b10
INFO: [Synth 8-3491] module 'LUT1' declared at
'C:/NIFPGA/programs/Vivado2021_1/scripts/rt/data/unisim_comp.v:59102' bound to
instance 'delay2' of component 'LUT1'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSymmetricDelay.vhd:69]
 Parameter INIT bound to: 2'b10
INFO: [Synth 8-3491] module 'LUT1' declared at
'C:/NIFPGA/programs/Vivado2021_1/scripts/rt/data/unisim_comp.v:59102' bound to
instance 'delay3' of component 'LUT1'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSymmetricDelay.vhd:73]
Parameter INIT bound to: 2'b10
INFO: [Synth 8-3491] module 'LUT1' declared at
'C:/NIFPGA/programs/Vivado2021_1/scripts/rt/data/unisim_comp.v:59102' bound to
instance 'delay4' of component 'LUT1'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSymmetricDelay.vhd:77]
INFO: [Synth 8-256] done synthesizing module 'CrioSymmetricDelay' (538#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSymmetricDelay.vhd:32]
INFO: [Synth 8-256] done synthesizing module 'CrioSbDataCaptureControl' (539#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbDataCaptureControl.vhd:83]
INFO: [Synth 8-256] done synthesizing module 'CrioSidebandClkResCore' (540#1)
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSidebandClkResCore.vhd:169]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:19 . Memory
(MB): peak = 1263.441 ; gain = 98.359
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:20
. Memory (MB): peak = 1263.441 ; gain = 98.359
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:20 .
Memory (MB): peak = 1263.441 ; gain = 98.359
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory
(MB): peak = 1272.383 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 18 Unisim elements for replacement
CRITICAL WARNING: [Netlist 29-346] The CLKOUT3_PHASE for PLLE2_ADV
(TopIo_ClockGenPll) is being adjusted from 285.5 to 283.5. The CLKOUT3_PHASE value
needs to be in increments of 1/56 the FVCO and/or increments depending on
CLKOUT_DIVIDE. Refer to the Clocking Resources User Guide of the device family for
details.
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints

Initializing timing engine
Parsing XDC File [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc]
WARNING: [Vivado 12-2489] -waveform contains time 6.247500 which will be rounded to
6.248 to ensure it is an integer multiple of 1 picosecond
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:334]
INFO: [Timing 38-2] Deriving generated clocks
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:351]
WARNING: [Vivado 12-508] No pins matched
'*/IoPort2Topx/LvdsSerializerx/ClockOSERDES/OQ'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:377]
WARNING: [Vivado 12-646] clock 'IoTxClockOut' not found.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:380]
WARNING: [Vivado 12-646] clock 'IoTxClockOut' not found.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:381]
WARNING: [Vivado 12-646] clock 'IoTxClockOut' not found.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:382]
WARNING: [Vivado 12-646] clock 'IoTxClockOut' not found.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:383]
WARNING: [Vivado 12-627] No clocks matched 'IoTxClockOut'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:386]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or
'create_generated_clock' command to create clocks.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:386]
WARNING: [Vivado 12-627] No clocks matched 'IoTxClockOut'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:387]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or
'create_generated_clock' command to create clocks.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:387]
WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not
supported by synthesis. The constraint will not be passed to synthesis.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:388]
WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not
supported by synthesis. The constraint will not be passed to synthesis.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:389]
WARNING: [Vivado 12-627] No clocks matched 'IoTxClockOut'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:394]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or
'create_generated_clock' command to create clocks.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:394]
WARNING: [Vivado 12-627] No clocks matched 'IoTxClockOut'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:395]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or
'create_generated_clock' command to create clocks.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:395]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not
supported by synthesis. The constraint will not be passed to synthesis.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:396]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not
supported by synthesis. The constraint will not be passed to synthesis.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:397]
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as
objects, only virtual clock 'IoRxClockVirt' will be created. If you don't want
this, please specify pin(s)/ports(s)/net(s) as objects to the command.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:400]
WARNING: [Vivado 12-508] No pins matched
'*/IoPort2Topx/ClockGenx/RxMmcm.RxMmcm/CLKIN1'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:402]
WARNING: [Vivado 12-508] No pins matched
'*/IoPort2Topx/ClockGenx/RxMmcm.RxMmcm/CLKOUT0'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:402]
WARNING: [Vivado 12-627] No clocks matched 'IoRxClockShifted'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:426]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or
'create_generated_clock' command to create clocks.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:426]
WARNING: [Vivado 12-627] No clocks matched 'IoRxClockShifted'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:427]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or
'create_generated_clock' command to create clocks.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:427]
WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not
supported by synthesis. The constraint will not be passed to synthesis.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:428]
WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not
supported by synthesis. The constraint will not be passed to synthesis.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:429]
WARNING: [Vivado 12-508] No pins matched '*CrioSidebandClkRes*/hStClk80Dup_reg/C'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:447]
WARNING: [Vivado 12-180] No cells matched
'window/theVI/CrioSidebandClkRes8/CrioSidebandClkResCorex/hReset_reg*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:471]
WARNING: [Vivado 12-180] No cells matched
'window/theVI/CrioSidebandClkRes8/CrioSidebandClkResCorex/hStClk80_reg*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:473]
WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not
supported by synthesis. The constraint will not be passed to synthesis.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:489]
WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not
supported by synthesis. The constraint will not be passed to synthesis.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:490]
WARNING: [Vivado 12-627] No clocks matched 'SidebandClk320Out'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:492]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or
'create_generated_clock' command to create clocks.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:492]
WARNING: [Vivado 12-627] No clocks matched 'SidebandClk320Out'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:492]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or
'create_generated_clock' command to create clocks.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:492]
WARNING: [Vivado 12-627] No clocks matched 'SidebandClk320Out'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:493]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or
'create_generated_clock' command to create clocks.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:493]
WARNING: [Vivado 12-180] No cells matched
'*Clk40ToInterface/BlkOut.SyncIReset/c1ResetFastLclx*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:556]
WARNING: [Vivado 12-180] No cells matched '*Clk40ToInterface/BlkIn.iPushTogglex*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:557]
WARNING: [Vivado 12-180] No cells matched '*Clk40ToInterface/BlkIn.i*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:558]
WARNING: [Vivado 12-180] No cells matched '*Clk40ToInterface/BlkOut.o*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:559]
WARNING: [Vivado 12-180] No cells matched
'*Clk40ToInterface/BlkOut.SyncIReset/c2ResetFe_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:560]
WARNING: [Vivado 12-180] No cells matched '*Clk40ToInterface/Blk*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:561]
WARNING: [Vivado 12-180] No cells matched '*Clk40ToInterface/Blk*_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:562]
WARNING: [Vivado 12-180] No cells matched '*Clk40ToInterface/BlkIn.iPushToggle*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:563]
WARNING: [Vivado 12-180] No cells matched
'*Clk40ToInterface/BlkOut.oPushToggle0_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:564]
WARNING: [Vivado 12-180] No cells matched '*Clk40ToInterface/*oPushToggle0_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:565]
WARNING: [Vivado 12-180] No cells matched '*Clk40ToInterface/*oPushToggle1*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:566]
WARNING: [Vivado 12-180] No cells matched '*Clk40ToInterface/*iRdyPushToggle_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:567]
WARNING: [Vivado 12-180] No cells matched '*Clk40ToInterface/*iRdyPushToggle*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:568]
WARNING: [Vivado 12-180] No cells matched
'*Clk40ToInterface/BlkOut.SyncIReset*c1*_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:569]
WARNING: [Vivado 12-180] No cells matched
'*Clk40ToInterface/BlkOut.SyncIReset*c1*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:570]
WARNING: [Vivado 12-180] No cells matched
'*Clk40ToInterface/BlkOut.SyncOReset*c1*_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:571]
WARNING: [Vivado 12-180] No cells matched
'*Clk40ToInterface/BlkOut.SyncOReset*c1*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:572]
WARNING: [Vivado 12-180] No cells matched
'*Clk40ToInterface/BlkOut.SyncIReset*c2*_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:573]
WARNING: [Vivado 12-180] No cells matched
'*Clk40ToInterface/BlkOut.SyncIReset*c2*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:574]
WARNING: [Vivado 12-180] No cells matched
'*Clk40ToInterface/BlkOut.SyncOReset*c2*_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:575]
WARNING: [Vivado 12-180] No cells matched
'*Clk40ToInterface/BlkOut.SyncOReset*c2*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:576]
WARNING: [Vivado 12-180] No cells matched
'*Clk40FromInterface/BlkOut.SyncIReset/c1ResetFastLclx*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:577]
WARNING: [Vivado 12-180] No cells matched
'*Clk40FromInterface/BlkIn.iPushTogglex*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:578]
WARNING: [Vivado 12-180] No cells matched '*Clk40FromInterface/BlkIn.i*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:579]
WARNING: [Vivado 12-180] No cells matched '*Clk40FromInterface/BlkOut.o*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:580]
WARNING: [Vivado 12-180] No cells matched
'*Clk40FromInterface/BlkOut.SyncIReset/c2ResetFe_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:581]
WARNING: [Vivado 12-180] No cells matched '*Clk40FromInterface/Blk*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:582]
WARNING: [Vivado 12-180] No cells matched '*Clk40FromInterface/Blk*_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:583]
WARNING: [Vivado 12-180] No cells matched '*Clk40FromInterface/BlkIn.iPushToggle*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:584]
WARNING: [Vivado 12-180] No cells matched
'*Clk40FromInterface/BlkOut.oPushToggle0_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:585]
WARNING: [Vivado 12-180] No cells matched '*Clk40FromInterface/*oPushToggle0_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:586]
WARNING: [Vivado 12-180] No cells matched '*Clk40FromInterface/*oPushToggle1*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:587]
WARNING: [Vivado 12-180] No cells matched
'*Clk40FromInterface/*iRdyPushToggle_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:588]
WARNING: [Vivado 12-180] No cells matched '*Clk40FromInterface/*iRdyPushToggle*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:589]
WARNING: [Vivado 12-180] No cells matched
'*Clk40FromInterface/BlkOut.SyncIReset*c1*_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:590]
WARNING: [Vivado 12-180] No cells matched
'*Clk40FromInterface/BlkOut.SyncIReset*c1*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:591]
WARNING: [Vivado 12-180] No cells matched
'*Clk40FromInterface/BlkOut.SyncOReset*c1*_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:592]
WARNING: [Vivado 12-180] No cells matched
'*Clk40FromInterface/BlkOut.SyncOReset*c1*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:593]
WARNING: [Vivado 12-180] No cells matched
'*Clk40FromInterface/BlkOut.SyncIReset*c2*_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:594]
WARNING: [Vivado 12-180] No cells matched
'*Clk40FromInterface/BlkOut.SyncIReset*c2*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:595]
WARNING: [Vivado 12-180] No cells matched
'*Clk40FromInterface/BlkOut.SyncOReset*c2*_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:596]
WARNING: [Vivado 12-180] No cells matched
'*Clk40FromInterface/BlkOut.SyncOReset*c2*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:597]
WARNING: [Vivado 12-180] No cells matched
'*n_bushold/*ShiftRegister/SyncBusReset/*iHoldSigInx/*FDCPEx'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:598]
WARNING: [Vivado 12-180] No cells matched
'*n_bushold/*ShiftRegister/SyncBusReset/*oHoldSigIn_msx/*FDCPEx'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:599]
WARNING: [Vivado 12-180] No cells matched
'*n_bushold/*ShiftRegister/SyncBusReset/*oLocalSigOutx/*FDCPEx'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:600]
WARNING: [Vivado 12-180] No cells matched
'*n_bushold/*ShiftRegister/SyncBusReset/*iSigOut_msx/*FDCPEx'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:601]
WARNING: [Vivado 12-180] No cells matched
'*n_bushold/*ShiftRegister/SyncBusReset/*oLocalSigOutCEx/*FDCPEx'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:602]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncBasex/
*iHoldSigInx/*FDCPEx'. [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:603]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncBasex/
*oHoldSigIn_msx/*FDCPEx'. [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:604]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncBasex/
*oLocalSigOutx/*FDCPEx'. [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:605]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncBasex/
*iSigOut_msx/*FDCPEx'. [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:606]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncBasex/
*oLocalSigOutCEx/*FDCPEx'. [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:607]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncBasex/
*iHoldSigInx/*FDCPEx'. [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:608]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncBasex/
*oHoldSigIn_msx/*FDCPEx'. [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:609]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncBasex/
*oLocalSigOutx/*FDCPEx'. [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:610]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncBasex/
*iSigOut_msx/*FDCPEx'. [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:611]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncBasex/
*oLocalSigOutCEx/*FDCPEx'. [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:612]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0*ClearControl*DoubleSyncBasex*iDlySigx/*FDCPEx'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:613]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0*ClearControl*DoubleSyncBasex*DoubleSyncAsyncInBasex/oSig_msx/
*FDCPEx'. [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:614]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0/TypeSelector/GenerateBlockRamFifo.GenerateDualClockFifo.BlockRamFifo/
NiFpgaFifox/NiFpgaFifoFlagsx*SyncToIClkx/cAddrAGrayx/GenFlops[*].DFlopx/*FDCPEx'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:615]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0/TypeSelector/GenerateBlockRamFifo.GenerateDualClockFifo.BlockRamFifo/
NiFpgaFifox/NiFpgaFifoFlagsx*SyncToOClkx/cAddrBGray_msx/GenFlops[*].DFlopx/
*FDCPEx'. [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:616]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0/TypeSelector/GenerateBlockRamFifo.GenerateDualClockFifo.BlockRamFifo/
NiFpgaFifox/NiFpgaFifoFlagsx*SyncToOClkx/cAddrBGrayx/GenFlops[*].DFlopx/*FDCPEx*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:617]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0/TypeSelector/GenerateBlockRamFifo.GenerateDualClockFifo.BlockRamFifo/
NiFpgaFifox/NiFpgaFifoFlagsx*SyncToOClkx/cAddrAGrayx/GenFlops[*].DFlopx/*FDCPEx'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:618]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0/TypeSelector/GenerateBlockRamFifo.GenerateDualClockFifo.BlockRamFifo/
NiFpgaFifox/NiFpgaFifoFlagsx*SyncToIClkx/cAddrBGray_msx/GenFlops[*].DFlopx/
*FDCPEx'. [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:619]
WARNING: [Vivado 12-180] No cells matched
'*FPGAwFIFOn0/TypeSelector/GenerateBlockRamFifo.GenerateDualClockFifo.BlockRamFifo/
NiFpgaFifox/NiFpgaFifoFlagsx*SyncToIClkx/cAddrBGrayx/GenFlops[*].DFlopx/*FDCPEx*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:620]
WARNING: [Vivado 12-180] No cells matched
'*DmaPortCommIfcIrqInterfacex/DoubleSyncSLx*iDlySigx/*FDCPEx'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:621]
WARNING: [Vivado 12-180] No cells matched
'*DmaPortCommIfcIrqInterfacex/DoubleSyncSLx*DoubleSyncAsyncInBasex/oSig_msx/
*FDCPEx'. [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:622]
WARNING: [Vivado 12-180] No cells matched '*DmaPortCommIfcLvFpgaIrq*bIpIrq_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:623]
WARNING: [Vivado 12-180] No cells matched '*DmaPortCommIfcLvFpgaIrq*bIpIrq*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:624]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/BlkOut.SyncIReset/c1ResetFastLclx*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:625]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/BlkIn.iPushTogglex*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:626]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/BlkIn.i*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:627]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/BlkOut.o*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:628]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/BlkOut.SyncIReset/c2ResetFe_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:629]
WARNING: [Vivado 12-180] No cells matched '*ViControlx*BusClkToReliableClkHS/Blk*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:630]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/Blk*_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:631]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/BlkIn.iPushToggle*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:632]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/BlkOut.oPushToggle0_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:633]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/*oPushToggle0_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:634]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/*oPushToggle1*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:635]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/*iRdyPushToggle_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:636]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/*iRdyPushToggle*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:637]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/BlkOut.SyncIReset*c1*_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:638]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/BlkOut.SyncIReset*c1*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:639]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/BlkOut.SyncOReset*c1*_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:640]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/BlkOut.SyncOReset*c1*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:641]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/BlkOut.SyncIReset*c2*_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:642]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/BlkOut.SyncIReset*c2*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:643]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/BlkOut.SyncOReset*c2*_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:644]
WARNING: [Vivado 12-180] No cells matched
'*ViControlx*BusClkToReliableClkHS/BlkOut.SyncOReset*c2*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:645]
WARNING: [Vivado 12-180] No cells matched '*ViControlx*rEnableIn*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:646]
WARNING: [Vivado 12-180] No cells matched '*ViControlx*tEnableIn_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:647]
WARNING: [Vivado 12-180] No cells matched '*ViControlx*rEnableClear*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:648]
WARNING: [Vivado 12-180] No cells matched '*ViControlx*tEnableClear_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:649]
WARNING: [Vivado 12-180] No cells matched '*ViControlx*bEnableIn_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:650]
WARNING: [Vivado 12-180] No cells matched '*ViControlx*bEnableClear_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:651]
WARNING: [Vivado 12-180] No cells matched '*ViControlx*rDerivedClkLostLock*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:652]
WARNING: [Vivado 12-180] No cells matched '*ViControlx*bDerivedClkLostLock_ms*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:653]
INFO: [Common 17-14] Message 'Vivado 12-180' appears 100 times and further
instances of the messages will be disabled. Use the Tcl command set_msg_config to
change the current settings. [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:653]
WARNING: [Vivado 12-507] No nets matched '*DiagramResetx*aDiagramResetLoc*'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:779]
WARNING: [Vivado 12-508] No pins matched '*RTReset*/cReset_int*/C'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc:888]
Finished Parsing XDC File [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc]
WARNING: [Project 1-498] One or more constraints failed evaluation while reading
constraint file [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc] and the design
contains unresolved black boxes. These constraints will be read post-synthesis (as
long as their source constraint file is marked as used_in_implementation) and
should be applied correctly then. You should review the constraints listed in the
file [.Xil/toplevel_gen_propImpl.xdc] and check the run log file to verify that
these constraints were correctly applied.
INFO: [Project 1-236] Implementation specific constraints were found while reading
constraint file [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc]. These
constraints will be ignored for synthesis but will be used in implementation.
Impacted constraints are listed in the file [.Xil/toplevel_gen_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in
[.Xil/toplevel_gen_propImpl.xdc] to another XDC file and exclude this new file from
synthesis with the used_in_synthesis property (File Properties dialog in GUI) and
re-run elaboration/synthesis.
Parsing XDC File [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/Dram2DP.xdc]
WARNING: [Vivado 12-508] No pins matched '*bNumOfMemBuffers*/C'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/Dram2DP.xdc:8]
WARNING: [Vivado 12-508] No pins matched '-hierarchical'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/Dram2DP.xdc:8]
WARNING: [Vivado 12-508] No pins matched '*bLowLatencyBuffer*/C'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/Dram2DP.xdc:11]
WARNING: [Vivado 12-508] No pins matched '-hierarchical'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/Dram2DP.xdc:11]
WARNING: [Vivado 12-508] No pins matched '*bBaseAddrTable*/C'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/Dram2DP.xdc:14]
WARNING: [Vivado 12-508] No pins matched '-hierarchical'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/Dram2DP.xdc:14]
WARNING: [Vivado 12-508] No pins matched '*bBaggageBits*/C'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/Dram2DP.xdc:17]
WARNING: [Vivado 12-508] No pins matched '-hierarchical'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/Dram2DP.xdc:17]
WARNING: [Vivado 12-508] No pins matched '*Dram2DP*ClearFDCP*/C'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/Dram2DP.xdc:20]
WARNING: [Vivado 12-508] No pins matched '-hierarchical'.
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/Dram2DP.xdc:20]
Finished Parsing XDC File [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/Dram2DP.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading
constraint file [C:/NIFPGA/jobs/Mz4406L_MLpAW6m/Dram2DP.xdc]. These constraints
will be ignored for synthesis but will be used in implementation. Impacted
constraints are listed in the file [.Xil/toplevel_gen_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in
[.Xil/toplevel_gen_propImpl.xdc] to another XDC file and exclude this new file from
synthesis with the used_in_synthesis property (File Properties dialog in GUI) and
re-run elaboration/synthesis.
INFO: [Project 1-236] Implementation specific constraints were found while reading
constraint file
[C:/NIFPGA/programs/Vivado2021_1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl].
These constraints will be ignored for synthesis but will be used in implementation.
Impacted constraints are listed in the file [.Xil/toplevel_gen_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in
[.Xil/toplevel_gen_propImpl.xdc] to another XDC file and exclude this new file from
synthesis with the used_in_synthesis property (File Properties dialog in GUI) and
re-run elaboration/synthesis.
INFO: [Project 1-1714] 1 XPM XDC files have been applied to the design.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 .

Memory (MB): peak = 1442.199 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 12 instances were transformed.
FDCE_1 => FDCE (inverted pins: C): 12 instances

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.134 .

Memory (MB): peak = 1442.199 ; gain = 0.000
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:36 .
Memory (MB): peak = 1442.199 ; gain = 277.117
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed =
00:00:36 . Memory (MB): peak = 1442.199 ; gain = 277.117
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[0]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 933).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[1]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 934).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[2]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 935).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[3]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 936).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[4]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 937).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[5]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 938).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[6]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 939).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[7]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 940).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[8]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 941).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[9]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 942).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[10]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 943).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[11]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 944).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[12]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 945).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[13]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 946).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[14]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 947).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dq[15]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 948).
Applied set_property IO_BUFFER_TYPE = none for ddr3_addr[13]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 949).
Applied set_property IO_BUFFER_TYPE = none for ddr3_addr[12]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 950).
Applied set_property IO_BUFFER_TYPE = none for ddr3_addr[11]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 951).
Applied set_property IO_BUFFER_TYPE = none for ddr3_addr[10]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 952).
Applied set_property IO_BUFFER_TYPE = none for ddr3_addr[9]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 953).
Applied set_property IO_BUFFER_TYPE = none for ddr3_addr[8]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 954).
Applied set_property IO_BUFFER_TYPE = none for ddr3_addr[7]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 955).
Applied set_property IO_BUFFER_TYPE = none for ddr3_addr[6]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 956).
Applied set_property IO_BUFFER_TYPE = none for ddr3_addr[5]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 957).
Applied set_property IO_BUFFER_TYPE = none for ddr3_addr[4]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 958).
Applied set_property IO_BUFFER_TYPE = none for ddr3_addr[3]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 959).
Applied set_property IO_BUFFER_TYPE = none for ddr3_addr[2]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 960).
Applied set_property IO_BUFFER_TYPE = none for ddr3_addr[1]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 961).
Applied set_property IO_BUFFER_TYPE = none for ddr3_addr[0]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 962).
Applied set_property IO_BUFFER_TYPE = none for ddr3_ba[2]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 963).
Applied set_property IO_BUFFER_TYPE = none for ddr3_ba[1]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 964).
Applied set_property IO_BUFFER_TYPE = none for ddr3_ba[0]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 965).
Applied set_property IO_BUFFER_TYPE = none for ddr3_ras_n. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 966).
Applied set_property IO_BUFFER_TYPE = none for ddr3_cas_n. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 967).
Applied set_property IO_BUFFER_TYPE = none for ddr3_we_n. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 968).
Applied set_property IO_BUFFER_TYPE = none for ddr3_reset_n. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 969).
Applied set_property IO_BUFFER_TYPE = none for ddr3_cke[0]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 970).
Applied set_property IO_BUFFER_TYPE = none for ddr3_odt[0]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 971).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dqs_p[0]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 972).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dqs_n[0]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 973).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dqs_p[1]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 974).
Applied set_property IO_BUFFER_TYPE = none for ddr3_dqs_n[1]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 975).
Applied set_property IO_BUFFER_TYPE = none for ddr3_ck_p[0]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 976).
Applied set_property IO_BUFFER_TYPE = none for ddr3_ck_n[0]. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 977).
Applied set_property IO_BUFFER_TYPE = none for cRIO_FPGA_LED_Y. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 980).
Applied set_property IO_BUFFER_TYPE = none for aIrq1. (constraint file
C:/NIFPGA/jobs/Mz4406L_MLpAW6m/toplevel_gen.xdc, line 981).
Applied set_property KEEP_HIERARCHY = SOFT for Dram2DPx/\
DevMem.SingleClockDeviceRamx /\Memories[0].xpm_memory_sdpramx . (constraint file
auto generated constraint).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:21 ;
elapsed = 00:00:36 . Memory (MB): peak = 1442.199 ; gain = 277.117
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'bPktState_reg' in module
'SimpleInterruptMessageTx'
INFO: [Synth 8-802] inferred FSM for state register
'dDmaPortHighSpeedSinkState_reg' in module
'ShimSwitchedLinkDmaPortHighSpeedSinkIfc'
INFO: [Synth 8-802] inferred FSM for state register 'dDmaPortReqDataState_reg' in
module 'ShimHandleDmaPortInputRequestAndData'
INFO: [Synth 8-802] inferred FSM for state register 'dArbitrationState_reg' in
module 'ShimGenSwLinkPacketsAndDmaPortStatus'
INFO: [Synth 8-802] inferred FSM for state register 'dReqSendState_reg' in module
'ShimConvertDmaPortOutputRequestsToPackets'
INFO: [Synth 8-802] inferred FSM for state register 'dDataReceiveState_reg' in
module 'ShimConvertResponsePacketsToDmaPortOutput'
INFO: [Synth 8-802] inferred FSM for state register 'bRegAccessState_reg' in module
'ShimChinchRegisterAccess'
INFO: [Synth 8-802] inferred FSM for state register 'bReadCompleterState_reg' in
module 'ShimChinchRegisterAccess'
INFO: [Synth 8-802] inferred FSM for state register 'oAckState_reg' in module
'ShimLvFpgaRegPortClockCrossing'
INFO: [Synth 8-802] inferred FSM for state register 'SmLogicAndFFs.sMainArbSt_reg'
in module 'ShimChinchCommIfcArbiterBase'
INFO: [Synth 8-802] inferred FSM for state register 'bArbitrationState_reg' in
module 'DmaPortCommIfcInputArbiter'
INFO: [Synth 8-802] inferred FSM for state register 'bArbitrationState_reg' in
module 'DmaPortCommIfcOutputArbiter'
INFO: [Synth 8-802] inferred FSM for state register 'dArbiterIfcRdState_reg' in
module 'Dram2DP'
INFO: [Synth 8-802] inferred FSM for state register 'dArbiterIfcWrState_reg' in
module 'Dram2DP'
INFO: [Synth 8-802] inferred FSM for state register 'cState_reg' in module
'CrioSbSlotControl'
INFO: [Synth 8-802] inferred FSM for state register 'cSenderState_reg' in module
'CrioSbSlotControl'
INFO: [Synth 8-802] inferred FSM for state register 'cState_reg' in module
'CrioSbLineControl'
INFO: [Synth 8-802] inferred FSM for state register 'cState_reg' in module
'CrioSbEngineArbiter'
INFO: [Synth 8-802] inferred FSM for state register 'cTxState_reg' in module
'CrioSbEngineLogic'
INFO: [Synth 8-802] inferred FSM for state register 'fParseState_reg' in module
'CrioSbPacketReceiver'
INFO: [Synth 8-802] inferred FSM for state register 'fState_reg' in module
'CrioSbRxSpiSlave'
INFO: [Synth 8-802] inferred FSM for state register 'cState_reg' in module
'CrioSbDataCaptureControl'
INFO: [Synth 8-802] inferred FSM for state register 'fTrainState_reg' in module
'CrioSidebandClkResCore'
INFO: [Synth 8-802] inferred FSM for state register
'ClockDomainCrossing.bPushEnState_reg' in module 'SafeBusCrossing'
INFO: [Synth 8-802] inferred FSM for state register
'EnableInBlk.rEnableInState_reg' in module 'ViControl'
INFO: [Synth 8-802] inferred FSM for state register
'ClockDomainCrossing.bPushEnState_reg' in module 'SafeBusCrossing__parameterized0'
INFO: [Synth 8-802] inferred FSM for state register
'DiagramResetFSM.rDiagramResetState_reg' in module 'DiagramReset'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 00 |
00
header | 01 |
01
data | 10 |
10
waitdeassert | 11 |
11
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'bPktState_reg' using encoding
'sequential' in module 'SimpleInterruptMessageTx'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 001 |
00
receivepacketheader | 010 |
01
receivepacketdata | 100 |
10
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register
'dDmaPortHighSpeedSinkState_reg' using encoding 'one-hot' in module
'ShimSwitchedLinkDmaPortHighSpeedSinkIfc'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 000 |
000
storerequest | 001 |
001
 storeextheader | 010 |
010
storedata | 011 |
011
waitforadditionalalignwrite | 100 |
100
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'dDmaPortReqDataState_reg'
using encoding 'sequential' in module 'ShimHandleDmaPortInputRequestAndData'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 001 |
00
requestaccesstoifc | 010 |
01
waitforcompletion | 100 |
10
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'dArbitrationState_reg' using
encoding 'one-hot' in module 'ShimGenSwLinkPacketsAndDmaPortStatus'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 00 |
00
requestaccesstoifc | 01 |
01
sendreadrequest | 10 |
10
sendreadrequestextheader | 11 |
11
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'dReqSendState_reg' using
encoding 'sequential' in module 'ShimConvertDmaPortOutputRequestsToPackets'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 00 |
00
rcvoutputdmaheader | 01 |
01
rcvoutputdmadata | 10 |
10
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'dDataReceiveState_reg' using
encoding 'sequential' in module 'ShimConvertResponsePacketsToDmaPortOutput'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 000 |
000
getwritedata | 001 |
001
writereadywait | 010 |
010
strobewrite | 011 |
011
strobereadwait | 100 |
100
stroberead | 101 |
101
getreadresponse | 110 |
110
triggerreadresponse | 111 |
111
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'bRegAccessState_reg' using
encoding 'sequential' in module 'ShimChinchRegisterAccess'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 00 |
00
requestarbiteraccess | 01 |
01
transmitresponseheader | 10 |
10
transmitresponsedata | 11 |
11
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'bReadCompleterState_reg'
using encoding 'sequential' in module 'ShimChinchRegisterAccess'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 001 |
00
datavalidwait | 010 |
01
readywait | 100 |
10
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'oAckState_reg' using encoding
'one-hot' in module 'ShimLvFpgaRegPortClockCrossing'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 000 |
000
instrmsnormacc | 001 |
100
outstrmsnormacc | 010 |
101
msiacc | 011 |
011
statuspushacc | 100 |
010
memspcacc | 101 |
001
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'SmLogicAndFFs.sMainArbSt_reg'
using encoding 'sequential' in module 'ShimChinchCommIfcArbiterBase'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 001 |
00
emergencyaccess | 010 |
01
normalaccess | 100 |
10
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'bArbitrationState_reg' using
encoding 'one-hot' in module 'DmaPortCommIfcInputArbiter'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 001 |
00
emergencyaccess | 010 |
01
normalaccess | 100 |
10
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'bArbitrationState_reg' using
encoding 'one-hot' in module 'DmaPortCommIfcOutputArbiter'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 00 |
00
req | 01 |
01
grant | 10 |
10
done | 11 |
11
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'dArbiterIfcRdState_reg' using
encoding 'sequential' in module 'Dram2DP'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 00 |
00
req | 01 |
01
grant | 10 |
10
done | 11 |
11
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'dArbiterIfcWrState_reg' using
encoding 'sequential' in module 'Dram2DP'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 00001 |
000
requestengine | 00010 |
001
readfpgaintstatus | 00100 |
010
checkicfpgainterruptstatus | 01000 |
011
sendingmessage | 10000 |
100
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'cSenderState_reg' using
encoding 'one-hot' in module 'CrioSbSlotControl'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
 sbcommnotready | 0000000001 |
0000
sendingpresence | 0000000010 |
0001
wrongslotmode | 0000000100 |
0010
requestingslot | 0000001000 |
0110
slotrequested | 0000010000 |
0011
idlewithaccess | 0000100000 |
0100
waitslotrelease | 0001000000 |
1011
relinquishingslot | 0010000000 |
0111
setmodpresenceoverride | 0100000000 |
0101
settingmodpresenceoverride | 1000000000 |
1000
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'cState_reg' using encoding
'one-hot' in module 'CrioSbSlotControl'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
noslotaccess | 00000000001 |
0000
waitforenginegrant | 00000000010 |
0001
changingsleep | 00000000100 |
1000
idle | 00000001000 |
0010
changeenables | 00000010000 |
0100
waitforoechangeack | 00000100000 |
0011
changingenables | 00001000000 |
0101
afterenableschange | 00010000000 |
1100
waitforspidither | 00100000000 |
1110
changingidselout | 01000000000 |
0110
readingidsel | 10000000000 |
0111
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'cState_reg' using encoding
'one-hot' in module 'CrioSbLineControl'
WARNING: [Synth 8-327] inferring latch for variable 'cEnableBidirMode_reg'
[C:/NIFPGA/jobs/Mz4406L_MLpAW6m/CrioSbLineControl.vhd:378]
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 001 |
00
waitforenableout | 010 |
01
waitforrelease | 100 |
10
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'cState_reg' using encoding
'one-hot' in module 'CrioSbEngineArbiter'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 000 |
0000
pbwriteresp | 001 |
0110
armmsgfirstramwrite | 010 |
0001
armmsgsecondramwrite | 011 |
0010
armmsgregwrite | 100 |
0011
regwrite | 101 |
0100
regread | 110 |
0101
waitpacketdone | 111 |
1000
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'cTxState_reg' using encoding
'sequential' in module 'CrioSbEngineLogic'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
sbcommnotready | 000 |
000
waitforpacket | 001 |
001
shiftpackettype | 010 |
010
shiftpbwrite | 011 |
011
shiftregread | 100 |
100
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'fParseState_reg' using
encoding 'sequential' in module 'CrioSbPacketReceiver'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
reset | 001 |
00
active | 010 |
01
done | 100 |
10
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'fState_reg' using encoding
'one-hot' in module 'CrioSbRxSpiSlave'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
plus0 | 000 |
000
plus1 | 001 |
001
plus2 | 010 |
010
minus1 | 011 |
011
minus2 | 100 |
100
minus3 | 101 |
101
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'cState_reg' using encoding
'sequential' in module 'CrioSbDataCaptureControl'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 0000001 |
000
requestslip | 0000010 |
001
waitafterslip | 0000100 |
010
checkpattern | 0001000 |
011
done | 0010000 |
100
failed | 0100000 |
101
waitbeforeretry | 1000000 |
110
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register 'fTrainState_reg' using
encoding 'one-hot' in module 'CrioSidebandClkResCore'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 00 |
00
assert1 | 01 |
01
assert2 | 10 |
10
iSTATE | 11 |
11
*
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register
'ClockDomainCrossing.bPushEnState_reg' using encoding 'sequential' in module
'SafeBusCrossing'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 00 |
000
enableindeasserted | 01 |
001
waituntilcomponentsinit | 10 |
011
enableinasserted | 11 |
100
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register
'EnableInBlk.rEnableInState_reg' using encoding 'sequential' in module 'ViControl'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 00 |
00
assert1 | 01 |
01
assert2 | 10 |
10
iSTATE | 11 |
11
*
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register
'ClockDomainCrossing.bPushEnState_reg' using encoding 'sequential' in module
'SafeBusCrossing__parameterized0'
-----------------------------------------------------------------------------------
----------------
State | New Encoding |
Previous Encoding
-----------------------------------------------------------------------------------
----------------
idle | 000000001 |
0000
waitforexternalcircuittoinit | 000000010 |
0001
waitforbaseclkstobecomevalid | 000000100 |
0010
waitforgatedbaseclkstobecomevalid | 000001000 |
0100
waitfordervclkstobecomevalid | 000010000 |
0101
waitforresetassertionduration | 000100000 |
0110
waitfordiagrstdeasrtpropdly | 001000000 |
0111
waitforhosttoassertdiagrst | 010000000 |
1000
waituntilderivedfromexternalshutdown | 100000000 |
1001
-----------------------------------------------------------------------------------
----------------
INFO: [Synth 8-3354] encoded FSM with state register
'DiagramResetFSM.rDiagramResetState_reg' using encoding 'one-hot' in module
'DiagramReset'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:26 ; elapsed = 00:00:45 .
Memory (MB): peak = 1442.199 ; gain = 277.117
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of
width 8 for RAM gen_blk_box.gen_bb_async.xpm_memory_base_inst
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of
width 8 for RAM gen_blk_box.gen_bb_async.xpm_memory_base_inst
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of
width 8 for RAM gen_blk_box.gen_bb_async.xpm_memory_base_inst
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of
width 8 for RAM gen_blk_box.gen_bb_async.xpm_memory_base_inst
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of
width 8 for RAM gen_blk_box.gen_bb_async.xpm_memory_base_inst
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of
width 8 for RAM gen_blk_box.gen_bb_async.xpm_memory_base_inst
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of
width 8 for RAM gen_blk_box.gen_bb_async.xpm_memory_base_inst
INFO: [Synth 8-7030] Implemented Non-Cascaded Block Ram (cascade_height = 1) of
width 8 for RAM gen_blk_box.gen_bb_async.xpm_memory_base_inst
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:45 ; elapsed
= 00:01:16 . Memory (MB): peak = 1442.199 ; gain = 277.117
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:49 ; elapsed =
00:01:24 . Memory (MB): peak = 1442.199 ; gain = 277.117
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:50 ; elapsed = 00:01:26 .
Memory (MB): peak = 1442.199 ; gain = 277.117
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-7052] The timing for the instance
crio904xBaseLogicx/ShimSwitchedLinkDmaPortIfcx/ShimSwitchedLinkDmaPortInputIfcx/
PacketFifo/DualPortRAMx/InferredRamx/iRAM_reg (implemented as a Block RAM) might be
sub-optimal as no optional output register could be merged into the ram block.
Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:57 ; elapsed = 00:01:43 .
Memory (MB): peak = 1442.199 ; gain = 277.117
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------