8-Bit Microcontroller With 2K Bytes Flash AT89C2051: Features
8-Bit Microcontroller With 2K Bytes Flash AT89C2051: Features
8-Bit Microcontroller With 2K Bytes Flash AT89C2051: Features
Description
The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with 2K Bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high density nonvolatile memory technology and is compatible with the industry standard MCS-51 instruction set. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89C2051 provides the following standard features: 2K Bytes of Flash, 128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the AT89C2051 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
Pin Configuration
PDIP/SOIC
/VPP
0368D-B12/97
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Block Diagram
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AT89C2051
AT89C2051
Pin Description
VCC Supply voltage. GND Ground. Port 1 Port 1 is an 8-bit bidirectional I/O port. Port pins P1.2 to P1.7 provide internal pullups. P1.0 and P1.1 require external pullups. P1.0 and P1.1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port 1 output buffers can sink 20 mA and can drive LED displays directly. When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7 are used as inputs and are externally pulled low, they will source current (IIL) because of the internal pullups. Port 1 also receives code data during Flash programming and verification. Port 3 Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional I/O pins with internal pullups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C2051 as listed below:
Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 Alternate Functions RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (timer 0 external input) T1 (timer 1 external input) Note: C1, C2 = 30 pF 10 pF for Crystals = 40 pF 10 pF for Ceramic Resonators
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Figure 1. Oscillator Connections
Port 3 also receives some control signals for Flash programming and verification. RST Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin high for two machine cycles while the oscillator is running resets the device. Each machine cycle takes 12 oscillator or clock cycles. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
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User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
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AT89C2051
AT89C2051
Restrictions on Certain Instructions
The AT89C2051 and is an economical and cost-effective member of Atmels growing family of microcontrollers. It contains 2K bytes of flash program memory. It is fully compatible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 2K for the AT89C2051. This should be the responsibility of the software programmer. For example, LJMP 7E0H would be a valid instruction for the AT89C2051 (with 2K of memory), whereas LJMP 900H would not. 1. Branching instructions: LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR These unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 00H to 7FFH for the 89C2051). Violating the physical space limits may cause unknown program behavior. CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With these conditional branching instructions the same rule above applies. Again, violating the memory boundaries may cause erratic execution. For applications involving interrupts the normal interrupt service routine address locations of the 80C51 family architecture have been preserved. 2. MOVX-related instructions, Data Memory: The AT89C2051 contains 128 bytes of internal data memory. Thus, in the AT89C2051 the stack depth is limited to 128 bytes, the amount of available RAM. External DATA memory access is not supported in this device, nor is external PROGRAM memory execution. Therefore, no MOVX [...] instructions should be included in the program. A typical 80C51 assembler will still assemble instructions, even if they are written in violation of the restrictions mentioned above. It is the responsibility of the controller user to know the physical features and limitations of the device being used and adjust the instructions used correspondingly.
1. The Lock Bits can only be erased with the Chip Erase operation.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. P1.0 and P1.1 should be set to 0 if no external pullups are used, or set to 1 if external pullups are used. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
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Ready/Busy: The Progress of byte programming can also be monitored by the RDY/BSY output signal. Pin P3.1 is pulled low after P3.2 goes High during programming to indicate BUSY. P3.1 is pulled High again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed code data can be read back via the data lines for verification: 1. Reset the internal address counter to 000H by bringing RST from L to H. 2. Apply the appropriate control signals for Read Code data and read the output data at the port P1 pins. 3. Pulse pin XTAL1 once to advance the internal address counter. 4. Read the next code data byte at the port P1 pins. 5. Repeat steps 3 and 4 until the entire array is read. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire PEROM array (2K bytes) and the two Lock Bits are erased electrically by using the proper combination of control signals and by holding P3.2 low for 10 ms. The code array is written with all 1s in the Chip Erase operation and must be executed before any nonblank memory byte can be re-programmed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 000H, 001H, and 002H, except that P3.5 and P3.7 must be pulled to a logic low. The values returned are as follows. (000H) = 1EH indicates manufactured by Atmel (001H) = 21H indicates 89C2051
Programming Interface
Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.
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AT89C2051
AT89C2051
Flash Programming Modes
Mode Write Code Data(1)(3) RST/VPP 12V P3.2/PROG P3.3 L P3.4 H P3.5 H P3.7 H
H 12V
L H
L H
H H
H H
Bit - 2
12V
Chip Erase
12V
(2)
1. The internal PEROM address counter is reset to 000H on the rising edge of RST and is advanced by a positive pulse at XTAL 1 pin. 2. Chip Erase requires a 10-ms PROG pulse. 3. P3.1 is pulled Low during programming to indicate RDY/BSY.
PP
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AT89C2051
AT89C2051
Absolute Maximum Ratings*
Operating Temperature ................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage............................................. 6.6V DC Output Current...................................................... 25.0 mA *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics
TA = -40C to 85C, VCC = 2.0V to 6.0V (unless otherwise noted)
Symbol VIL VIH VIH1 VOL VOH Parameter Input Low Voltage Input High Voltage Input High Voltage Output Low (Ports 1, 3) Voltage(1) (Except XTAL1, RST) (XTAL1, RST) IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 2.7V IOH = -80 A, VCC = 5V 10% IOH = -30 A IOH = -12 A IIL ITL ILI VOS VCM RRST CIO ICC Logical 0 Input Current (Ports 1, 3) Logical 1 to 0 Transition Current (Ports 1, 3) Input Leakage Current (Port P1.0, P1.1) Comparator Input Offset Voltage Comparator Input Common Mode Voltage Reset Pulldown Resistor Pin Capacitance Power Supply Current Test Freq. = 1 MHz, TA = 25C Active Mode, 12 MHz, VCC = 6V/3V Idle Mode, 12 MHz, VCC = 6V/3V P1.0 & P1.1 = 0V or VCC Power Down Mode(2) VCC = 6V P1.0 & P1.1 = 0V or VCC VCC = 3V P1.0 & P1.1 = 0V or VCC Notes: VIN = 0.45V VIN = 2V, VCC = 5V 10% 0 < VIN < VCC VCC = 5V 0 50 2.4 0.75 VCC 0.9 VCC -50 -750 10 20 VCC 300 10 15/5.5 5/1 100 20 Condition Min -0.5 0.2 VCC + 0.9 0.7 VCC Max 0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 0.5 Units V V V V V V V A A A mV V K pF mA mA A A
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 20 mA Maximum total IOL for all output pins: 80 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power Down is 2V.
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AT89C2051
AT89C2051
Serial Port Timing: Shift Register Mode Test Conditions
(VCC = 5.0V 20%; Load Capacitance = 80 pF)
Symbol Parameter 12 MHz Osc Min tXLXL tQVXH tXHQX tXHDX tXHDV Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid 1.0 700 50 0 700 Max Variable Oscillator Min 12tCLCL 10tCLCL-133 2tCLCL-117 0 10tCLCL-133 Max s ns ns ns ns Units
Float Waveforms(1)
Note:
1.
AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.
Note:
1.
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change frothe loaded VOH/VOL level occurs.
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AT89C2051
TYPICAL ICC - ACTIVE (85C)
20 Vcc=6.0V
I 15 C C 10 m A
5
Vcc=5.0V Vcc=3.0V
0 0 6 12 18 24
FREQUENCY (MHz)
AT89C2051
TYPICAL ICC - IDLE (85C)
3 Vcc=6.0V
I C 2 C m 1 A
Vcc=5.0V
Vcc=3.0V 0 0 3 6 9 12
FREQUENCY (MHz)
AT89C2051
TYPICAL ICC vs. VOLTAGE- POWER DOWN (85C)
20
I 15 C C 10 A
5
0 3.0V
4.0V
5.0V
6.0V
Vcc VOLTAGE
Notes:
1. 2. 3.
XTAL1 tied to GND for ICC (power down) P .1.0 and P1.1 = VCC or GND Lock bits programmed
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AT89C2051
AT89C2051
Ordering Information
Speed (MHz) 12 Power Supply 2.7V to 6.0V Ordering Code AT89C2051-12PC AT89C2051-12SC AT89C2051-12PI AT89C2051-12SI AT89C2051-12PA AT89C2051-12SA 24 4.0V to 6.0V AT89C2051-24PC AT89C2051-24SC AT89C2051-24PI AT89C2051-24SI Package 20P3 20S 20P3 20S 20P3 20S 20P3 20S 20P3 20S Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Automotive (-40C to 105C) Commercial (0C to 70C) Industrial (-40C to 85C)
Package Type 20P3 20S 20 Lead, 0.300 Wide, Plastic Dual In-line Package (PDIP) 20 Lead, 0.300 Wide, Plastic Gull Wing Small Outline (SOIC)
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