Embedded Systems

"It is a combination of hardware and software to perform a specific task"

“An embedded system is a computer system with a dedicated function

within a larger mechanical or electrical system, often with real-time
computing constraints. It is embedded as part of a complete device often
including hardware and mechanical parts. Embedded systems control
many devices in common use today.”

1
 Components of Embedded Systems

Communication
Power Supply Processor Memory Timers & Counters
Ports

Application Specific Software

Input & Output
Circuits Components

••Stable UART
Power
Speed Supply Output
& Smooth ••Load
RS-423
Number – Fluctuation
of I/O
Regulation Pins in output voltage when
•••Proper
CAN
Processor
Read-Only
Unit Price memory(RAM)
Output
Assembler Current to Drive the Load ••load
RS-485
Power Consumption
current changes
••Perfect
SPI
Display
Random
PackagingDevice
Power
Emulator Access Memory(ROM)
Efficiency •Efficiency
UART
Amount of RAM and ROM
••Stable
I2C
Buzzer for Alert
Electrically
Performance Erasable
in Different
Debugger Programmable
Temperature Range Read-Only •Input/Output
I2C
SpecializedRipple
Processing Units
Voltage
•••Proper
Device
Memory
USB Drivers
Peripheral
Noise
Compiler (EEPROM)
Set
Filtering •Transient
Architecture
SPI 8-bit, 16-bit, or 32-bit
Response
••Proper
MEMS
Timer devices
on the Chip
Decoupling
Ethernet Allowable Dissipation
••LineRS-232
Operating
RegulationVoltage
changes

2
Microprocessor Based System
CPU
External RAM, ROM, I/O
(No internal RAM, ROM, I/O ports in the CPU)

SURESH.P.NAIR , HOD - ECE , RCET

8051 Microcontroller 3
 Microcontroller
A smaller computer on a CHIP
On-chip RAM, ROM, I/O Ports, Timer, Serial Controller…
Example: Motorola’s 6811, Intel’s 8051, Atmel 32

SURESH.P.NAIR , HOD - ECE , RCET

8051 Microcontroller 4
8051 - ARCHITECTURE
 Microcontroller

Intel 8051 family

8031 – External ROM
8051 – Built-in ROM
8751 – EPROM 4k Programmable memory
8951 – Flash ROM

Instruction cycle : 1 µ sec with 12 MHz crystal

 8051 family

▪ HMOS technology
▪ Single Power supply –5v
▪ Data memory – 128 bytes
▪ Programmable memory – 4096 bytes
▪ Software Flag – 128 user
▪ Addressable (16 address lines) – 64 K byte
▪ Bi-directional I/O lines – 32
▪ High speed Serial I / O
 8051 family

▪ Timer / Counter – Two

▪ Level prioritized Interrupt – Two
▪ Bit addressable locations
▪ Upward compatible
▪ ASCII code for data
Unique 7 bit binary number
128 characters
MSB is often zero for all characters
Sometime D7 bit used for parity
 1 40
2 39
3 38
4 37
5 36
6 8 35
7 34
8 33
9 0 32
10 31
11 30
12 5 29
13 28
14 27
15 1 26
16 25
17 24
18 23
19 22
20 21
 1 40
2 39 P0.0 (AD0)
3 38 P0.1 (AD1)
4 37 P0.2 (AD2)
5 36 P0.3 (AD3)
6 8 35 P0.4 (AD4)
7 34 P0.5 (AD5)
8 33 P0.6 (AD6)
9 0 32 P0.7 (AD7)
10 31
11 30
12 5 29
13 28
14 27
15 1 26
16 25
17 24
18 23
19 22
20 21
 1 40
2 39 P0.0 (AD0)
3 38 P0.1 (AD1)
4 37 P0.2 (AD2)
5 36 P0.3 (AD3)
6 8 35 P0.4 (AD4)
7 34 P0.5 (AD5)
8 33 P0.6 (AD6)
9 0 32 P0.7 (AD7)
10 31
11 30
12 5 29
13 28 P2.7 (A15)
14 27 P2.6 (A14)
15 1 26 P2.5 (A13)
16 25 P2.4 (A12)
17 24 P2.3 (A11)
18 23 P2.2 (A10)
19 22 P2.1 (A9)
20 21 P2.0 (A8)
 1 40
2 39 P0.0 (AD0)
3 38 P0.1 (AD1)
4 37 P0.2 (AD2)
5 36 P0.3 (AD3)
6 8 35 P0.4 (AD4)
7 34 P0.5 (AD5)
8 33 P0.6 (AD6)
9 0 32 P0.7 (AD7)
(RxD) P3.0 10 31
(TxD) P3.1 11 30
(INT0) P3.2 12 5 29
(INT1) P3.3 13 28 P2.7 (A15)
(T0) P3.4 14 27 P2.6 (A14)
(T1) P3.5 15 1 26 P2.5 (A13)
(WR) P3.6 16 25 P2.4 (A12)
(RD) P3.7 17 24 P2.3 (A11)
18 23 P2.2 (A10)
19 22 P2.1 (A9)
20 21 P2.0 (A8)
 P1.0 1 40
P1.1 2 39 P0.0 (AD0)
P1.2 3 38 P0.1 (AD1)
P1.3 4 37 P0.2 (AD2)
P1.4 5 36 P0.3 (AD3)
P1.5 6 8 35 P0.4 (AD4)
P1.6 7 34 P0.5 (AD5)
P1.7 8 33 P0.6 (AD6)
9 0 32 P0.7 (AD7)
(RxD) P3.0 10 31
(TxD) P3.1 11 30
(INT0) P3.2 12 5 29
(INT1) P3.3 13 28 P2.7 (A15)
(T0) P3.4 14 27 P2.6 (A14)
(T1) P3.5 15 1 26 P2.5 (A13)
(WR) P3.6 16 25 P2.4 (A12)
(RD) P3.7 17 24 P2.3 (A11)
18 23 P2.2 (A10)
19 22 P2.1 (A9)
20 21 P2.0 (A8)
 P1.0 1 40 Vcc
P1.1 2 39 P0.0 (AD0)
P1.2 3 38 P0.1 (AD1)
P1.3 4 37 P0.2 (AD2)
P1.4 5 36 P0.3 (AD3)
P1.5 6 8 35 P0.4 (AD4)
P1.6 7 34 P0.5 (AD5)
P1.7 8 33 P0.6 (AD6)
9 0 32 P0.7 (AD7)
(RxD) P3.0 10 31
(TxD) P3.1 11 30
(INT0) P3.2 12 5 29
(INT1) P3.3 13 28 P2.7 (A15)
(T0) P3.4 14 27 P2.6 (A14)
(T1) P3.5 15 1 26 P2.5 (A13)
(WR) P3.6 16 25 P2.4 (A12)
(RD) P3.7 17 24 P2.3 (A11)
18 23 P2.2 (A10)
19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)
 P1.0 1 40 Vcc
P1.1 2 39 P0.0 (AD0)
P1.2 3 38 P0.1 (AD1)
P1.3 4 37 P0.2 (AD2)
P1.4 5 36 P0.3 (AD3)
P1.5 6 8 35 P0.4 (AD4)
P1.6 7 34 P0.5 (AD5)
P1.7 8 33 P0.6 (AD6)
9 0 32 P0.7 (AD7)
(RxD) P3.0 10 31
(TxD) P3.1 11 30
(INT0) P3.2 12 5 29
(INT1) P3.3 13 28 P2.7 (A15)
(T0) P3.4 14 27 P2.6 (A14)
(T1) P3.5 15 1 26 P2.5 (A13)
(WR) P3.6 16 25 P2.4 (A12)
(RD) P3.7 17 24 P2.3 (A11)
XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)
 P1.0 1 40 Vcc
P1.1 2 39 P0.0 (AD0)
P1.2 3 38 P0.1 (AD1)
P1.3 4 37 P0.2 (AD2)
P1.4 5 36 P0.3 (AD3)
P1.5 6 8 35 P0.4 (AD4)
P1.6 7 34 P0.5 (AD5)
P1.7 8 33 P0.6 (AD6)
RST 9 0 32 P0.7 (AD7)
(RxD) P3.0 10 31
(TxD) P3.1 11 30
(INT0) P3.2 12 5 29
(INT1) P3.3 13 28 P2.7 (A15)
(T0) P3.4 14 27 P2.6 (A14)
(T1) P3.5 15 1 26 P2.5 (A13)
(WR) P3.6 16 25 P2.4 (A12)
(RD) P3.7 17 24 P2.3 (A11)
XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)
 P1.0 1 40 Vcc
P1.1 2 39 P0.0 (AD0)
P1.2 3 38 P0.1 (AD1)
P1.3 4 37 P0.2 (AD2)
P1.4 5 36 P0.3 (AD3)
P1.5 6 8 35 P0.4 (AD4)
P1.6 7 34 P0.5 (AD5)
P1.7 8 33 P0.6 (AD6)
RST 9 0 32 P0.7 (AD7)
(RxD) P3.0 10 31
(TxD) P3.1 11 30 ALE
(INT0) P3.2 12 5 29
(INT1) P3.3 13 28 P2.7 (A15)
(T0) P3.4 14 27 P2.6 (A14)
(T1) P3.5 15 1 26 P2.5 (A13)
(WR) P3.6 16 25 P2.4 (A12)
(RD) P3.7 17 24 P2.3 (A11)
XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)
 P1.0 1 40 Vcc
P1.1 2 39 P0.0 (AD0)
P1.2 3 38 P0.1 (AD1)
P1.3 4 37 P0.2 (AD2)
P1.4 5 36 P0.3 (AD3)
P1.5 6 8 35 P0.4 (AD4)
P1.6 7 34 P0.5 (AD5)
P1.7 8 33 P0.6 (AD6)
RST 9 0 32 P0.7 (AD7)
(RxD) P3.0 10 31 EA
(TxD) P3.1 11 30 ALE
(INT0) P3.2 12 5 29
(INT1) P3.3 13 28 P2.7 (A15)
(T0) P3.4 14 27 P2.6 (A14)
(T1) P3.5 15 1 26 P2.5 (A13)
(WR) P3.6 16 25 P2.4 (A12)
(RD) P3.7 17 24 P2.3 (A11)
XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)
 P1.0 1 40 Vcc
P1.1 2 39 P0.0 (AD0)
P1.2 3 38 P0.1 (AD1)
P1.3 4 37 P0.2 (AD2)
P1.4 5 36 P0.3 (AD3)
P1.5 6 8 35 P0.4 (AD4)
P1.6 7 34 P0.5 (AD5)
P1.7 8 33 P0.6 (AD6)
RST 9 0 32 P0.7 (AD7)
(RxD) P3.0 10 31 EA
(TxD) P3.1 11 30 ALE
(INT0) P3.2 12 5 29 PSEN
(INT1) P3.3 13 28 P2.7 (A15)
(T0) P3.4 14 27 P2.6 (A14)
(T1) P3.5 15 1 26 P2.5 (A13)
(WR) P3.6 16 25 P2.4 (A12)
(RD) P3.7 17 24 P2.3 (A11)
XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)
 8051 Pin details

Port 0
18
Crystal 39 - 32 AD0 – AD7
19
Port 2
21 - 28 A8 – A15
RST 9

31 Port 1
EA 1-8
User
PSEN 29
Port 3
ALE 30 10 - 17
Control
Ground 20
 MEMORY MAP
Program Memory Internal RAM Data Memory
FFFF FF FFFF

SFR

External 80
7F
Data
RAM External
1000 00
0FFF
INT. EXT.
EA = 1 EA = 0

0000 0000
 Internal Memory Map
Internal RAM

FF
Special
Function
Register
80
7F
Data
RAM
00
 Internal Memory Map
Internal RAM

FF 7F
Special
Function
Register
80
7F
Data
RAM 20
1F
00 Bank 3
18
17
Bank 2
10
0F
Bank 1
08
07
00
Bank 0
 Internal Memory Map
Internal RAM

FF 7F
Special 07 R7
Function
Register 06 R6
80
05 R5
7F
Data
04 R4
RAM 20
1F
00 Bank 3 03 R3
18
17 02 R2
Bank 2
10
0F
Bank 1 01 R1
08 Internal
07
00 R0 Pointers
00
Bank 0
 Block Diagram

External interrupts

On-chip Timer / Counter

Interrupt ROM for On-chip Timer 1 Counter

Control program RAM
Timer 0 Inputs
code

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P2 P1 P3 TxD RxD
Address / Data
D7 D6 D5 D4 D3 D2 D1 D0
 PSW Register

D7 D6 D5 D4 D3 D2 D1 D0

Carry Parity
Au. Carry
User Flag1
User Flag 0 0 0 Bank 0 Over Flow
0 1 Bank 1
1 0 Bank 2
1 1 Bank 3
 Stack Pointer
▪ SP is an 8 bit register
▪ May reside anywhere in on-chip RAM
▪ Normally initialized with 07H
▪ Actual location starts from 08H
▪ SP is incremented for Push, Call
▪ SP is decremented for Pop
 Data Pointer

▪ Data Pointer - DPTR

▪ One 16 bit register
▪ To hold 16 bit address
▪ Used to access external data memory
▪ May be used as two 8 bit registers
▪ DPH, DPL
 I /O Port

▪ Port 0 – can sink 8 TTL inputs

▪ Port 0 – open drain output
▪ Port 3 – can drive 4 TTL inputs
▪ Port 1, 2, 3 – have internal pull-ups
▪ On Reset, ports are written with 1
 Clock

▪ Crystal is connected between pins

18 & 19
▪ Crystal generator provides internal
clocking signal
▪ Internal clocking is half the OSC
frequency
▪ Each machine cycle contain 6 states
▪ User cannot access internal clocks
Address Latch Enable
Address Latch Enable (ALE)
▪ Activated twice during each machine cycle
▪ It is used to latch the valid address externally
PSEN signal
Used for external fetches from Program Memory
⚫ It takes 6 oscillator periods
⚫ EA pin must be connected to ground
⚫ PC contains value larger than 0FFF
 Boolean Processor

▪ It is an integrated bit processor

▪ It has own
Instruction set
Accumulator
Carry flag
Bit addressable RAM
I/O
CONTROL Register

These registers contain control / status

information
▪ TMOD – Timer mode register
▪ TCON – Timer control register
▪ SCON – Serial control register
▪ IE – Interrupt enable register
▪ IP – Interrupt priority register
▪ PCON – Power control register
 TIMER REGISTER

▪ Two timers in 8051 family

▪ Three timers in 8052 family
▪ Sixteen bit Timer / Counter – T0, T1
▪ Eight bit register – TH0, TL0, TH1, TL1
▪ Used auto-reload
TH0 TL0
TH1 TL1
 Timer

Timer 0, Timer 1
▪ Mode 0
8 bit counter
Divide by 32 pre-scalar
13 bit register
▪ Mode 1 – sixteen bits timer
▪ Mode 2 – 8 bit counter with auto-reload
▪ Mode 3 – Timer 1
To hold the count value
Two separate counter
 Tmod Register
Timer - 1 Timer - 0

D7 D6 D5 D4 D3 D2 D1 D0

Gate M1 M0
0 0 8 bit counter
0 1 16 bit
C/T
1 for Counter 1 0 8 bit, auto reload

0 for Timer 1 1 Timer 0

 Tcon Register
Timer 1 Timer 0

D7 D6 D5 D4 D3 D2 D1 D0

TF1 TR 1 TF 0 TR 0 IE1 IT 1 IE 0 IT 0
1 - ON by SW
0 - Off

Overflow - Set by HW Set by HW when

Cleared – vectors to Int. routine External Int. detected

Level triggered
Edge triggered
Serial Data Buffer

▪ Referred as SBUF – 99h

▪ Contains two registers
Transmit Buffer
Receive Buffer
 Serial Port

4 modes
▪ Mode 0 – Data enters and exists through RxD
TxD outputs shift clock
8 bits, Baud rate 1/12 Frequency
▪ Mode 1 – 10 bits (data+ start, stop bit)
Data exists through TxD
Data received through RxD
Variable baud rate
▪ Mode 2 – 11 bits (data+ start, stop bit, parity bit)
Data exists through TxD
Data received through RxD
Baud rate is programmable
▪ Mode 3 – Similar to mode 2, Baud variable
 Scon Register

D7 D6 D5 D4 D3 D2 D1 D0

SM0 SM 1 SM2 REN TB8 RB8 TI RI

Multi-processor
Comm. features Mode 2 / 3
9 bit

0 0 - mode 0 - fosc / 12
0 1 - mode 1 - 8 bit UART – variable baud
Receive Int. flag
1 0 - mode 2 - 9 bit UART – fosc / 32 or fosc / 64 set – HW
1 1 - mode 3 - 9 bit UART - variable Cleared - SW
 Interrupt Enable Register
D7 D6 D5 D4 D3 D2 D1 D0

EA X ET2 ES ET1 EX1 ET0 EX0

Serial Port Int. Ext. Int. 1

0 – disables all
0 – disables 0 – disables
the interrupts
1 – enables 1 – enables
1 – enables

Timer 1 overflow Int.

0 – disables
1 – enables
Timer 0 overflow Int. Ext. Int. 0
0 – disables 0 – disables
1 – enables 1 – enables
 Interrupt Priority Register
D7 D6 D5 D4 D3 D2 D1 D0

x X X PS PT1 PX1 PT0 PX0

Int-1 Int-0

Serial Port Int. Timer 1 Timer 0

1 – Higher priority

IE0 – highest - 0003

TF0 – - 000B
IE1 – - 0013
TF1 - - 001B
RI + TI - - 0023
TF2 + ExF2 - lowest - 002B
 Power Down Mode

▪ By instruction
▪ Oscillator is stopped
▪ Content of RAM & SFR is held
▪ Exit only by Reset

▪ Vcc can be reduced

▪ Vcc must be restored before Reset
 Power Control Register
D7 D6 D5 D4 D3 D2 D1 D0
Smod1 Smod0 POF GF1 GF0 PD IDL

1 – baud rate is Set when the

power is ON
made two
times faster
General Purpose bits

This bit determines

the purpose of Set for Power down
seventh bit in Scon mode
register
Set for idle mode
 Addressing Modes

▪ 5 modes
▪ Register – R0-R7, Acc, B, DPTR, Cy
▪ Direct – RAM, Special Function Reg.
▪ Register Indirect - @R0, @R1, SP
▪ Immediate
▪ Base register + Index register
@DPTR + Acc
@PC + Acc
 Instruction Set

5 groups

▪ Data Transfer group

▪ Arithmetic operation group
▪ Logical operation group
▪ Boolean variable manipulation
▪ Program & Machine control