Microprocessor Systems

Lecture 18
System Peripherals

Engr. Rehan Azmat

Lecture 18
Recap
 SysTick, Nested Vector Interrupt Controller, System Control
Block, Memory Protection Unit, Floating Point Unit

Topics
 DMA
 EEPROM
 GPIO
 Watchdog Timer
 Hibernation Module
 General Purpose Timer

Engr. Rehan Azmat

 Input/Output: TM4C123
Cortex M4 Systick
System Bus Interface NVIC

GPIO Port A GPIO Port B

PA7 PB7
PA6 Four PB6
PA5/SSI0Tx Eight PB5
UARTs I2Cs
PA4/SSI0Rx PB4
PA3/SSI0Fss PB3/I2C0SDA
PA2/SSI0Clk Four PB2/I2C0SCL
PA1/U0Tx CAN 2.0 PB1
SSIs
PA0/U0Rx PB0
PC7 GPIO Port C GPIO Port D PD7
PC6
PC5 USB 2.0 Twelve
PD6
PD5
6 General-Purpose
PC4
PC3/TDO/SWO
Timers PD4
PD3 I/O (GPIO) ports:
PC2/TDI PD2
• Four 8-bit ports
JTAG Six
PC1/TMS/SWDIO 64-bit wide PD1
PC0/TCK/SWCLK PD0

GPIO Port E GPIO Port F

(A, B, C, D)
PE5
PE4 ADC Two Analog PF4 • One 6-bit port (E)
PE3 2 channels Comparators PF3
PE2
PE1
12 inputs
12 bits Two PWM
PF2
PF1
• One 5-bit port (F)
PE0 Modules PF0

Advanced High Performance Bus Advanced Peripheral Bus

Bard, Gerstlauer, Valvano,

Yerraballi
System Peripherals
 DMA
◦ Support for memory-to-memory, memory-to-
peripheral, and peripheral-to-memory in multiple
transfer modes with data sizes of 8, 16, and 32
bits.
 EEPROM (2K)
◦ 2Kbytes of memory accessible as 512 32-bit
words
◦ Access protection per block
◦ Interrupt support for write completion to avoid
polling

Engr. Rehan Azmat

Continue...
 GPIO (43)
◦ The GPIO module is composed of six physical GPIO
blocks, each corresponding to an individual GPIO port
(Port A, Port B, Port C, Port D, Port E, Port F).
◦ The GPIO module supports up to 43 programmable
input/output pins, depending on the peripherals being used.

 Watchdog Timer (2)

◦ The watchdog timer is used to regain control when a
system has failed due to a software error or due to the
failure of an external device to respond in the expected
way.

Engr. Rehan Azmat

Continue...
 Hibernation Module
◦ The Hibernation Module manages removal and
restoration of power to provide a means for
reducing system power consumption.

 General Purpose Timer (12)

◦ Programmable timers can be used to count or
time external events that drive the Timer input
pins.

Engr. Rehan Azmat

General Purpose Input/Output
 General-purpose input/output (GPIO) pins offer
flexibility for a variety of connections.
 The TM4C123GH6PM GPIO module is comprised
of six physical GPIO blocks, each corresponding to
an individual GPIO port.
 The GPIO module is FiRM-compliant (compliant to
the ARM Foundation IP for Real-Time
Microcontrollers specification) and supports 0-43
programmable input/output pins.
 Highly flexible pin muxing allows use as GPIO or
one of several peripheral functions
 5-V-tolerant in input configuration
Engr. Rehan Azmat
Continue...
 Ports A-G accessed through the Advanced
Peripheral Bus (APB)
 Fast toggle capable of a change every clock cycle
for ports on AHB, every two clock cycles for ports
on APB
 Programmable control for GPIO interrupts
◦ Interrupt generation masking
◦ Edge-triggered on rising, falling, or both
◦ Level-sensitive on High or Low values

 Bit masking in both read and write operations

through address lines
 Can be used to initiate an ADC sample sequence
or a μDMA transfer
Engr. Rehan Azmat
Continue...
 Pin state can be retained during
Hibernation mode
 Pins configured as digital inputs are
Schmitt-triggered
 Programmable control for GPIO pad
configuration
◦ Weak pull-up or pull-down resistors
◦ 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink
18-mA

◦ Slew rate control for 8-mA pad drive

Engr. Rehan Azmat

Default States GPIO

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Alternate Functions of GPIO

Engr. Rehan Azmat

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Engr. Rehan Azmat
Engr. Rehan Azmat
Configuring GPIO
To configure the GPIO pins of a particular port, follow these
steps:
1. Enable the clock to the port by setting the appropriate bits in
the RCGCGPIO register.
2. Set the direction of the GPIO port pins by programming the
GPIODIR register.
3. Configure the GPIOAFSEL register to program each bit as a
GPIO or alternate pin.
4. Set the drive strength for each of the pins through the
GPIODR2R, GPIODR4R, and GPIODR8R registers.
5. Program each pad in the port to have either pull-up, pull-
down, or open drain functionality through the GPIOPUR,
GPIOPDR, GPIOODR register.

Engr. Rehan Azmat

Continue...
6. To enable GPIO pins as digital I/Os, set the appropriate DEN
bit in the GPIODEN register. To enable GPIO pins to their
analog function (if available), set the GPIOAMSEL bit in the
GPIOAMSEL register.

7. Program the GPIOIS, GPIOIBE, GPIOBE, GPIOEV, and

GPIOIM registers to configure the type, event, and mask of
the interrupts for each port.

8. Optionally, software can lock the configurations of the NMI

and JTAG/SWD pins on the GPIO port pins, by setting the
LOCK bits in the GPIOLOCK register.

Engr. Rehan Azmat