Computer-Aided Design

For
Digital Systems
In the beginning…
“Integrated Circuits” with transistors and interconnecting
wires on the same semiconductor substrate date from
the early 1960’s. Early IC’s used bipolar transistors and
“transistor-transistor logic” (TTL).

First TTL commercial 7400 part - 1965

In the beginning…
TTL logic was dominant through the
1970’s, until field-effect transistors and
CMOS logic offered higher densities and
lower cost.

Designs progressed from Small-Scale

Integration (SSI) through Medium and
Large-Scale Integration (MSI and LSI),
to Very Large Scale Integration (more
than 10K transistors on a single “chip”)
as CMOS became dominant in the
1980’s.
First CMOS 7400 part - 1980
In the beginning…
Digital/electronic systems were built using LSI or VLSI chips.

Breadboard Wire wrap Printed Circuit Assembly

By 1980…

CMOS-based VLSI systems (> 10K transistors) were

mainstream (processors, memories, bus controllers, etc.)

Programmable devices on the rise (PALs, CPLDs, FPGAs)

Computers were becoming more powerful and less expensive

CAD tools became essential for digital design

Digital circuit CAD tools initially helped engineers design
the structure of a circuit, by…
 Digital circuit CAD tools initially helped engineers design
the structure of a circuit, by…
A
B
C
X

…drawing a schematic picture, or

 Digital circuit CAD tools initially helped engineers design
the structure of a circuit, by…
G1 N1
A not g1 (N1,A);
B G3 N3
C not g2 (N2,C);
or g3 (N3,N1,B,C);
G4 G6 X
N4 or g4 (N4,B,C);
G5 N5
or g5 (N5,N1,N2,B);
N2 and g6 (X,N3,N4,N5);
G2

…drawing a schematic picture, or …creating a netlist

 Digital circuit CAD tools initially helped engineers design
the structure of a circuit, by…
A not g1 (N1,A);
B not g2 (N2,C);
C
or g3 (N3,N1,B,C);
X
or g4 (N4,B,C);
or g5 (N5,N1,N2,B);
and g6 (X,N3,N4,N5);

…drawing a schematic picture, or …creating a netlist

…and converting between these forms

Schematic symbols generally had a 1:1 relationship with
low-level implementations (transistor patterns)

VDD

A
B
A Out
Out
B

GND
Schematic symbols generally had a 1:1 relationship with
low-level implementations (transistor patterns)
A
B
Schematic entry included hierarchy, where lower- C

level circuits are bundled as components in B Y

higher-level designs (like software subroutines) I0

I2
I3
I4
I5
Schematic symbols generally had a 1:1 relationship with
low-level implementations (transistor patterns)
A
B I$01
N$01
Schematic entry included hierarchy, where lower- C

level circuits are bundled as components in B I$02 Y

higher-level designs (like software subroutines) I0

I1 N$02
I2 I$03
I3
Netlists are text-based renditions of circuit I4

structure; all instances and nets are given C1: I$01(N$01, A, B, C)

C2: I$02(Y, N$01, B, N$02)
unique names, and a list is built.
C3: I$03(N$02, I0, I1, I2, I3, I4)

Generally, netlists were generated from schematics, and

were the common form used for manufacturing
Transistors became smaller and cheaper, and digital
systems became more complex.
Transistors became smaller and cheaper, and digital
systems became more complex.

As larger design teams formed,

communication and coordination
became a bottleneck
Schematics became inefficient – too many signals, too
many pictures, too many tool issues.

How to keep large teams using

the same definitions, names,
components, etc?
Then with ULSI, integrated circuits with hundreds of
subcircuits and millions of transistors became mainstream

Precise specifications & clear

communications were absolutely
necessary to coordinate large
systems.
The Advent of HDLs
In the 1980’s, the federal government sponsored work on a
“hardware design language” (HDL) to describe specifications.

It would offer “1-0” or “event driven” simulation to verify logic

Based on ADA, it would be promoted as the standard design

environment. Circuit synthesis was not a part of the plan.

VHDL was born, and was in widespread use by the time IEEE
released a spec in 1987.
Gateway Design Automation noticed, and released Verilog as a
commercial product in 1990.
Background
Verilog is based on C, and is simpler than VHDL. It rapidly became
the market leader, even though it was expensive.

Like VHDL, Verilog was conceived as a specification language.

By mid 1990’s, synthesis had proven it’s worth, and became the
major force behind HDL adoption.

By early 2000’s, HDL’s supplanted all other design tools.

It is relatively easy to learn VHDL after first learning Verilog, and

vice-versa.
Background
A
Verilog and VHDL are a “hardware B
C
design languages” (HDL) used to X
describe digital circuits and systems.

An HDL description may be thought of as an

“executable functional specification”
Background
A
Here’s a basic example… B
C
X
module Verilog_example (
input A, B, C,
output X
);

assign X = (!A | B | C) & (B | C) & (!A | B | !C);

endmodule
History
void bubbleSort(int a[], int n)
{
HDL’s are not sequential int i, j;
for (i = 0; i < n-1; i++)
programming languages like C or for (j = 0; j < n-i-1; j++)
if (a[j] > a[j+1])
Java that describe algorithms using {
int temp = a[j];
step-by-step processes. a[j] = a[j+1];
a[j+1] = temp;
}
}
History
void bubbleSort(int a[], int n)
{
HDL’s are not sequential int i, j;
for (i = 0; i < n-1; i++)
programming languages like C or for (j = 0; j < n-i-1; j++)
if (a[j] > a[j+1])
Java that describe algorithms using {
int temp = a[j];
step-by-step processes. a[j] = a[j+1];
a[j+1] = temp;
}
}

A
HDL’s describe circuits. They can be B
C
simulated or synthesized, but they do X
not result in an executable (object) file
Behavioral vs. Structural Models

HDL’s can describe circuit structure, from high-level block diagrams to

root-level descriptions. Structural HDL lets engineers assemble
predesigned/preexisting modules into more complex circuits.

HDL’s can also describe high-level circuit behavior, instead of circuit

structure. Behavioral HDL lets engineers think and work at higher
abstraction levels, and that makes code easier to read and write.

More involved designs are hierarchical, with top-level designs built from
lower-level blocks. Low-level “leaf” blocks are typically use behavioral
HDL, and these are assembled into systems using structural HDL.
Behavioral vs. Structural Models
A
module example (input A, B, C, output X); B
C
assign X = (!A | B | C) & (B | C) & (!A | B | !C); X
endmodule
Behavioral

module example (input A, B, C, output X);

wire n1, n2, n3, n4, n5; N1
A
not (n1, A); B N3

not (n2, C); C

nor (n3, n1, B, C); X
N4
nor (n4, B, C);
nor (n5, n1, B, n2); N5
nor (X, n3, n4, n5); N2

endmodule Structural
Behavioral vs. Structural Models
Behavioral HDL defines outputs as functions of inputs, without describing any circuit
components that might be used in constructing the circuit.
Structural HDL is a form of netlist, defining a circuit as a collection of subordinate
components and their interconnecting wires.

A B C Y I$001: INV(B,N$001)
Drive an output B
0 0 0 0 signal Y to a 1 C I$002: AND2(N$001,C,N$002)
0 0 1 1 Y I$003: INV(C,N$003)
0 1 0 0 whenever input B is
not asserted at the A I$004: AND2(A,N$003,N$004)
0 1 1 0
1 0 0 1 same time C is, or I$005: OR2(N$002,N$004,Y)
1 0 1 1 when A is asserted
1 1 0 1 when C is not.
1 1 1 0

Behavioral descriptions define input-to- Structural descriptions show how lower-level

output relationships, but provide no components (like logic gates) are interconnected,
information about how to construct a circuit but the input/output behavior must be deduced.
Behavioral vs. Structural Models
A behavioral description of a 4-bit comparator is easy to create, its function is clear to the
reader, and it is portable between CAD tools.

Structural Circuit Behavioral Description

assign AgtB = (A > B) ? 1’b1 : 1’b0;
assign AeqB = (A < B) ? 1’b1 : 1’b0’;
assign AltB = (!AgtB & !AeqB);

Don’t worry about the Verilog syntax

for now – we’ll look at that shortly!
Behavioral vs. Structural Verilog Models
module adder_4bit(input Cin, [3:0] X, Y, output Cout, [3:0] Sum);
Verilog Behavioral Adder
assign {Cout, sum} = x + y + Cin;
Simple and easy to read
endmodule

module full_adder(input A, B, Cin, output S, Cout);

wire s1,c1,c2,c3;
xor(s1,A,B);
xor(S,Cin,s1);
and(c1,A,B);
and(c2,A,Cin);
and(c3,B,Cin);
or(Cout,c1,c2,c3);
endmodule

module adder_4bit(input Cin, [3:0] X, Y, output Cout, [3:0] Sum);

wire c1,c2,c3;
full_adder fa1(.x(x[0]),.y(y[0]),.cin(cin),.s(sum[0]),.cout(c1));
full_adder fa2(.x(x[1]),.y(y[1]),.cin(c1),.s(sum[1]),.cout(c2)); Verilog Structural Adder
full_adder fa3(.x(x[2]),.Y(y[2]),.cin(c2),.s(sum[2]),.cout(c3)); More work, more detail.
full_adder fa4(.x(x[3]),.y(y[3]),.cin(c3),.s(sum[3]),.cout(cout));
endmodule
A good thing?
Simulator
HDL simulations execute in a concurrent environment.
HDL statements are event driven: they are only simulated
(executed) after an input variable changes state.

A
B G3 N3
C A
G4 G6 X B
N4
C
G5 N5
Time
T1 T2 T3 T4 T5 T6 T7 T8
Simulator
Sequential processing algorithm defines a set of steps that are taken in
a specific order; Concurrent processing steps occur whenever new
input data is available, with no implied sequence relationship between
separate concurrent processes.
Consider a simulation of a 2-input mux: At what time(s) should gate A1
be simulated? What about gate O1?

A
A N2
A1
B B
N1 O1 Y
C
A2
C N3
Y
T0 T1 T2 T3 T4 T5 T6
Simulator – Modelling time
Simulators model time as arbitrarily small “time steps”, typically around
10ps.

Only circuit components whose inputs have changed are simulated in

any given step. Each step can take as much CPU time as is needed - in
some time steps, many circuit nodes may change, requiring lots of CPU
time. In other steps, few nodes may change, requiring little CPU time.

“Simulator time” is held constant during the simulator time step, until all
circuit nodes/instances have been simulated and there are no more
changes. Only then does simulator time advance.
Simulator – Modelling time
A B
N$60 I$19: NAND3(N$43,N$41,N$44,N$53)
Block 1 N$42 I$22
N$43 I$20: OR3(N$45,N$43,N$46,N$54)
N$53
I$19 N$61 I$21: NAND2(N$53,N$54,N$58)
N$44
N$58 I$23 I$25 I$22: OR2(B,N$42,N$60)
B I$21 N$64 I$23: OR2(N$42,N$58,N$61)
Block 3 N$45
Clk N$46 I$20 N$62 I$24: FF(Clk,B,N$62)
N$54 I$25: AND3(N$60,N$61,N$62,N$54)
I$24
Clk
Block 2

User Source File Block 3 Detail Block 3 Netlist

Current time Simulator Time Steps

Consider block 3, expanded into a schematic

...
and netlist. Instances and nets not named in ... ...
B 0 0 0 - - -
the source file get auto-generated names. N$42 ... 1 1 0 - - - ...
N$43 ... 1 1 1 - - - ...
Only some nets will change in any given time Clk ... 0 0 1 - - - ...
step. Here, only N$42 and Clk change. Only N$54 ... 1 1 1 - - - ...
instances whose inputs have changed in a N$58 ... 0 0 0 - - - ...
N$61 ... 0 0 0 - - - ...
given step are simulated.

...
Time
Simulator
Consider the circuit and
netlist…
g1
A
B g3
C
g4 g6 X

g5
g2

not g1 (N1,A);
not g2 (N2,C);
or g3 (N3,N1,B,C);
or g4 (N4,B,C);
or g5 (N5,N1,N2,B);
and g6 (X,N3,N4,N5);
Simulator
Consider the circuit and …gate order is immaterial, and
netlist… so is netlist statement order

g1
A B g4
B g3
C
C g1
A g3 g6 X
g4 g6 X

g5
g5
g2
g2

not g1 (N1,A); and g6 (X,N3,N4,N5);

not g2 (N2,C); not g1 (N1,A);
or g3 (N3,N1,B,C); or g4 (N4,B,C);
or g4 (N4,B,C); or g3 (N3,N1,B,C);
or g5 (N5,N1,N2,B); not g2 (N2,C);
and g6 (X,N3,N4,N5); or g5 (N5,N1,N2,B);
Simulator
This is unlike C, where statement order definitely matters

void bubbleSort(int a[], int n) void bubbleSort(int a[], int n)

{ {
int i, j; int i, j;
for (i = 0; i < n-1; i++) for (i = 0; i < n-1; i++)
for (j = 0; j < n-i-1; j++) for (j = 0; j < n-i-1; j++)
if (a[j] > a[j+1]) if (a[j] > a[j+1])
{ {
int temp = a[j]; a[j] = a[j+1];
a[j] = a[j+1]; int temp = a[j];
a[j+1] = temp; a[j+1] = temp;
} }
} }

You get an A! You don’t

Simulator
g1
A
B g3
C
g4 g6 X

g5
g2
not (N1,A);
Consider our example circuit not (N2,C);
or (N3,N1,B,C);
and netlist… or (N4,B,C);
or (N5,N1,N2,B);
and (X,N3,N4,N5);
Simulator
module netlist(
g1
A input A, B, C,
B g3
C output X
);
g4 g6 X

g5
wire N1,N2,N3,N4,N5;
g2
not (N1,A);
Add a few lines, and you get a not (N2,C);
or (N3,N1,B,C);
valid Verilog source file. The or (N4,B,C);
example shows structural or (N5,N1,N2,B);
and (X,N3,N4,N5);
Verilog – structural VHDL
would look similar. endmodule
Simulator
module netlist(
g1
A input A, B, C,
B g3
C output X
);
g4 g6 X

g5
wire N1,N2,N3,N4,N5;
g2
not (N1,A);
not (N2,C);
The order of lines in the or (N3,N1,B,C);
Verilog file does not matter. or (N4,B,C);
or (N5,N1,N2,B);
and (X,N3,N4,N5);

endmodule
Simulator
module netlist(
g1
A input A, B, C,
B g3
C output X
);
g4 g6 X

g5
wire N1,N2,N3,N4,N5;
g2
and (X,N3,N4,N5);
not (N1,A);
The order of lines in the or (N4,B,C);
Verilog file does not matter. or (N3,N1,B,C);
not (N2,C);
or (N5,N1,N2,B);

endmodule
Simulator
N1
module netlist(
A N3
input A, B, C,
B
C output X
);
X
N4

N5
wire N1,N2,N3,N4,N5;
N2
assign N1 = !A;
We can replace the structural assign N2 = !C;
assign N3 = N1 | B | C;
description with a behavioral assign N4 = B | C;
description… assign N5 = N1 | B | N2;
assign X = N3 & N4 & N5;

endmodule
Simulator
N1
module netlist(
A N3
input A, B, C,
B
C output X
);
X
N4

N5
wire N1,N2,N3,N4,N5;
N2
assign N5 = N1 | B | N2;
We can replace the structural assign N1 = !A;
assign X = N3 & N4 & N5;
description with a behavioral assign N2 = !C;
description… assign N3 = N1 | B | C;
assign N4 = B | C;

And still the order of lines endmodule

does not matter
Simulator
N1 module netlist(
A
B N3 input A, B, C,
C output X
X );
N4

N5 wire N1,N2,N3,N4,N5;
N2

assign X=(!A|B|C) & (B|C)&(!A|B|!C);

Or we can use a more compound
behavioral description… endmodule

… this is the most typical form

Again, if there were multiple assign statements, they could
appear in any order – this is the hallmark of a concurrent system
Synthesizer
HDL code can be synthesized into a physical circuit description, and
then implemented in any one of several technologies (FPGAs are
common targets).

Structural and behavioral code will synthesize to the same circuit…

Structural Verilog assists module reuse and simulation visibility –
but the synthesizer doesn’t care.
The simplest Verilog designs use behavioral descriptions to specify
simple logic circuits in a single module.

Most “real world” designs use hierarchy, where more complex circuits
are constructed from simpler modules using “structural Verilog”.

Engineers typically maintain libraries of basic Verilog modules that can

be reused to more quickly construct digital systems.

Pre-designed Verilog are generally known as “IP blocks”; today, you can
download any one of thousands of IP blocks.
Why use an HDL?
Text-based – any editor will do

Straight-forward syntax, rules, and design methods; code

is often self-documenting
Can describe behavior (easier than describing structure).

Can be simulated – this is huge!

Can be synthesized – also huge!

End.