Class Note: L13 Faculty name-

EC-502 Microprocessors & Microcontrollers Avanish Kumar Jayank

(Dept. of ECE, FOET, University of Lucknow)
UNIT II
Hardware Interfacing with 8085 : Methods of data Transfer and Interrupts of 8085 microprocessor:
Classification of interrupts, programming using interrupts, direct memory access, serial and parallel data
transfer, interfacing of memory chips with 8085 microprocessor, interfacing of 8085 with 8155/8156 (RAM),
8355/8755 (ROM). Interfacing of programmable devices with 8085 microprocessor, 8279 programmable
keyboard/display interface, 8255A programmable parallel interface, 8254 programmable interval timer,
8259A programmable interrupt controller, assembly language programming.

Data transfer schemes of 8085 microprocessor

In 8085 microprocessor based systems several input and output devices are
connected. We know that data transfer may take place between microprocessor and
memory, microprocessor and I/O devices and memory & I/O devices. As we know
not much of the problems arise for the data communication between microprocessor
and memory as same technology is used in the manufacturing of memory and
microprocessor.
The main reason for that the speed of the memory is almost compatible with the
speed of 8085 microprocessor. Now the main concern is for the data transfer between
the microprocessor and I/O devices. The main problems arise due to mismatch of the
speed of the I/O devices and the speed of microprocessor or memory. To overcome
this problem of speed mismatch between the microprocessor and I/O devices we have
to do something. For that reason only we introduce data transfer schemes of 8085
microprocessor.
So following data transfer schemes may be considered for smooth data transfer
process. The data transfer schemes of 8085 microprocessor were categorised
depending upon the capabilities of I/O devices for accepting serial or parallel data.
The 8085 microprocessor is a parallel device. That means it transfers eight bits of
data simultaneously over eight data lines (parallel I/O mode).

However in many situations, the parallel I/O mode is either impractical or impossible.
For example, parallel data communication over a long distance becomes very
expensive. Similarly, parallel data communication is not possible with devices such
as CRT terminal or Cassette tape etc.

Serial I/O mode transfer

For these devices and for these reasons serial I/O mode is used. In serial I/O mode
transfer a single bit of data on a single line at a time. For serial I/O data transmission
mode, 8-bit parallel word is converted to a stream of eight serial bit using parallel-to-
serial converter. Similarly, in serial reception of data, the microprocessor receives a
stream of 8-bit one by one which are then converted to 8- bit parallel word using
serial-to-parallel converter. For this purpose data transfer schemes of 8085
microprocessor are introduced.

Parallel data transfer scheme

Parallel data transfer scheme is faster than serial I/O transfer. in parallel data transfer
8-bit data send all together with 8 parallel wire. In 8085 microprocessor mainly three
types of parallel data transfer scheme we observed.
Those are:-
• Programmed I/O Data Transfer
• Interrupt Driven I/O Data Transfer
• Direct Memory Access (DMA) Data Transfer.
 Interrupts in 8085 microprocessor
When microprocessor receives any interrupt signal from peripheral(s) which are
requesting its services, it stops its current execution and program control is
transferred to a sub-routine by generating CALL signal and after executing sub-
routine by generating RET signal again program control is transferred to main
program from where it had stopped.
When microprocessor receives interrupt signals, it sends an acknowledgement
(INTA) to the peripheral which is requesting for its service.
Interrupts can be classified into various categories based on different parameters:
1. Hardware and Software Interrupts –
When microprocessors receive interrupt signals through pins (hardware) of
microprocessor, they are known as Hardware Interrupts. There are 5 Hardware
Interrupts in 8085 microprocessor. They are – INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP
Software Interrupts are those which are inserted in between the program which
means these are mnemonics of microprocessor. There are 8 software interrupts in
8085 microprocessor. They are – RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST
6, RST 7.

2. Vectored and Non-Vectored Interrupts –

Vectored Interrupts are those which have fixed vector address (starting address of
sub-routine) and after executing these, program control is transferred to that address.
Vector Addresses are calculated by the formula 8 * TYPE
INTERRUPT VECTOR ADDRESS
TRAP (RST 4.5) 24 H
RST 5.5 2C H
RST 6.5 34 H
RST 7.5 3C H
For Software interrupts vector addresses are given by:
INTERRUPT VECTOR ADDRESS
RST 0 00 H
RST 1 08 H
RST 2 10 H
RST 3 18 H
RST 4 20 H
RST 5 28 H
RST 6 30 H
RST 7 38 H
Non-Vectored Interrupts are those in which vector address is not predefined. The
interrupting device gives the address of sub-routine for these interrupts. INTR is the
only non-vectored interrupt in 8085 microprocessor.

3. Maskable and Non-Maskable Interrupts –

Maskable Interrupts are those which can be disabled or ignored by the
microprocessor. These interrupts are either edge-triggered or level-triggered, so they
can be disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts in 8085
microprocessor.
Non-Maskable Interrupts are those which cannot be disabled or ignored by
microprocessor. TRAP is a non-maskable interrupt. It consists of both level as well as
edge triggering and is used in critical power failure conditions.

Priority of Interrupts –
When microprocessor receives multiple interrupt requests simultaneously, it will
execute the interrupt service request (ISR) according to the priority of the interrupts.

Instruction for Interrupts –

1.Enable Interrupt (EI) – The interrupt enable flip-flop is set and all interrupts
are enabled following the execution of next instruction followed by EI. No flags
are affected. After a system reset, the interrupt enable flip-flop is reset, thus
disabling the interrupts. This instruction is necessary to enable the interrupts
again (except TRAP).

2.Disable Interrupt (DI) – This instruction is used to reset the value of enable
flip-flop hence disabling all the interrupts. No flags are affected by this
instruction.
3.Set Interrupt Mask (SIM) – It is used to implement the hardware interrupts
(RST 7.5, RST 6.5, RST 5.5) by setting various bits to form masks or generate
output data via the Serial Output Data (SOD) line. First the required value is
loaded in accumulator then SIM will take the bit pattern from it.
4. Read Interrupt Mask (RIM) – This instruction is used to read the status of the
hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by loading into the A register a byte
which defines the condition of the mask bits for the interrupts. It also reads the
condition of SID (Serial Input Data) bit on the microprocessor.