DEPARTMENT OF ELECTRONICS AND VLSI DESIGN AND TECHNOLOGY

QUESTION BANK
SUBJECT : 22VLT402-COMPUTER ARCHITECTURE AND ORGANIZATION
SEM/YEAR: IV/II
UNIT-I COMPUTER ORGANIZATION & INSTRUCTIONS
Basics of a computer system: Evolution, Ideas, Technology, Performance, Power wall, Uniprocessors to
Multiprocessors. Addressing and addressing modes. Instructions: Operations and Operands, Representing
instructions, Logical operations, control operations.
PART-A
Q.No Questions BT Competence
Level
1 Express the equation for the dynamic power required per transistor. BTL 2 Understanding

2 Identify general characteristics of Relative addressing mode BTL4 Analyzing

with an exam le.
3 List the eight great ideas invented by computer architects. BTL 1 Remembering
4 Tabulate are the components of computer system. BTL 1 Remembering
5 Distinguish Pipelining from Parallelism. BTL 2 Understanding
6 Interpret the various instructions based on the operations they BTL2 Understanding
perform and give one example to each category.
7 Differentiate DRAM and SRAM. BTL 4 Anal in
8 Give the components of a computer system and list their functions. BTL 2 Understanding

9 What is the MIPS code for the statement BTL 1 Remembering

f=(g+h)-(i+j).
10 Calculate throughput and response time. BTL 3 Analyzin
g
11 Compose the CPU performance equation. BTL 6 Creating
12 Measure the performance of the computers: BTL 5 Evaluating
If computer A runs a program in 10
seconds, and computer B runs the same
program in 15 seconds, how much faster is
A over B?
13 Formulate the equation of CPU execution BTL 6 Creating
time for a program.
14 State the need for indirect addressing mode. BTL 1 Remembering
Give an example.
15 Show the formula for CPU clock cycles BTL 3
required for a program.
16 Define Stored Program Concept. BTL 1 Remembering
17 Name the different addressing modes. BTL 1 Remembering
18 Compare multi-processor and uniprocessor. BTL4 Analzing
19 Illustrate relative addressing mode with BTL 3 Applying
example.
20 BTL 5 Evaluating
Consider the following performance
measurements for a program. which
computer has the higher MIPS rating
 Measurement Computer A Computer B
Instruction 10 billion 8 billion
Count
Clock Rate 4GHz 4GHz
CPI 1.0 1.1

PART B
1 i).Summarize the eight great ideas of computer Architecture. (7) BTL5 Evaluating
ii). Explain the technologies for Building Processors. (6)
2 List the various components of computer system and explain with (13) BTL Remembering
neat diagram. 1
3 i).Define addressing mode. (4) BTL Remembering
ii).Describe the basic addressing modes for MIPS and give one (9) 1
suitable exam le instruction to each cate o
4. Examine the operands and operations of computer hardware. 13 BTL Remembering
1
5 i).Discuss the logical operations and control operations of (7) BTL Understanding
computer. 2
6
ii). Express the concept of Powerwall processor.
6 Consider three different processors PI, P2, and P3 executing the BTL Analyzing
same instruction set. PI has a 3 GHz clock rate and a CPI of 1.5. 4
P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz
clock rate and has a CPI of 2.2.
i).Which processor has the highest performance expressed in
instructions per second?
ii).If the processors each execute a program in 10 seconds, find (3)
the number of cycles and the number of instructions?
iii).We are trying to reduce the execution time by 30% but this (5)
leads to an increase of 20% in the CPI. What clock rate should
we have to get this time reduction? (5)
7 Assume a program requires the execution of 50 x 106 FP BTL3 Applying
instructions,110 x 106 INT instructions, 80 x 106 L/S
instructions, and 16 x 106 branch instructions The CPI for each
type of instruction is 1, 1, 4, and 2, respectively. Assume that
the processor has a 2 GHz clock rate.
i).By how much must we improve the CPI of FP instructions if
we want the program to run two times faster?
ii).By how much must we improve the CPI of L/S instructions? (4)
iii).By how much is the execution time of the program
improved if the CPI of INT and FP Instructions are reduced by (4)
40% and the CPI of L/S and Branch is reduced by 30%? (5)
8 Recall how performance is calculated in a computer system and (13) BTL2 Understanding
derive the necessary performance equations.
9 i).Formulate the performance of CPU. (7) BTL6 Creating
ii).Compose the factors that affect performance. 6
10 i).Illustrate the following sequence of instructions and identify (7) BTL 3 Applying
the addressing modes used and the operation done in every
instruction
(1) Move (R5)+, RO
(2) Add(R5)+, RO
(3) Move RO, (R5)
(4) Move 16(R5),R3
(5) Add #40, R5
ii).Calculate which code sequence will execute faster according to (6)
execution time for the following conditions:
Consider the computer with three instruction classes and CPI
measurements as given below and instruction counts for each

instruction class for the same program from two different

compilers are given. Assume that the computer's clock rate is
IGHZ
Code from CPI for the instruction class

CPI 1 2 3
Code from CPI for the instruction class

Compiler 1 2 1 2
Compiler 2 2 1 1
11 Consider two different implementation of the same instruction (13) BTL 1 Remembering
(13) set architecture, The instruction can be divided into four
classes according to their CPI ( class A,B,C and D). P1 with
clock rate 2.5 Ghz and CPI s of 1,2,3, and 3 respectively and P2
with clock rate 3 Ghz and CPI s of 2,2,2and 2 respectively.
Given a program with a dynamic instruction count of 1.0*10°
instruction divided into classes as follows: 10% class A, 20%
class B, 50% class C, and 20% class D, which implementation is
faster? What is the global CPI for each implementation? Find the
clock cycles required in both cases.
12 i). Compare uni-processors and multi- processors. (3) BTL 4 Analyzing
ii). Analyze how instructions that involve decision making are (10)
executed with an example.
13 Analyze the various instruction formats and illustrate with an (13) BTL 4 Analyzing
example.
14 ()With suitable examples, Summarize the compilation of assignment (8) BTL Understanding
statements into MIPS. 2
(ii)Translate the following C code to MIPS assembly code .Use a (5)
minimum number of instructions. Assume that I and k correspond to
register $s3 and $s5 and the base of the array save is in $s6.What is the
MIPs assembly code corresponding to this is C segment
While(save[i]==k) i+=1;

PART C
 Assume that the variables f and g are assigned to register Ss0 (15) BTL Creating
1 and SSI respectively. Assume that base address of the array A is 6
in register Ss2. Assume f is zero initially.
f- -g-- A[4]
A[5]=f+ 100
Translate the above C statement into MIPS code. how many
MIPS assembly instructions are needed to perform the C
statements and how many different registers are needed to carry
out the C statements ?
2 Integrate the eight ideas from computer architecture to the (5) BTL 6 Creating
following ideas from other fields: (5)
i). Assembly lines in automobile manufacturing. (5)
ii). Express elevators in buildings.
iii) .Aircraft and marine navigation systems that incorporate wind
information.
3 Evaluate a MIPS assembly instruction in to a machine instruction, for the BTL5 Evaluating
(15)
add Sto, $s1,$s2 MIPS instruction.
4 Explain the steps to convert the following high level language (15) such BTL5 Analyzing
as C into a MIPS code. a=b+e; c=b+f;

UNIT-II -ARITHMETIC
Fixed point Addition, Subtraction, Multiplication and Division. Floating Point
arithmetic, High
arithmetic, Subword parallelism performance
PART-A
Q.NO Questions Competence
Level
1 Calculate the following: Add 510 to 610 in binary and Subtract -6 10 BTL3 Applying
from 710 in binary.
2 Analyze overflow conditions for addition and subtraction. BTL4 Analyzing
3 Construct the Multiplication hardware diagram. BTL3 Applying
4 List the steps of multiplication algorithm. BTL 1 Remembering
5 What is meant by ALU fast multiplication? BTL 1 Remembering
6 Subtract (11011)2 — (10011)2 using 1's complement and 2’s BTL2 Understanding
complement method.
7 Illustrate scientific notation and normalization with example. BTL3 Applying
8 Perform X-Y using 2 's complement arithmetic for the given two BTL4 Analyzing
16-bit numbers X=0000 1011 1110 1111 and Y=1111 0010
1001 1101.
9 Contrast overflow and underflow with examples. BTL2 Understanding
10 State the rules to add two integers. BTL6 Creating
11 Name the floating point instructions in MIPS. BTL 1 Remembering
12 Formulate the steps of floating point addition. BTL6 Creating
13 Evaluate the sequence of floating point multiplication. BTL5 Evaluating
Define scientific notation and normalized notation. BTL Remembering
15 Express the IEEE 754 floating point format. BTL2 Understanding
16 State sub-word parallelism and the data path in CPU. BTL Remembering
17 Interpret single precision floating point number representation BTL2 Understanding
with example and the representation of double precision floating
point number.
18 Divide 1,001,010 by 1000. BTL4 Analyzing
19 Describe edge triggered clocking. BTL 1 Remembering
20 For the following MIPS assembly instructions above, decide the BTL5 Evaluating
corresponding C statement? add f, g, h & add f, i, f
PART-B
1 i).Discuss the multiplication algorithm its hardware and its (6) BTL2 Understanding
sequential version with diagram. ii).Express the steps to Multiply
 2*3. (7)
2 Illustrate the multiplication of signed numbers using Booth (13) BTL3 Applying
algorithm. A=(-34)10=(1011110)2 and B=(22)10=(0010110)2
where B is multiplicand and A is multiplier.
3 Describe about basic concepts of ALU design. 13 BTL 1 Remembering
4 Develop algorithm to implement A *B. Assume A and B for a pair (13) BTL6 Creating
of signed 2's complement numbers with values: A 010111, B-
101100

5 i).State the division algorithm with diagram and examples. ii).Divide (6) BTL 1 Remembering
00000111 by 0010. (7)
6 i).Express in detail about Cany looks ahead Adder. (8) BTL2 Understanding
i) Divide(12)10 by (3)10 (7)
7 Point out how ALU performs division with flow chart and block (13) BTL4 Analyzing
diagram.
8 i).Examine with a neat block diagram how floating point addition is (10) BTL 1 Remembering
carried out in a computer system.
ii).Give an example for a binary floating point addition. (3)
9 Tabulate the IEEE 754 binary representation of the number- BTL 1 Remembering
0.7510
i).Single precision. (6)
ii).Double precision. (7)
10 i).Design an arithmetic element to perform the basic floating point (7) BTL2 Understanding
operations.
ii).Discuss sub word parallelism. (6)
11 i).Explain floating point addition algorithm with diagram. (6) BTL5 Evaluating
ii).Assess the result of the numbers (0.5)10 and (0.4375)10 using (7)
binary Floating point Addition algorithm.
12 Calculate using single precision IEEE 754 representation. BTL4 Analyzing
i). 32.75 ii).18.125 (6)
(7)
13 Arrange the given number 0.0625 BTL4 Analyzing
i). Single precision. (6)
ii). Double precision formats. (7)
Solve using Floating point multiplication algorithm BTL3 Applying
i). A = 1.1010x10^10 B-9.200XIO^-5 ii). (7)
0.510 X 0.437510 (6)
PART C
1 Create the logic circuit for CLA. What are the disadvantages of (15) BTL6 Creating
Ripple cany addition and how it is overcome in cany look ahead
adder?
Evaluate the sum of 2.6125 * 101 and 4.150390625 * 101 by (15) BTL5 Evaluating
hand, assuming A and B are stored in the 16-bit half precision.
Assume 1 guard, 1 round bit and 1 sticky bit and round to the
2.
 nearest even. Show all the steps.
3 Summarize 4 bit numbers to save space, which implement the (15) BTL5 Evaluating
multiplication algorithm for 00102 , 00112 with hardware design.
4 Design 4 bit version of the algorithm to save pages, for dividing (15) BTL6 Creating
000001112, by 00102, with hardware design.
UNIT-III- THE PROCESSOR
Introduction, Logic Design Conventions, Building a Datapath - A Simple Implementation scheme - An
Overview of Pipelining - Pipelined Datapath and Control. Data Hazards: Forwarding versus Stalling, Control
Hazards, Exceptions, Parallelism via Instructions.
PART-A
Q.NO Questions Competence
Level
1 Express the truth table for AND gate and OR gate. BTL2 Understanding
2 Define hazard. Give an example for data hazard. BTL2 Understanding

3 Recall pipeline bubble. BTL 1 Remembering

4 List the state elements needed to store and access an instruction. BTL Remembering
5 Describe the main idea of ILP. BTL2 Understanding
6 Distinguish the hazards with respect to processor function. BTL2 Understanding
7 Name the use of different logic gates. BTL 1 Remembering
8 Evaluate branch taken and branch not taken in instruction BTL5 Evaluating
execution.
9 State the ideal CPI of a pipelined processor. BTL 1 Remembering
10 Design the instruction format for the jump instruction. BTL6 Creating
11 Classify the different types of hazards with examples. BTL4 Analyzing
12 Illustrate the two steps that are common to implement any type of BTL3 Applying
instruction.
13 Assess the methods to reduce the pipeline stall. BTL5 Evaluating
Tabulate the use of branch prediction buffer. BTL Remembering
15 Show the 5 stages pipeline. BTL3 Applying
16 Point out the concept of exceptions. Give one example of MIPS BTL4 Analyzing
exception.
17 What is pipelining? BTL 1 Remember
18 Illustrate how to organize a multiple issue processor? BTL3 Applying
19 Neatly sketch three primary units of dynamically scheduled BTL4 Analyzing
pipeline.
20 Generalize Exception. Give one example for MIPS exception. BTL6 Creatin
PART-B
1 Discuss the basics of logic design conventions. (13) BTL2 Understanding
2 i) State the MIPS implementation in detail with necessary (7) BTL 1 Remembering
multiplexers and control lines.
ii) Examine and draw a simple MIPS datapath with the control
unit and the execution of ALU instructions. (6)
3 i).Define parallelism and its types. (3) BTL 1 Remembering
ii).List the main characteristics and limitations of Instruction level (10)
parallelism.
4 Design and develop an instruction pipeline working under various (13) BTL6 Creating
situations of pipeline stall.
5 i).What is data hazard? (3) BTL 1 Remembering
ii). Explain stalls with neat diagrams and suitable examples. (10)
6 i).Summarize the speculation scheme. (3) BTL2 Understanding
ii).Distinguish static and dynamic techniques for speculation. (10)
7 i).Differentiate sequential execution and pipelining. (3) BTL4 Analyzing
ii). Explain the process of building single data path with neat (10)
diagram.
8 Recommend the techniques for BTL5 Evaluating
i).Dynamic branch prediction. (7)
ii).Static branch prediction. (6)
9 Examine the approaches would you use to handle exceptions in (13) BTL3 Applying
MIPS.
10 i).Analyze the hazards caused by unconditional branching (7) BTL4 Analyzing
statements and pipelining a processor using an example.
ii).Describe operand forwarding in a pipeline processor with a (6)
diagram.

11 Express the simple data path with control unit and modified data (13) BTL Understanding
path to accommodate pipelined executions with a diagram. 2
12 With a suitable set of sequence of instructions show what (13) BTL Applying
happens when the branch is taken, assuming the pipeline is 3
optimized for branches that are not taken and that we moved the
branch execution to the stage.
13 i) Define multiple issue. (3) BTL Remembering
ii) Differentiate static and dynamic multiple issues. (10) 1
14 i).Explain single cycle and pipelined performance with examples. (7) BTL Analyzing
ii).Point out the advantages of pipeline over single cycle and (6) 4
limitations of pipelining a processor's datapath. Suggest the
methods to overcome the later part
PART C
1 Assume the following sequence of instructions are executed on a BTL6 Creating
5 stage pipelined processor
Or rl ,r2,r3
Or r2,rl ,r4
Or rl, r1, ,r2
i) Indicate dependences and their type.
ii) Assume there is no forwarding in this pipelined processor. (5)
Indicate hazards and add NOP instructions to eliminate them. (5)
iii) Assume there is a full forwarding .Indicate hazard and add
NOP instructions to eliminate them. (5)
2 Consider the following code segment in C: A=b+e; c=b+f; Here (15) BTL Evaluating
(15) |BTL 5| Evaluating is the generated MIPS code for this 5
segment, assuming all variables are in memory and are
addressable as off sets from $t0:
1w $t1, 0($t0)
1w $t2, 4($t0)
add $t3, $t1, $t2
sw $t3, 12($t0)
1w $t4, 8($t0)
add $t5, $t1,St4
sw St5, 16($t0)
Find the hazards in the preceding code segment and reorder the
instructions to avoid any pipeline stalls.
3 Consider the following loop: BTL Evaluating
Loop: 1wr1,0(r1) 5
and rl,rl,r2
1w r1,0(r1)
Iw,r1,0(r1)
beq,r1,r0,loop
Assume that perfect branch prediction is used (no stalls) that
there are no delay slots, and that the pipeline has full forwarding
support. Also assume that many iterations of this loop are
executed before the loop exits.
i).Assess a pipeline execution diagram for the third iteration of
this loop. (8)
ii).Show all instructions that are in the pipeline during these cycles
(for all iterations). (7)

4 Plan the pipelining in MIPS architecture and generate the (15) BTL6 Creating
exceptions handled in MIPS.
UNIT IV- MEMORY AND 1/0 ORGANIZATION
Memory hierarchy, Memory Chip Organization, Cache memory, Virtual memory.
Parallel Bus Architectures, Internal Communication Methodologies, Serial Bus
Architectures, Mass storage, Input and Output Devices
PART-A
Q.NO Questions Competence
Level
1 Distinguish the types of locality of references. BTL2 Understanding
2 Define the structure of memory hierarchy in a typical computer BTL 1 Remembering
system and draw its diagram.
3 Give how many total bits are required for a direct mapped cache BTL2 Understanding
with 16KB of data and 4-word blocks, assuming a 32 bit address.
4 Compare and contrast SRAM and DRAM BTL4 Analyzing
5 What is miss penalty? BTL 1 Remembering
6 Describe Rotational Latency. BTL 1 Remembering
7 State is direct-mapped cache. BTL Remembering
8 Evaluate Hit Ratios and Effective Access Times in cache BTL5 Evaluating
9 Formulate Fragmentation in virtual memory BTL6 Creating
10 Analyze the writing strategies in cache memo BTL4 Analyzin
11 Integrate the functional steps required in an instruction cache miss BTL6 Creating

12 State hit rate and miss rate. BTL 1 Remembering

13 Summarize the various block placement schemes in cache BTL2 Understanding
memory.
Identify the purpose of Dirty/Modified bit in Cache memory. BTL 1 Remembering
15 Point out the use of parallel bus architecture? BTL4 Analyzing
16 Show the role of TLB in virtual memory. BTL3 Applying
17 Illustrate the advantages of virtual memory. BTL3 Applying
18 Assess the use of Overlays in memory. BTL5 Evaluating
19 Differentiate Paging and segmentation. BTL2 Understanding
20 Demonstrate the sequence of events involved in handling Direct BTL3 Applying
Memory Access.
PART-B
1 i).Define parallelism and its types. (7) BTL 1 Remembering
ii).List the main characteristics and limitations of Instruction level (6)
parallelism.
2 i).Define virtual memory and its importance. (7) BTL2 Understanding
ii).Examine TLB with necessary diagram .What is its use? (6)
3 i).List the various memory technologies and examine its relevance (7) BTL2 Understanding
in architecture design.
ii). Identify the characteristics of memory system. (6)
4 Apply how Internal Communication Methodologies is useful in (13) BTL3 Applying
developing computer architecture.
5 i).Demonstrate the DMA controller. Discuss how it improves the (7) BTL 1 Remembering
overall performance of the system.
ii).Illustrate how DMA controller is used for direct data transfer (6)
between memory and peripherals?
6 Point out the need for cache memory. Explain the following three (13) BTL4 Analyzing
mapping methods with examples.
i). Direct.
ii).Associative. iii).Set
associative.
7 Evaluate the features of Bus Arbitration-Masters and Slaves. (13) BTL5 Evaluating
8 Generalize the Bus Structure, Protocol, and Control in Parallel Bus (13) BTL6 Creating
Architecture
9 i).Classify the types of memory chip organization. (7) BTL4 Analyzing
ii).Analyze the advantages of cache and virtual memory (6)
10 Elaborate in detail about the following in Parallel Bus Architectures BTL 1 Remembering
i).The Synchronous Bus (7)
ii).The Asynchronous Bus (6)

11 i).Give the advantages of cache. (6) BTL4 Analyzing

ii).Identify the basic operations of cache in detail with diagram. (7)
12 Describe the principle approaches of Serial Bus Architectures with (13) BTL 1 Remembering
necessary diagrams.
13 Illustrate the following in detail BTL3 Applying
1). Magnetic Disks (5)
ii). Magnetic Tape (4)
iii). Optical Disks (4)
14 Discuss the following in detail BTL2 Understanding
1). Input Devices. (7)
ii). Output Devices. (6)
PART C
1 Generalize the merits and demerits of Parallel Bus Architectures, (15 BTL 6 Creating
Bridge-Based Bus Architectures and Serial Bus Architectures. )
2 For a direct mapped cache design with a 32 bit address, the BTL 5 Evaluating
following bits of the address are used to access the cache. Tag : 31-
10 Index: 9-5 Offset: 4-0
i). Judge what is the cache block size?
ii).Decide how many entries does the cache have? (5)
iii).Assess what is the ratio between total bits required for such a (5)
cache implementation over the data storage bits? (5)
3 Develop methods to constructing large RAMS from small RAMS (15) BTL6 Creating
and commercial memory modules
4 Summarize the virtual memory organization followed in digital (15) BTL5 Evaluating
computers.
UNIT V- ADVANCED COMPUTER ARCHITECTURE

Parallel processing architectures and challenges, Hardware multithreading, Multicore and shared memory
multiprocessors, Introduction to Graphics Processing Units, Clusters and Warehouse scale computers - Introduction
to Multiprocessor network topologies.
PART-A
Q.NO Questions Competence
Level
1 Describe the main idea of Parallel processing architectures. BTL2 Understanding
2 Illustrate how to organize a clusters. BTL3 Applying
3 List the network topologies in parallel processor. BTL Remembering

4 Analyze the main characteristics of SMT processor. BTL4 Analyzing

5 Quote the importance of Graphics Processing Units. BTL Remembering
6 Define multicore microprocessor. BTL Remembering
7 Express Warehouse scale computers. BTL2 Understanding
8 State the overall speedup if a webserver is to be enhanced with a BTL 1 Remembering
new CPU which is 10 times faster on computation than an old
CPU . The original CPU spent 40% of its time processing and
60% of its time waiting for I/O.
9 Differentiate between SIMD and MIMD BTL2 Understanding
10 Show the performance of cluster organization. BTL3 Applying
11 Compare SMT and hardware multithreading BTL5 Evaluating
12 Identify the Flynn classification and give an example for each BTL 1 Remembering
class in Flynn's classification.
13 Integrate the ideas of multistage network and cross bar network. BTL6 Creating
Discriminate UMA and NUMA. BTL5 Evaluating
15 Describe fine grained multithreading. BTL 1 Remembering
16 Express the need for instruction level parallelism. BTL2 Understanding
17 Formulate the various approaches to hardware multithreading. BTL6 Creating
18 Categorize the various multithreading options. BTL4 Analyzing
19 Compare fine grained multithreading and coarse grained BTL4 Analyzing
multithreading
20 Classify shared memory multiprocessor based on the memory BTL3 Applying
access latency.

PART-B

1 i).Define parallelism and its types. (4) BTL 1 Remembering

ii).List the main characteristics and limitations of Instruction level (9)
parallelism.
2 i).Give the software and hardware techniques to achieve (4) BTL2 Understanding
Instruction level parallelism.
ii).Summarize the facts or challenges faced by parallel processing (9)
i] enhancing computer architecture.
3 Express in detail about hardware multithreading. (13) BTL2 Understanding
4 Apply your knowledge on graphics processing units and explain (13) BTL3 Applying
how it helps computer to improve processor performance.
5 Describe data level parallelism in BTL 1 Remembering
(6)
i).SMD.
(7)
 ii).MISD.
6 i).Point out how will you classify shared memory multi-processor (7) BTL4 Analyzing
based on memory access latency.
ii).Compare and contrast Fine grained, Coarse grained (8)
multithreading and Simultaneous Multithreading.
7 Evaluate the features of Multicore processors. (13) BTL5 Evaluating
8 i).Classify the types of multithreading. (9) BTL4 Analyzing
ii).Analyze the advantages in multithreading. (4)
9 Formulate the classes in Flynn's Taxonomy of computer (13) BTL6 Creating
Architecture classification with example.
10 Elaborate in detail about the following

i).SISD. (8) BTL 1 Remembering

ii).MIMD (5)
11 Explain simultaneous Multithreading with example. (13) BTL4 Analyzing
12 Describe the four principle approaches to multithreading with (13) BTL 1 Remembering
necessary diagrams.
13 Illustrate the following in detail BTL 3 Applying
i). Clusters (7)
ii).Wharehouse scale computers (6)
Discuss the multiprocessor network topologies in detail. (13) BTL2 Understanding
PART C
1 Evaluate the below C code using MIMD and SIMD machine as (15) BTL 5 Evaluating
efficient as possible:
For(i=0;i<2000;i++)
For(j=0;j<3000;j++)
X_array[i][j]=y_array[j][i]+200;
2 Write down a list of your daily activities that you typically do on (15) BTL 6 Creating
a weekday. For instance get out of bed, take a shower, get
dressed, eat breakfast, brush your teeth, dry your hair etc
(minimum ten activities). Which of these activities can be done
in form of parallelism. For each activity discuss if they are
working in parallel, but if not, why they are not. Estimate how
much shorter time it will take to complete all the activities if it is
done in parallel.
3 Consider the following portions of two different programs BTL 6 Creating
running at the same time on four processors in a symmetric
multicore processor (SMP). Assume that before this code is run,
both x and y are 0? Core l: x=2;
Core 2: y=2;
Core 3: w=x+ y +1; Core
4: z=x + y;
i. What if all the possible resulting values of w, ? For each
possible outcomes, explain how we might arrive at those values.
ii. Develop the execution more deterministic so that only one set (8)
of values is possible?
(7)
4 Summarize the merits and demerits of clusters and warehouse (15) BTL 5 Evaluating
scales computer.