KTU - CST202 - Computer Organization and Architecture Module: 2

9
may span more than one word of memory, and which may specify more complicated operations.

Let’s consider task C = A + B, implemented as C←[A] + [B]. Figure 8 shows a possible

directly specified in Load and Store instructions, although this is not possible if a full 32-bit address

instructions, one at a time, in the order of increasing addresses. This is called straight-

 During the execution of each instruction, the PC is incremented by 4 to point to the

 Then, the processor control circuits use the information in the PC to fetch and execute
length is 32 bits and the memory isbyte-addressable. The four instructions of the program are in

Since each instruction is 4 bytes long, the second, third, and fourth instructions are at
addresses i + 4, i + 8, and i + 12. For simplicity, we assume that a desired memory address can be

contains the value i + 16, which is the address of the first instruction of the next program
program segment for this task as it appears inthe memory of a computer. We assume that the word

next instruction. Thus, after the Store instruction at location i + 12 is executed, the PC
 To begin executing a program, the address of its first instruction (i in our example)
Computers based on this idea have been subsequently called ComplexInstruction Set Computers

KTU - CST202 - Computer Organization and Architecture Module: 1

An alternative
An alternative to
to the
the RISC
RISC approach
approach is
is to
to make
make use
use of
of more
more complex
complex instructions
instructions which
which
may span
may span more
more than
than one
one word
word of
of memory,
memory, and
and which
which may
may specify
specify more
more complicated
complicated operations.
operations.
Computers based
Computers based on
on this idea have
this idea have been
been subsequently
subsequently called
called ComplexInstruction
ComplexInstruction Set
Set Computers
Computers KTU - CST202 - Computer Organization and Architecture Module: 1
(CISC).
(CISC).
The sum / result formed in A may be used for other computation or may be
transfered to a required destination.
Instruction Execution
Instruction Execution and
and Straight-Line
Straight-Line Sequencing
Sequencing EXECUTION OF A COMPLETE INSTRUCTION
Status Registers
Let’s consider
Let’s consider task
task CC= =AA+ + B,
B, implemented
implemented as
as C←[A]
C←[A] + + [B].
[B]. Figure
Figure 8
8 shows
shows aa possible
possible
program segment
program segment for
for this
this task
task as
as it
it appears
appears inthe
inthe memory
memory of
of aa computer.
computer. WeWe assume
assume that
that the
the word
word Consider the instruction Add (R3),R1 which adds the contents of a memory location The relative magnitude of two numbers may be determined by subtracting one number
length is
length is 32
32 bits
bits and
and the
the memory
memory isbyte-addressable.
isbyte-addressable. The
The four
four instructions
instructions of
of the
the program
program are
are in
in pointed to by R3 to register R 1. from the other andthen checking certain bit conditions in the resultant difference. This status bit KTU - CST202 - Computer Organization and Architecture Module: 2
successive word
successive word locations,starting
locations,starting atat location
location i.
i. conditions (often calledcondition-code bits or flag bits) are stored in a status register.
Executing this instruction requires the following actions:
Status register is a 4 bit register. The four bits are C (carry), Z (zero),S (sign) and V The logic circuit can be combined with the arithmetic circuit to produce one arithmetic
1. Fetch the instruction.
(overflow).These bits are set or cleared as a result of an operation performed in the ALU. logic unit. Selection variables S1 and S0 can be made common to both sections provided we use a
2. Fetch the first operand (the contents of the memory location pointed to by R3).
Bit C is set if the output carry of an ALU is 1.
 third selection variable, S2, to differentiate between the two. This configuration is illustrated in
3. Perform the addition.
the above figure. The outputs of the logic and arithmetic circuits in each stage go through a
4. Load the result into RI. Bit S is set to 1 if the highest order bit of the result in the output of the ALU is 1.

multiplexer with selection variable S2.
Bit Z is set to 1 if the output of the ALU contains all O's.

Instruction execution proceeds as follows. When S2 = 0, the arithmetic output is selected,
Bit V is set if the exclusive —OR of carries C8 and C9 is 1, and cleared otherwise.

Instruction Execution and Straight-Line Sequencing

Figure 8

Step 1: The instruction fetch operation is initiated

Let us consider how this program is executed.

This is the condition for overflow when the numbers are in signed 2's complement when S2 = 1, the logic output is selected.
by loading the contents of the PC into the MAR and representation. For an 8 bit ALU, V is set if the result is greater than 127 or less
sending a Read request to the memory. The Select signal is [To extend the sign bit - since its 5 bit signed operand, 10 bit product should be generated. than
KTU - CST202 -128.
- Computer Organization and Architecture Module: 2
Although the two circuits can be combined in this manner, this is not the best way to design
an ALU.A more efficient ALU can be obtained if we investigate the possibility of generating logic
successive word locations,starting at location i.

set to Select4, which causes the multiplexer MUX to select

the constant 4. This value is added to the operand at input
So, if the partial product’s MSB is 1, add 1 for signAfter
extension (tostatus
an ALU operation, left),
bits can be checked to determine the relationship that exist operations in an already available arithmetic circuit. This can be done by inhibiting all input carries
between thevalues of A and B.
Figure 8
Figure 8
B, which is the contents of the PC, and the result is stored if the partial product’s MSB is 0, add 0 for sign extension (to left)] into the full-adder circuits of the parallel adder. Consider the Boolean function that generates the
output sum in a full-adder circuit:
Since each instruction
instruction is
is 44 bytes
bytes long,
long, the
the second,
second, third,
third, and
and fourth
fourth instructions
instructions are
are at
at in register Z.
must be placed into the PC.

Since each
addresses ii +
addresses + 4,
4, ii +
+ 8,
8, and
and ii +
+ 12.
12. For
For simplicity,
simplicity, we
we assume
assume that
that aa desired
desired memory
memory address
address can
can be
be 13 F=X ْ Y ْ Cin
Step 2: The updated value is moved from register Z
directly specified
directly specified in
is involved.
is involved.
in Load
Load and
and Store
Store instructions,
instructions, although
although this
this is
is not
not possible
possible if
if aa full
full 32-bit
32-bit address
address
back into the PC, while waiting for the memory to respond. Example: Sign extension of negative multiplicand The input carry Cin in each stage can be made to be equal to 0 when a selection variableS2is
Figure 16 equal to 1. The result would be:
Let us
us consider
consider how
how this
this program
program is
is executed.
executed. Step 3:The word fetched from the memory is loaded
Let [To extend the sign bit - since its 5 bit signed operand, 10 bit product should be generated. F=X ْ Y
line sequencing.

into the IR.

To begin
To begin executing
executing aa program,
program, the
 the address
address ofof its
its first
first instruction
instruction (i
(i in
in our
our example)
example) So, if the partial product’s MSB is 1, add 1 for sign extension (to left), This expression is valid because of the property of the X-OR operation: Xْ0 = X
must be
must be placed
placed into
into the
the PC.
PC. (Steps 1 through 3 constitute the instruction fetch phase, which is the same for all if the partial product’s MSB is 0, add 0 for sign extension (to left)]
Then, the
Then, the processor
processor control
control circuits
 circuits use
use the
the information
information in in the
the PC
PC to
to fetch
fetch and
and execute
execute instructions.) Design of Arithmetic Logic Unit
segment.

instructions, one
instructions, one at
at aa time,
time, in
in the
the order
order of
of increasing
increasing addresses.
addresses. This
This is
is called
called straight-
straight- Step 4: The instruction decoding circuit interprets the contents of the IR. This enables the Example: Sign extension of negative multiplicand
line sequencing.
line sequencing. The logic circuit can be combined with the arithmetic circuit to produce one arithmetic
control circuitry to activate the control signals for steps 4 through 7, which constitute the execution
During the
 During the execution
execution ofof each
each instruction,
instruction, the
the PC
PC isis incremented
incremented byby 4 4 to
to point
point to
to the
the logic unit. Selection variables S1 and S0 can be made common to both sections provided, we are
phase. The contents of register R3 are transferred to the MAR in step 4, and a memory read
next instruction.
instruction. Thus,
Thus, after
after the
the Store
Store instruction
instruction atat location
location ii +
+ 12
12 is
is executed,
executed, the
the PC
PC using a third selection variable S2, to differentiate between the two.
is involved.

next operation is initiated.

KTU - CST202
contains
contains - Computer
the value
the +Organization
value ii + 16, which
16, which isis the
theand Architecture
address
address of the
of the first
first instruction
instruction of theModule:
of the 1
next program
next program If bit V is set after the addition two signed numbers, it indicates an overflow condition. If
Design steps
(CISC).

segment.
segment. Step 5: the contents of R1 are transferred to register Y, to prepare for the addition operation. Z is set after anexclusive OR operation, it indicates that A=B. A single bit in A can be checked to
Executing a given instruction is a two-phase procedure. In the first phase, called instruction determine if it is 0 or 1by masking all bits except the bit in question and then checking the Z status 1. Design the arithmetic section independent of the logic section.
Step 6: When the Read operation is completed, the memory operand is available in register 2. Determine the logic operations obtained from the arithmetic circuit in step 1, assuming
fetch, the instruction is fetched from the memory location whose address is in the PC. This bit.
MDR, and the addition operation is performed. The contents of MDR are gated to the bus, and that the input carries to all stages are 0.
instruction is placed in the instruction register (IR) in the processor. Relative magnitudes of A and B can be checked by compare operation. If A-B is performed
9 thus also to the B input of the ALU, and register Y is selected as the second input to the ALU by 3. Modify the arithmetic circuit to obtain the required logic operations.
9 for twounsigned binary numbers, relative magnitudes of A and B can be determined from the
At the start of the second phase, called instruction execute, the instruction in IR is examined choosing SelectY.
to determine which operation is to be performed. The specified operation is then performed by the values transferred tothe C and Z bits. If Z=1,we knows that A=B, since A-B=0. If Z=0, then we The third step in the design is not a straightforward procedure and requires a certain
processor. This involves a small number of steps such as fetching operands from the memory or Step 7: The sum is stored in register Z, and then transferred to R1. The End signal causes know that A is not equal to B. amount of ingenuity on the part of the designer. There is no guarantee that a solution can be found
a new instruction fetch cycle to begin by returning to step 1. [product is10 bits ->(2n)] or that the solution uses the minimum number of gates. The example presented here demonstrates
from processor registers, performing an arithmetic or logic operation, and storing the result in the
Similarly C=1 if A>=B and C=0 if A<B. The following table lists the various conditions
the type of logical thinking sometimes required in the design of digital systems.
destination location. This discussion accounts for all control signals in Figure 7.6 except Yin in step 2. There is
no need to copy the updated contents of PC into register Y when executing the Add instruction.
[product is10 bits ->(2n)]
For a negative multiplier, a straightforward solution is to form the 2’s-complement of The final ALU is shown in figure below Only the first two stages are drawn, but the
At some point during this two-phase procedure, the contents of the PC are advanced to
point to the next instruction. When the execute phase of an instruction is completed, the PC But, in Branch instructions the updated value of the PC is needed to compute the Branch target both the multiplier and the multiplicand and proceed as in the case of a positive multiplier.diagram can be easily extended to more stages. The inputs to each full-adder circuit are specified
contains the address of the next instruction, and a new instruction fetch phase can begin. address. This is possible because complementation of both operands does not change the value or the signby the Boolean functions:
of the product.
Branching For a negative multiplier, a straightforward solution is to form the 2’s-complement of Xi = Ai + S2 S1’ S0’Bi + S2 S1 S0’ Bi
19 [If the sign bit is 0 then the number is positive, If the sign bit is 1, then the number is negative]
KTUthe
that
Consider the task of adding a list of n numbers. Assume
- CST202
number of- Computer
entries in Organization and Architecture
the list, n, is stored in memory Module: 2 both the multiplier and the multiplicand and The proceed as in the case of a positive multiplier.
Booth Algorithm 18
What is Memory Transfer in Computer Architecture?
location N, as shown.
This is possible because complementation of both operands does not
Algorithm & Flowchart change
for Booth the value or the sign
Multiplication
Types of Micro-Operations
Register R2 is used as in digital system
a counter to determine the number
of times the loop is executed. Hence, the contents of location N
 Interregister transfer micro-operation: Do not change the information content when the
of the product.
The transfer of data from a memory word to the external environment is known as a read 1. Multiplicand is placed in BR and Multiplier in QR
2. Accumulator register AC, Q are initialized to 0
are loaded into register R2 at the beginning of the program. Then, operation. The read operation in memory transfer is represented as the transfer of data from the ARITHMETIC LOGIC UNIT n+1
binary information moves from one register to another 3. Sequence counter SC is initialized to n (number of
within the body of the loop, the instruction
Arithmetic operation: Perform arithmetic on numbers stored in registers.
 [If the sign bit is 0 then the number is positive, If thebits).
address register (AR) with the selected word M for the memory into the memory buffer register
(MBR).
sign
An bitlogic
arithmetic is unit
1, (ALU)
thenis athe
multi number is negative]
operation, combinational-logic digital function.
Subtract R2, R2, #1 4. perform
It can Compare a set and
Qnof Qn+1arithmetic
basic and perform the following
operations and a set of logic operations. The ALU has a
Logic microoperation:
 Perform operations such as AND and OR on individual pairs of
reduces theincontents
bits stored registers.of R2 by 1 each time through the [AR]M MBR=Read Operation
The Booth Algorithm number01of–>selection
AC=AC+BR lines to select a particular operation in the unit. The selection lines are
loop. Execution of the loop is repeated
Shift microoperation: as long as the
Specify operations contents
for shift of
registers. decoded within the ALU so that k selection variables can specify up to 2 k distinct operations.
The control signal of the read operation starts the read operation. The read operation statement 10 –> AC=AC+BR’+1
R2 are greater than zero.
INTERWe
REGISTER TRANSFER
now introduce branch instructions. This type of
generates the data transfer from the chosen memory register M into the MBR. Algorithm & Flowchart for Booth Multiplication00 –> No arithmetic operation
14
instruction loads a new address into the program counter. As a The transfer of new data to be saved into the memory is known as the write operation. The 11-> No arithmetic operation
1. Multiplicand is placed in BR and Multiplier 5.inASHR- QR Arithmetic Shift right AC,QR
Figure 9:
Computer registers are designated by capital letters (sometimesUsing
followed byadd
a loop to numerals)
n numbers.to
result, the processor fetches and executes the instruction at this memory transfer in the write operation is described as the transfer of data from the memory buffer
denote the function of the register. [Example: R1 - Processor Register, MAR - Memory Address
new address, called the branch target, instead of the instruction
Register (holds an address for a memory unit), PC - Program Counter, IR - Instruction Register,
at the location that follows the branch instruction in sequential address order.
2. Accumulator register AC, Qn+1 are initialized6. to
register (MBR) to the address register (AR) with the chosen word M for the memory. 0 SC by 1
Decrement
SR: Status Register].The cells or flipflops of n-bit register are numbered in sequence from1 to n
(from 0Atoconditional
n-1) startingbranch
eitherinstruction
from left orcauses a branch only if a specified condition is satisfied.
from right
MBR M [AR] =Write 3.Operation.
Sequence counter SC is initialized to n The (number
final productof
will be store in AC, QR
If the condition is not satisfied, the PC is incremented in the normal way, and the next instruction
The register
in sequential addresscan be represented
order is fetched andin executed
4 ways: bits).
The control signal of the write operation starts the write operation. The write operation statement
generates the data transfer from the MBR into the chosen memory register through the address
Rectangular
 the
In program inbox with the
Figure, name of the register inside,
instruction shows in the memory Compare Qn and Qn+1 and perform the following
4. M [AR].
 The individual cells is assigned a letter withLOOP
Branch_if_[R2]>0 a subscript number,
 The numbering of cells from right to left can be marked on top of the box,
is a conditional branch instruction that causes a branch to location LOOP if the contents of
It can achieve through a read or write operation, first, the memory register (M) should be selected
by a particular address.
01 –> AC=AC+BR
 16 bit register is partitioned into 2 parts , bits 1 to 8 are assigned the letter L(for low)
register R2 are greater than zero. Finally the Store instruction is fetched and executed. It moves
and bits 9 to 16 are assigned the letter H(for high)
the final result from R3 into memory location SUM. The figure shows the memory transfer representation. It demonstrates that the memory unit can 10 –> AC=AC+BR’+1
transfer the data from the memory address register and memory buffer register to implement read
A e) Register A
10 and write operations in the memory transfer. 00 –> No arithmetic operation
f) Showing individual
11-> No arithmetic operation
A8 A7 A6 A5 A4 A3 A2 A1
Cells
12 1
MAR g) Numbering of Cells 5. ASHR- Arithmetic Shift right AC,QR
16 9 8 1 6. Decrement SC by 1
PC (L) PC (H) h) Portions of Register
Registers can be specified in a register transfer language with a declaration statement. For
example: Registers in the above figure can be defined with declaration statement such as
The final product will be store in AC, QR
DECLARE REGISTER A(8), MBR(12), PC(16)
DECLARE SUBREGISTER PC(L) = PC(1-8), PC(H) = PC(9-16).
Information transfer from one register to another is described by a replacement operator:
A ← B. This statement denotes a transfer of the content of register B into register A and this
transfer happens in one clock cycle. After the operation, the content of the B (source) does not