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Computer_Organization_Answers

The document discusses various topics in computer organization and architecture, including the five generations of computers, the role of processor clock and clock rate, and the MESI cache coherence protocol. It also covers virtual memory, data transfer rates using DMA, RAID architectures, and arithmetic shift operations in registers. Additionally, it describes hardware methods for establishing priority in processing tasks.

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2 views

Computer_Organization_Answers

The document discusses various topics in computer organization and architecture, including the five generations of computers, the role of processor clock and clock rate, and the MESI cache coherence protocol. It also covers virtual memory, data transfer rates using DMA, RAID architectures, and arithmetic shift operations in registers. Additionally, it describes hardware methods for establishing priority in processing tasks.

Uploaded by

ankitaakki18
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Computer Organization & Architecture - Answer Sheet

Question:

Q1 a) Discuss the generations of computers...

Answer:

Answer: There are five generations of computers: First (vacuum tubes), Second (transistors), Third

(integrated circuits), Fourth (microprocessors), and Fifth (AI-based systems). Each generation

improved speed, size, and processing power.

Question:

Q1 b) What is the role of Processor clock, clock rate in performance?

Answer:

Answer: The processor clock synchronizes all components. Clock rate determines how many

operations a CPU can perform per second; higher clock rate means better performance.

Question:

Q1 c) What is MESI in cache block?

Answer:

Answer: MESI stands for Modified, Exclusive, Shared, and Invalid - a cache coherence protocol

used to maintain consistency in multiprocessor systems.

Question:

Q1 d) Explain the 2D Memory with suitable block diagram.

Answer:

Answer: 2D memory organizes memory in a row-column matrix format. A block diagram shows rows

and columns intersecting at memory cells.

Question:

Q1 e) Explain AND and BSA instructions.


Answer:

Answer: AND is a logical instruction performing bitwise AND. BSA (Branch and Save Address) is

used to call subroutines and save return address.

Question:

Q2 a) Draw a block diagram for R1 - R1+R2 and R1 - R1+1 using 4-bit adder...

Answer:

Answer: The block diagram uses a 4-bit parallel adder connected to a 4-bit counter R1. R2 is input

to the adder. A control line selects addition or increment operation.

Question:

Q2 b) Explain virtual memory and its role.

Answer:

Answer: Virtual memory allows large programs to run by using disk space as extension of RAM. It

offers memory protection and isolation of processes.

Question:

Q3 a) Calculate data transfer rate using DMA.

Answer:

Answer: With 2 MHz processor and 0.5% DMA usage: 0.005 - 2,000,000 = 10,000 characters/sec =

80,000 bits/sec.

Question:

Q3 c) Flowchart for instruction cycle.

Answer:

Answer: The instruction cycle includes Fetch - Decode - Execute - Store. Each step transitions to

the next via control signals.

Question:
Q4 a) Time for transfer from L2 to L1 cache.

Answer:

Answer: L2 hit and L1 miss leads to a block transfer taking 20 ns (L2 access) + 4-2 ns (block of 4

words) = 28 ns.

Question:

Q4 b) Discuss all RAID architectures.

Answer:

Answer: RAID levels include RAID 0 (striping), 1 (mirroring), 5 (parity), 6 (double parity), and 10

(combination). Each offers trade-offs in performance, reliability, and cost.

Question:

Q5 a) 8-bit register arithmetic shift operations.

Answer:

Answer: Right shift of 10011100 yields 11001110. Left shift yields 00111000. No overflow in right

shift; left shift may overflow if MSB changes.

Question:

Q5 c) Hardware methods to establish priority.

Answer:

Answer: Two methods are Daisy Chaining (serial priority resolution) and Parallel Priority Encoder

(hardware logic to detect highest priority line).

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