BITS Pilani

Pilani Campus

EEE/CS/ECE/INSTR F241 Microprocessor Programming & Interfacing

Lect-1
Prof. Meetha.V.Shenoy
Team of Instructors

Prof. Meetha V Shenoy (IC)

Prof. Vinay Chamola

MPI@Meetha V Shenoy
Tutorial Instructors

• Prof. GSS Chalapathi,

• Prof. Satyendra Kumar Mourya,
• Prof. Neeraj Mishra,
• Prof. Tejasvi Alladi,
• Mr.Naga Siva Sai Reddy,
• Mr.Balamurugan,
• Mr.Anubhav Elhence,
• Ms. Jyoti Pandey

MPI@Meetha V Shenoy
General Purpose Computers/ Embedded Systems &
Microprocessors

In today’s world, we have Embedded Systems all around us. Almost all modern electronic systems
can be considered as Embedded Systems.

MPI@Meetha V Shenoy
Microprocessor Vs Microcontroller

Instruction
Memory I/O Instruction
Memory I/O

Microprocessor Microprocessor
Data Memory
I/O Data Memory
I/O

Timers Timers

MPI@Meetha V Shenoy
Von-Neumann/ Princeton Memory architecture

MPI@Meetha V Shenoy
Harvard Memory architecture

MPI@Meetha V Shenoy
Registers
• Assembly level Instruction

ADD R1, R2, R3

Registers can be 8-bit/16-bit/32-bit/64-bit etc.

MPI@Meetha V Shenoy
• What do you understand by the term
8-bit, 16-bit , 32 or 64 bit processor?

Size of the ALU

MPI@Meetha V Shenoy
Microcontroller Vs SOC

BCM2385,
Raspberry Pi 3

MPI@Meetha V Shenoy
OMAP 4430- SOC

MPI@Meetha V Shenoy
 Complex Instruction Set Computer
CISC Vs RISC Reduced Instruction Set Computer

c=a x b

CISC
• MUL C, A, B
RISC
• LOAD R1,A
• LOAD R2, B
• MUL R1, R1,R2
• STORE R1, C

MPI@Meetha V Shenoy
CISC Vs RISC

MPI@Meetha V Shenoy
Module 1

MPI@Meetha V Shenoy
BITS Pilani, Pilani Campus
Microprocessor

Instruction
Memory I/O

Microprocessor

Data Memory
I/O

Timing, RTC

MPI@Meetha V Shenoy
Module 2

MPI@Meetha V Shenoy
BITS Pilani, Pilani Campus
Motherboard

MPI@Meetha V Shenoy
Module 3

MPI@Meetha V Shenoy
 Evaluation Scheme

Lab (regular): 2 marks for each lab. 1 mark for attendance, 1 for right answers, Best 7 will be
taken of 9 labs
Tutorial exams: Best 8 will be taken of 10 tuts

MPI@Meetha V Shenoy
Thank You

MPI@Meetha V Shenoy
 BITS Pilani
Pilani Campus

EEE/CS/ECE/INSTR F241 Microprocessor Programming & Interfacing

Lect-2
Prof. Meetha.V.Shenoy
Module 1

MPI@Meetha V Shenoy
BITS Pilani, Pilani Campus
Module 2

MPI@Meetha V Shenoy
BITS Pilani, Pilani Campus
ADC

Analog
to
Digital
Converter

MPI@Meetha V Shenoy
DAC

Digital
to
Analog
Converter

MPI@Meetha V Shenoy
Module 3

MPI@Meetha V Shenoy
Motherboard

MPI@Meetha V Shenoy
Module 3

MPI@Meetha V Shenoy
 Evaluation Scheme

Lab (regular): 2 marks for each lab. 1 mark for attendance, 1 for right answers, Best 7 will be
taken of 9 labs
Tutorial exams: Best 8 will be taken of 10 tuts

MPI@Meetha V Shenoy
 Complex Instruction Set Computer
CISC Vs RISC Reduced Instruction Set Computer

c=a x b

CISC
• MUL C, A, B
RISC
• LOAD R1,A
• LOAD R2, B
• MUL R1, R1,R2
• STORE R1, C

MPI@Meetha V Shenoy
CISC Vs RISC

MPI@Meetha V Shenoy
• Assembly Level Instruction- ADD R1,R2,R3

• MACHINE CODE- 01011110……..

MPI@Meetha V Shenoy
SIZE OF MACHINE CODE
• ADD R1,R2, R3
• ADD A,B,C

• Consider there are 16 registers in the processor and

the address/data bus size is 32 bits

• RISC processors will have the same size machine

codes.

MPI@Meetha V Shenoy
Handling of Instruction by processor
• Instruction Fetch (IF)- Machine code is fetched from Instruction memory

• Instruction Decode (ID)- Identify the type of operation (opcode) and the
operands from the fetched machine code
ADD R1,R2,R3

• Execute (EX)- The operation specified by the instruction is performed. ALU is

utilized.

• Memory Access (MEM): Access memory if the instruction involves reading

from or writing to memory

• Write back (WB): The results of the instruction are written back to a
destination register or memory.

MPI@Meetha V Shenoy
Single Cycle Implementation

LDR R0, A
LDR R0,[R1]
LDR R0, [R1, R2]
STR R0, [R1,R2]
ADD R1,R1,R2

MPI@Meetha V Shenoy
 Multicycle Implementation

LDR R0, [R1]

LDR R0, [R1, R2]
STR R0, [R1,R2]
ADD R1,R1,R2

MPI@Meetha V Shenoy
Pipelined Implementation

MPI@Meetha V Shenoy
SCALAR PIPELINED ARCHITECTURES

MPI@Meetha V Shenoy
Thank You

MPI@Meetha V Shenoy
 Microprocessors programming
and Interfacing
CS/EEE/ECE/INSTR F241- Lect-3
Prof. Meetha V Shenoy, Prof. Vinay Chamola

BITS Pilani Introduction to x86 processors

Pilani Campus

BITS Pilani, Pilani Campus

CISC Vs RISC
c=a x b

CISC
• MUL C, A, B
RISC
• LOAD R1,A
• LOAD R2, B
• MUL R1, R1,R2
• STORE R1, C

BITS Pilani, Pilani Campus

SCALAR PIPELINED ARCHITECTURES

ADD R1,R2,R3

BITS Pilani, Pilani Campus

RISC VS CISC

RISC CISC
(Optimize) (Optimize)

BITS Pilani, Pilani Campus

Characteristics of X86 family

CISC
Complex Instruction Decoder

BITS Pilani, Pilani Campus

16 Bit Processors

1,048,576/(1024*1024)

BITS Pilani, Pilani Campus

8086 Buses

16-bit processor

BITS Pilani, Pilani Campus

Address bus/ address space

BITS Pilani, Pilani Campus

16 Bit Processors

BITS Pilani, Pilani Campus

32-bit Processors

Earlier version had co-

processor to support
floating pt operations

BITS Pilani, Pilani Campus

Block Diagram of 8086

BIU- Fetches instruction & Data

EU- Executes Instruction

BITS Pilani, Pilani Campus

Block Diagram of 8086

BITS Pilani, Pilani Campus

Variation of 8086-8088

BITS Pilani, Pilani Campus

Block Diagram of 8086

The instruction
pointer (IP) in an
8086 microprocessor
is a 16-bit register
that points to the
address of the next
instruction to be
fetched

BITS Pilani, Pilani Campus

Memory data size

BITS Pilani, Pilani Campus

Buses

BITS Pilani, Pilani Campus

8086 Buses

20 bit memory address

16 bit registers

BITS Pilani, Pilani Campus

Segment Registers

• Memory Organization
– Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1M of
addressable memory
– Addresses are expressed as 5 hex digits from 00000 – FFFFF
– Problem: But 20 bit addresses are TOO BIG to fit in 16 bit registers!

– Solution: Memory Segment

• Block of 64K (65,536) consecutive memory bytes
• Within a segment, a particular memory location is specified with an offset
• An offset also ranges from 0000 to FFFF

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
Segments in 8086

• The code segment is a section of memory that holds the

code (programs and procedures) used by the
microprocessor. The code segment (CS) register defines the
starting address of the section of memory holding code.

BITS Pilani, Pilani Campus

 Intel
Memory address generation

• The BIU has a dedicated adder for determining physical memory addresses

Offset Value (16 bits) IP

Segment Register (16 bits) 0000

CS

Adder

Physical Address (20 Bits)

BITS Pilani, Pilani Campus

Example (Accessing a location)

BITS Pilani, Pilani Campus

Examples

BITS Pilani, Pilani Campus

 Microprocessors programming
and Interfacing
CS/EEE/ECE/INSTR F241
Prof.Meetha V Shenoy/Prof. Vinay Chamola

BITS Pilani
Pilani Campus BIU & EU

BITS Pilani, Pilani Campus

8086 Buses

16-bit processor

BITS Pilani, Pilani Campus

Block Diagram of 8086

BIU- Fetches instruction & Data

EU- Executes Instruction

BITS Pilani, Pilani Campus

8086 Buses

20 bit memory address

16 bit registers

BITS Pilani, Pilani Campus

Segment Registers

• Memory Organization
– Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1M of
addressable memory
– Addresses are expressed as 5 hex digits from 00000 – FFFFF
– Problem: But 20 bit addresses are TOO BIG to fit in 16 bit registers!

– Solution: Memory Segment

• Block of 64K (65,536) consecutive memory bytes
• Within a segment, a particular memory location is specified with an offset
• An offset also ranges from 0000 to FFFF

BITS Pilani, Pilani Campus

Block Diagram of 8086

The instruction
pointer (IP) in an
8086 microprocessor
is a 16-bit register
that points to the
address of the next
instruction to be
fetched

BITS Pilani, Pilani Campus

 Intel
Memory address generation

• The BIU has a dedicated adder for determining physical memory addresses

Offset Value (16 bits) IP

Segment Register (16 bits) 0000

CS

Adder

Physical Address (20 Bits)

BITS Pilani, Pilani Campus

Example (Accessing a location)

BITS Pilani, Pilani Campus

Segments in 8086
• The code segment is a section of memory that holds the
code (programs and procedures) used by the
microprocessor. The code segment (CS) register defines the
starting address of the section of memory holding code.

• The data segment is a section of memory that contains most

data used by a program.

• The extra segment is an additional data segment that is used

by some of the string instructions to hold destination data.

• The stack segment defines the area of memory used for the
stack.

BITS Pilani, Pilani Campus

Segmentation

BITS Pilani, Pilani Campus

Block Diagram of 8086

BITS Pilani, Pilani Campus

Examples

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
8086 Registers
Block Diagram of 8086
8086 Microprocessor
Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O devices,
writes data to memory and I/ O
devices.
16
8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Dedicated Adder to generate

20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Segment Registers >> 17

8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Facilitates
Segment Relocation
Registers

8086’s 1-megabyte The 8086 can directly Programs obtain access

memory is divided address four segments to code and data in the
into segments of up (256 K bytes within the 1 segments by changing
to 64K bytes each. M byte of memory) at a the segment register
particular time. content to point to the
desired segments.

18
8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment
Registers Code Segment Register

16-bit

CS contains the base or start of the current code segment;

IP contains the distance or offset from this address to the
next instruction byte to be fetched.

BIU computes the 20-bit physical address by logically

shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.

That is, all instructions of a program are relative to the

contents of the CS register multiplied by 16 and then offset
is added provided by the IP.

19
8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Data Segment Register

Registers
16-bit

Points to the current data segment; operands for most

instructions are fetched from this segment.

The 16-bit contents of the Source Index (SI) or

Destination Index (DI) or a 16-bit displacement are used
as offset for computing the 20-bit physical address.

20
8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Stack Segment Register

Registers
16-bit

Points to the current stack.

The 20-bit physical stack address is calculated from the

Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions

21
8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Extra Segment Register

Registers
16-bit

Points to the extra segment in which data (in excess of

64K pointed to by the DS) is stored.

String instructions use the ES and DI to determine the 20-

bit physical address for the destination.

22
8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Instruction Pointer

Registers
16-bit

Always points to the next instruction to be executed within

the currently executing code segment.

So, this register contains the 16-bit offset address pointing

to the next instruction code within the 64Kb of the code
segment area.

Its content is automatically incremented as the execution

of the next instruction takes place.

23
8086 Microprocessor
Architecture Execution Unit (EU)

EU decodes and
executes instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and

Index registers (Source

Index, Destination Index)
each of 16-bits

24
Default segment-offset combinations
8086 Microprocessor
Architecture Execution Unit (EU)

EU decodes and
executes instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 26
DX can be used as DH and DL
8086 Microprocessor
Architecture Execution Unit (EU)

EU Accumulator Register (AX)

Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.

AL in this case contains the low order byte of the word,

and AH contains the high-order byte.

The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

27
8086 Microprocessor
Architecture Execution Unit (EU)

EU Base Register (BX)

Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.

This is the only general purpose register whose contents

can be used for addressing the 8086 memory.

All memory references utilizing this register content for

addressing use DS as the default segment register.

28
8086 Microprocessor
Architecture Execution Unit (EU)

EU Counter Register (CX)

Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

When combined, CL register contains the low order byte of

the word, and CH contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.

29
8086 Microprocessor
Architecture Execution Unit (EU)

EU Data Register (DX)

Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.

When combined, DL register contains the low order byte of

the word, and DH contains the high-order byte.

30
8086 Microprocessor
Architecture Execution Unit (EU)

EU
Registers

Stack Pointer (SP) and Base Pointer (BP)

SP and BP are used to access data in the stack segment.

31
8086 Microprocessor
Architecture Execution Unit (EU)

EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

32
8086 Microprocessor
Architecture Execution Unit (EU)

EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

33
 Microprocessors programming
and Interfacing
CS/EEE/ECE/INSTR F241
Prof.Meetha V Shenoy/Prof. Vinay Chamola

BITS Pilani
Pilani Campus

BITS Pilani, Pilani Campus

Block Diagram of 8086

BITS Pilani, Pilani Campus

8086 Microprocessor
Architecture Execution Unit (EU)
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Trap Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 3
 P1: 44+52

2CH , 34H

1 1 1 1
0 0 1 0 1 1 0 0 Auxiliary Carry – 1
0 0 1 1 0 1 0 0
0 1 1 0 0 0 0 0 No Carry
Result Not Zero
Positive Number
No overflow
Parity - Even
8086 registers
categorized
into 4 groups

7
8086 Internal registers

AX, BX, CX and DX are two

bytes wide and each byte can
be accessed separately

These registers are used as

memory pointers.

Flags

Segment registers are used

as base address for a segment
in the 1 M byte of memory
Buses
MOV instruction

Addressing modes in the 8086 microprocessor define how

the microprocessor accesses data stored in memory or in
registers.

They determine the location of operands (data) to be used in

an instruction.

BITS Pilani, Pilani Campus

Addressing Modes

• Register Addressing

• Both operands (source and destination) are registers.

eg: MOV AX, BX

BITS Pilani, Pilani Campus

Addressing Modes
• Immediate Addressing

• The operand is specified directly in the instruction as a constant

value.

eg: MOV AX, 1420H

MOV AL,’A’

BITS Pilani, Pilani Campus

Addressing Modes
• Direct Addressing

• The address of the operand is given in the instruction.

eg: MOV AX, [2340H ]

MOV CS, [2340H ]
MOV CH,DS:[1000H]

BITS Pilani, Pilani Campus

 Addressing Modes

• Register Indirect Addressing

• The address of the operand is contained in a register.

eg: MOV AX, [BX]

MOV [AX], BX

BITS Pilani, Pilani Campus

Default segment-offset combinations

BITS Pilani, Pilani Campus

Addressing Modes
• Base Plus Index Addressing

eg: MOV AX, [BX+SI]

MOV CX,[BX+DI]
MOV CH,[BP+SI]
MOV [BP+DI],AH

BITS Pilani, Pilani Campus

Addressing Modes

• Register relative addressing

eg: MOV AX,[DI+100H]

MOV DI,[AX+10H]

BITS Pilani, Pilani Campus

 Addressing Modes

• Base relative plus indexed addressing

eg: MOV AX,[BX+SI+100H]

BITS Pilani, Pilani Campus

 Microprocessors and Interfacing

CS F241/EEE F241/INSTR F241/ECEF241

Prof. Meetha.V.Shenoy/Prof. Vinay Chamola

BITS Pilani
Pilani Campus
8086 Microprocessor
Architecture

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
2
ADDRESSING MODES
&
Instruction set
Types of Instructions

BITS Pilani, Pilani Campus

The MOV instruction

BITS Pilani, Pilani Campus

MOV instruction

Addressing modes in the 8086 microprocessor define how the microprocessor

accesses data stored in memory or in registers.

They determine the location of operands (data) to be used in an instruction.

BITS Pilani, Pilani Campus

Addressing Modes

• Register Addressing

• Both operands (source and destination)

are registers.

eg: MOV AX, BX

BITS Pilani, Pilani Campus

Addressing Modes
• Immediate Addressing

• The operand is specified directly in the

instruction as a constant value.

eg: MOV AX, 1420H

MOV AL,’A’

BITS Pilani, Pilani Campus

Addressing Modes
• Direct Addressing

• The address of the operand is given in the

instruction.

eg: MOV AX, [2340H ]

MOV CS, [2340H ]
MOV CH,DS:[1000H]

BITS Pilani, Pilani Campus

Addressing Modes
• Register Indirect Addressing

• The address of the operand is contained in a

register.

eg: MOV AX, [BX]

MOV [AX], BX

BITS Pilani, Pilani Campus

Default segment-offset combinations

BITS Pilani, Pilani Campus

 Addressing Modes
Base Plus Index Addressing

eg: MOV AX, [BX+SI]

MOV CX,[BX+DI]
MOV CH,[BP+SI]
MOV [BP+DI],AH

BITS Pilani, Pilani Campus

Addressing Modes

• Register relative addressing

eg: MOV AX,[DI+100H]

MOV DI,[AX+10H]

BITS Pilani, Pilani Campus

 Addressing Modes

• Base relative plus indexed

addressing

eg: MOV AX,[BX+SI+100H]

BITS Pilani, Pilani Campus

Addressing modes

BITS Pilani, Pilani Campus

The MOV instruction

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
32-bit Processors

BITS Pilani, Pilani Campus

80386

BITS Pilani, Pilani Campus

32 bit addressing mode

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
 Evaluate machine code for both cases-
Machine running in 16 bit mode, 32 bit mode

BITS Pilani, Pilani Campus

80386 in 16 bit mode & 32 bit mode of
operation

BITS Pilani, Pilani Campus

 Microprocessors programming and Interfacing

CS/EEE/ECE/INSTR F241

Lecture -9
BITS Pilani
Pilani Campus
ADDRESSING MODES
&
Instruction set
Addressing modes
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
MOV AX, [BX+ 34H]

BITS Pilani, Pilani Campus

MOV [SI+600H], BH

BITS Pilani, Pilani Campus

MOV [SI+600h], BH

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
Base Relative plus indexed addressing

MOV [BX+SI+600H], BH

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
 Machine running in 16 bit mode

SS
00 – x1
01 – x2
10 – x4
11 – x8

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
 Caution: From online source:
For details and accurate template see barry brey book: Appendix B

BITS Pilani, Pilani Campus

 Microprocessors programming and Interfacing

CS/EEE/ECE/INSTR F241

Lecture -10
BITS Pilani
Pilani Campus
ADDRESSING MODES
&
Instruction set
Addressing modes
 Caution: From online source:
For details and accurate template see barry brey book: Appendix B

BITS Pilani, Pilani Campus

Special cases of MOV (Template is different)

1. MOV immediate to register

2. MOV Immediate to Memory
3. MOV direct memory to/from accumulator
4. MOV reg/mem to segment registers

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
Special cases of MOV (Template is different)

1. MOV immediate to register

2. MOV Immediate to Memory
3. MOV direct memory to/from accumulator
4. MOV reg/mem to segment registers

BITS Pilani, Pilani Campus

MOV immediate to memory

1100011 1 10 000 011 08H 10H 30H 12H

MOV [BP+DI+1008H], 1230H Machine code in hex: C7 83 08 10 30 12H

BITS Pilani, Pilani Campus

Special cases of MOV (Template is different)

1. MOV immediate to register

2. MOV Immediate to Memory
3. MOV direct memory to/from accumulator
4. MOV reg/mem to segment registers

BITS Pilani, Pilani Campus

MOV direct to/ from accumulator

Only applicable to direct addressing with accumulator (AX, AL)

EG.
MOV [1008H], AL
MOV [1008H], AX

MOV [1008H], AH - THIS MACHINE CODE TEMPLATE NOT APPLICABLE (as AH used)
MOV [BX], AX - THIS MACHINE CODE TEMPLATE NOT APPLICABLE (as not direct addressing)

BITS Pilani, Pilani Campus

MOV direct to/ from accumulator

MOV [1240H], AL
101000 00 40H 12H

A0 40 12 H

MOV AX, [1240H]

101000 11 40H 12H

A3 40 12 H

BITS Pilani, Pilani Campus

MOV reg/mem to segment registers

BITS Pilani, Pilani Campus

Special cases of MOV (Template is different)

1. MOV immediate to register

2. MOV Immediate to Memory
3. MOV direct memory to/from accumulator
4. MOV reg/mem to segment registers

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
Microsoft Macro Assembler
(MASM) Program Models

BITS Pilani, Pilani Campus

Microsoft Macro Assembler
(MASM) Program Models

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
 Microprocessors programming and Interfacing

CS/EEE/ECE/INSTR F241

Lecture -11
BITS Pilani
Pilani Campus
Addressing modes

BITS Pilani, Pilani Campus

ADDRESSING MODES
&
Instruction set
Microsoft Macro Assembler
(MASM) Program Models

BITS Pilani, Pilani Campus

Microsoft Macro Assembler
(MASM) Program Models

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
MASM Assembler Directives

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
 Microprocessors programming and Interfacing

CS/EEE/ECE/INSTR F241

Lecture -12
BITS Pilani
Pilani Campus
EXAMPLE

MOV SI, DAT3

COUNT EQU 32H MOV AL, DAT1+1
VAL1 EQU 0030H MOV BX, WORD PTR DAT1+4
DAT1 DB 45H,67H,100, 'A' ADD BX,20H
WRD DW 10H, 3500H, 0910H MOV AL, [BX]
DAT2 DD 0902H LEA BX,DAT4
VAL2 EQU 32H mov al,[bx]
DAT3 DW 2 DUP(0) mov bx, VAL1
DAT4 DB 56H mov al,[bx]
RES DB 10 DUP(?) mov bx,offset DAT4
SWRD DD 01020304H mov al,[bx]
mov al,DAT4

BITS Pilani, Pilani Campus

EXAMPLE
COUNT EQU 32H
VAL1 EQU 0030H
DAT1 DB 45H,67H,100, 'A'
WRD DW 10H, 3500H, 0910H
DAT2 DD 0902H
VAL2 EQU 32H
DAT3 DW 2 DUP(0)
DAT4 DB 56H
RES DB 10 DUP(?)
SWRD DD 01020304H

MOV SI, DAT3

MOV AL, DAT1+1
MOV BX, WORD PTR DAT1+4
ADD BX,20H
MOV AL, [BX]
LEA bx,DAT4
mov al,[bx]
mov bx, VAL1
mov al,[bx]
mov bx,offset DAT4
mov al,[bx]
mov al,DAT4

BITS Pilani, Pilani Campus

INC/DEC Instructions

Doesn’t support INC/DEC with direct memory addressing

with an immediate address

Segment register cannot be a destination

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
INC -Examples

BITS Pilani, Pilani Campus

DEC -Examples

BITS Pilani, Pilani Campus

CONDITIONAL JUMP INSTRUCTIONS

BITS Pilani, Pilani Campus

MOV 5 bytes of data from the location labelled DATA1
to locations starting from DS:300H

.model tiny
.data
count equ 5
DATA1 DB 11h,22h,33h,44h,55h
DATA2 DB 5 DUP (?) Not required
.code
.startup
LEA SI, DATA1
MOV DI,300h
MOV CL, count
l1:MOV AL,[SI]
MOV [DI], AL
INC SI
INC DI
DEC CL
JNZ l1
.exit
end
BITS Pilani, Pilani Campus
CONDITIONAL JUMPS in 8086

The range of the jump is within +127 bytes

and -128 bytes from the location following
the conditional jump.

JZ Label

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
.model tiny
0111 0101 F6
.data
count equ 5
DATA1 DB 11h,22h,33h,44h,55h
DATA2 DB 5 DUP (?)
.code
.startup
LEA SI, DATA1
MOV DI,300h
MOV CL, count
l1:MOV AL,[SI]
MOV [DI], AL
INC SI
INC DI
DEC CL 0111 0101 F6
JNZ l1
.exit
end
BITS Pilani, Pilani Campus
 Microprocessors programming and Interfacing

CS/EEE/ECE/INSTR F241

Lecture -13
BITS Pilani
Pilani Campus
INC/DEC Instructions

Doesn’t support INC/DEC with direct memory addressing

with an immediate address

Segment register cannot be a destination

BITS Pilani, Pilani Campus

CONDITIONAL JUMP INSTRUCTIONS

BITS Pilani, Pilani Campus

CONDITIONAL JUMPS in 8086

The range of the jump is within +127 bytes

and -128 bytes from the location following
the conditional jump.

JZ Label

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
Arithmetic Instruction – ADD & SUB

(Status)
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
Add with Carry (ADC)

BITS Pilani, Pilani Campus

CLC instruction clears
carry flag

STC instruction sets

carry flag

BITS Pilani, Pilani Campus

Add 2, 6 byte nos stored from
Location 20000H (Source 1) &
21000H (Source 2) and store the
result starting from 21000H.
Store the carry generated if any in
21006H

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
ZF=0
CF=1
AF=0
SF=1
OF=0

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
CONDITIONAL JUMP INSTRUCTIONS

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
 Microprocessors programming and Interfacing

CS/EEE/ECE/INSTR F241

Lecture -14
BITS Pilani
Pilani Campus
BITS Pilani, Pilani Campus
CONDITIONAL JUMP INSTRUCTIONS

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
AND mem, mem not allowed.

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
REP Prefix

The REP prefix causes CX to decrement by 1

each time the string instruction executes.

After CX decrements, the string instruction

repeats.

If CX reaches a value of 0, the instruction

terminates and the program continues with the
next sequential instruction

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
 Microprocessors programming and Interfacing

CS/EEE/ECE/INSTR F241

Lecture -15- String Instructions

BITS Pilani
BITS Pilani
Pilani
Pilani Campus
Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
REP Prefix

The REP prefix causes CX to decrement by 1

each time the string instruction executes.

After CX decrements, the string instruction

repeats.

If CX reaches a value of 0, the instruction

terminates and the program continues with the
next sequential instruction

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
DAT1

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
PREFIX
• REPNE (repeat while not equal) prefix- causes the SCASB
instruction to repeat until
• either the CX register reaches 0, or
• until an equal condition exists
as the outcome of the SCASB instruction’s comparison.

• REPNE/REPNZ - Continues scanning while values are

different (ZF = 0).
• REPE/REPZ (repeat while equal)- Continues scanning while
values are equal (ZF = 1)

BITS Pilani, Pilani Campus

PREFIX

Instruction Condition for Condition for Stop

Repeat
REPE / REPZ ZF = 1 and CX > 0 When CX = 0 or ZF = 0

REPNE / REPNZ ZF = 0 and CX > 0 When CX = 0 or ZF = 1

BITS Pilani, Pilani Campus

Instruction Condition Condition for
for Repeat Stop

REPE / ZF = 1 and When CX = 0 or

REPZ CX > 0 ZF = 0

REPNE / ZF = 0 and When CX = 0 or

REPNZ CX > 0 ZF = 1
 8086-80486 string, rotate Instructions

BITS Pilani
Pilani Campus Lecture -16
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
PREFIX

Instruction Condition for Condition for Stop

Repeat
REPE / REPZ ZF = 1 and CX > 0 When CX = 0 or ZF = 0

REPNE / REPNZ ZF = 0 and CX > 0 When CX = 0 or ZF = 1

BITS Pilani, Pilani Campus

 .model tiny
.data
DAT1 DB 80 dup (?)
ADD1 DW ?
.code
Instruction Condition Condition for .startup
for Repeat Stop MOV DI, OFFSET DAT1
MOV AL, 0DH
REPE / ZF = 1 and When CX = 0 or MOV CX,81
REPZ CX > 0 ZF = 0 CLD
REPNE SCASB
REPNE / ZF = 0 and When CX = 0 or CMP CX,0
REPNZ CX > 0 ZF = 1 JE L1
DEC DI
MOV ADD1, DI
L1:
.exit
end
BITS Pilani, Pilani Campus
Exit when either CX is ‘0 ‘ or when the two memory
locations are unequal
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
OF = CF ⊕ New MSB
OF = 1 (indicating a sign change)

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
Use CL to store count if count is > 1 for 8086,80286

For 80386,80486 count can be given directly

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
Used to swap nibbles

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
 8086-80486 shift/jmp Instructions

BITS Pilani
Pilani Campus Lecture -17
OF???

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
OF???

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
 BITS Pilani
Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
 8086-80486 Instructions

BITS Pilani
Pilani Campus Lecture -18
 BITS Pilani
Pilani Campus
BITS Pilani, Pilani Campus
JMP 2856H
JMP WORD PTR [BX], JMP BX

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
•Segment (Base Address) – Upper 16 bits of the double word
•Offset (Within the Segment) – Lower 16 bits of the double word

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
MUL SOURCE

•8-bit unsigned: 0 to 255 (00H to FFH)

•16-bit unsigned: 0 to 65,535 (0000H to FFFFH)
•32-bit unsigned: 0 to 4,294,967,295 (00000000H to FFFFFFFFH)

BITS Pilani, Pilani Campus

 8086-80486 Instructions

BITS Pilani
Pilani Campus Lecture -19
 BITS Pilani
Pilani Campus
MUL SOURCE

•8-bit unsigned: 0 to 255 (00H to FFH)

•16-bit unsigned: 0 to 65,535 (0000H to FFFFH)
•32-bit unsigned: 0 to 4,294,967,295 (00000000H to FFFFFFFFH)

BITS Pilani, Pilani Campus

•8-bit signed: -128 to 127 (80H to 7FH)
•16-bit signed: -32,768 to 32,767 (8000H to 7FFFH)
•32-bit signed: -2,147,483,648 to 2,147,483,647 (80000000H to 7FFFFFFFH)

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
Implied Addressing mode

Works on AL/AX

BITS Pilani, Pilani Campus

Example
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BL= -3, AX=16
AL=-5 (QUOTIENT)
AH=1(REMINDER)

BITS Pilani, Pilani Campus

BL= 3, AX=-16
AL=-5 (QUOTIENT)
AH=-1(REMINDER)

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
Divide 5/255

Quotient =0
Reminder =5

BITS Pilani, Pilani Campus

 Stack Operations
BITS Pilani
Pilani Campus
BITS Pilani, Pilani Campus
Push immediate is also possible.

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
 8086-80486 Stack instructions, Subroutines,
Macros

Lect-20
BITS Pilani
Pilani Campus
BITS Pilani, Pilani Campus
Push immediate is also possible.

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
8086-80486 Subroutines & Macros

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
Subroutines
Advantage: reduces the code length for repetitive usage of a group of instructions
– Machine code generated only once
Disadvantage: need stack and overhead time
– NOT SUITABLE if repetitive instructions are short

Solution: use MACROS

BITS Pilani, Pilani Campus

MACROS

BITS Pilani, Pilani Campus

 8086-80486 Subroutines- passing parameters

Lect-21

BITS Pilani
Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
Passing Parameters to Procedures

Parameters are data values or addresses passed back and forth

between the mainline program and the procedure.

Four ways to pass parameters

 In Registers
 In Dedicated memory locations accessed by name
 With pointers passed in registers
 With stack

BITS Pilani, Pilani Campus

Conversion example: Conversion example:
BCD – 16 BCD – 116
Bin/hex -10h Bin/hex -74h
(01 * 0ah ) + 6

BITS Pilani, Pilani Campus

BCD to Binary conversion
(using parameter (data) in register)

-------------
-------------
MOV AL, BCDINPUT
The BCD number is copied
CALL BCD_BIN
from memory to the AL and
MOV BIN_VAL, AL then passed to the
----------- procedure in the AL
------------------ register.

BITS Pilani, Pilani Campus

Parameter stored in register
EX: BCD to Binary Conversion
BCD_BIN PROC NEAR
PUSHF
PUSH BX
PUSH CX Not pushing the AX register on stack as
MOV BL , AL we use it to pass a value to the
procedure and expect the procedure to
AND BL , 0FH pass a different value back to the
AND AL , 0F0H program
MOV CL , 04
ROR AL, CL
MOV BH , 0AH
MUL BH
ADD AL, BL Disadvantage: no of registers limit
the no of parameters that can be
POP CX passed to procedures. Cant pass an
POP BX array of 100 elements using
POPF registers.
RET
BCD_BIN ENDP

BITS Pilani, Pilani Campus

Passing parameters stored in general memory

In the preceding example, why didn’t we simply access the BCD_INPUT and
BIN_VALUE by name from the procedure?
BCD_BIN PROC NEAR
PUSHF
PUSH AX
PUSH BX
PUSH CX
MOV AL, BCD_INPUT
MOV BL , AL
AND BL , 0FH
AND AL , 0F0H
MOV CL , 04
ROR AL, CL
MOV BH , 0AH
MUL BH
ADD AL, BL
MOV BIN_VALUE, AL
POP CX
POP BX
POP AX
POPF
RET
BCD_BIN ENDP
BITS Pilani, Pilani Campus
Procedure will always look for the named memory
location BCD_INPUT to get its data and will always
put the result in BIN_VALUE.
Or, we can use this procedure to convert the BCD
no stored somewhere else in memory.

BITS Pilani, Pilani Campus

Passing parameters using pointers
EX: BCD to Binary Conversion
BCD_BIN PROC NEAR
PUSHF
PUSH AX More versatile than using named memory
PUSH BX
location as the procedure pointers can
PUSH CX
MOV AL, [SI]
point to data anywhere in memory. Set up
MOV BL , AL SI and DI acting as pointers.
AND BL , 0FH
AND AL , 0F0H
MOV CL , 04
ROR AL, CL
MOV BH , 0AH
MUL BH
ADD AL, BL MOV SI, OFFSET BCD_INPUT
MOV [DI], AL MOV DI, OFFSET BIN_VALUE
POP CX CALL BCD_BIN
POP BX NOP
POP AX
POPF
RET
BCD_BIN ENDP
BITS Pilani, Pilani Campus
MOV AL, BCDINPUT
CALL BCD_BIN Using reg

BCD_BIN PROC NEAR

Using Mem
MOV AL, BCDINPUT

MOV SI, OFFSET BCDINPUT

CALL BCD_BIN Using Pointers

BCD_BIN PROC NEAR

MOV AL, [SI]

BITS Pilani, Pilani Campus

Passing parameters using stack

 Push parameters on stack before calling the procedure

 Instructions in procedure read these parameters from stack as needed.
 Parameters passed back from procedure are written on stack and read by the main-line program.

BITS Pilani, Pilani Campus

 PUSH BP
.model tiny MOV BP, SP
.data MOV AX, [BP + 12]
bcd_input db 16 MOV BL , AL
bin_value db (0) AND BL , 0FH
.code AND AL , 0F0H
.startup
MOV CL , 04
MOV AL,BCD_INPUT
PUSH AX ROR AL, CL
CALL BCD_BIN MOV BH , 0AH
POP AX MUL BH
MOV BIN_VALUE, AL ADD AL, BL
MOV [BP + 12], AX
;EX: BCD to Binary Conversion POP BP
BCD_BIN PROC NEAR POP CX
PUSHF
POP BX
PUSH AX
POP AX
PUSH BX
PUSH CX POPF
RET
BCD_BIN ENDP
.exit
end
BITS Pilani, Pilani Campus
 8086-80486 Subroutines
Lect-22

BITS Pilani
Pilani Campus
Write a procedure SUMS that sums EAX, EBX, ECX, and EDX. If a carry
occurs, place a logic 1 in EDI. If no carry occurs, place a 0 in EDI. The sum
should be found in EAX after the execution of your procedure.

SUMS PROC NEAR

MOV EDI, 0
ADD EAX, EBX
JNC X2
MOV EDI, 01h
X2: ADD EAX, ECX
JNC X3
MOV EDI, 01h
X3: ADD EAX, EDX
JNC X4
MOV EDI, 01h
X4:
RET
SUMS ENDP
 Write a near procedure SQRADD that squares the contents of the CX register and adds that in BX (storing it
in BX). This procedure must not affect any register except BX.

SQRADD PROC NEAR USES AX DX

MOV AX,CX
MUL CX
ADD BX, AX •The USES keyword tells the assembler that registers AX and DX
RET will be used inside the procedure.
SQRADD ENDP
•Before modifying AX and DX, the assembler will automatically push
them onto the stack at the start of the procedure.

•At the end of the procedure, these registers will be popped back,
restoring their original values.

•This helps in preserving register values and prevents unwanted

modification
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
 BITS Pilani BITS Pilani
Pilani | Dubai | Goa | Hyderabad

8086 Pin Description

Modes of Operations

BITS Pilani

8088/8086 can be configured to work in any of the two modes

Minimum Mode
Maximum Mode

Minimum Mode
Single processor based system
Simpler/Smaller systems

Maximum Mode
Larger systems – to be used when a co-processor exists in the system
Co-processor supplements the functions of the primary processor
Numeric Data processor (8087) –coprocessor
 BITS Pilani BITS Pilani
Pilani | Dubai | Goa | Hyderabad

8086 PIN FUNCTIONS– Minimum Mode

 BITS Pilani

A0 Add
Bus
A19

D0 Data
Bus
8086 D15

Control
signals
Dual In-line Package (DIP)
 8086 BITS Pilani

Address bus
BIU Discs
I/o
ROM RAM
Ports Video

Data Bus

ALU

CLK
Control
& Timing

EU
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD RQ/GT0
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD RQ/GT0
AD5 11 30 HLDA RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Clock

CLK is provided to 8086 from an external clock

BITS Pilani

generator device such as 8284

One cycle of this clock is called a T-state
A T-state is measured as falling edge of one
clock pulse to falling edge of next clock pulse
Different versions of 8086 have maximum clock
frequencies of between 5MHz and 10MHz
The minimum time of one T-state will be
between 200nS -100nS
Clock Generator- 8284
BITS Pilani
Reset
BITS Pilani
Reset input causes the microprocessor to reset
itself if this pin is held high for a minimum of
four clocking periods.
Whenever the 8086 is reset, it begins executing
instructions at memory location FFFF0H
Disables interrupts by clearing the IF flag
bit
 Instruction Cycle BITS Pilani

Bus/Machine Cycle

T states

A basic operation such as

Reading/writing a byte/word from/to memory or
Reading/writing a byte/word from/to a port

is referred to as a machine cycle

A port in an interface that allows the CPU to communicate with

external devices, such as sensors, displays, memory, and other
peripherals.
Machine Cycle
BITS Pilani

MEMR- Memory Read

For Opcode
For Data
MEMW- Memory Write
Data
IOR- I/O Read
IOW- I/O Write
 BITS Pilani

MOV AX, BX
Machine code: 89D8
Machine cycle: 1
 BITS Pilani

MOV CX,[1234H]
Machine code: 8B0E 3412
Machine cycle: 3
 BITS Pilani

ADD AX, [BX]

Machine code: 0307
Machine cycle: 2
 BITS Pilani

CBW
Machine code: 98
Machine cycle: 1
 BITS Pilani

ADD [1234H], AX
Machine code : 0106 3412
Machine cycle: 4
 BITS Pilani

Instruction Cycle

Bus/Machine Cycle

T states
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD
HLDA
RQ/GT0
AD5 11 30 RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7 MN/MX’ –
AD8 8 33 MN/MX logic 1
(Minimum
AD7 9 32 RD mode)
AD6 10 8086 31 HOLD
HLDA
RQ/GT0
MN/MX’ –
AD5 11 30 RQ/GT1 logic 0
AD4 12 29 WR LOCK (Maximum
AD3 13 28 M/IO S2 mode)

AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
 BITS Pilani BITS Pilani
Pilani | Dubai | Goa | Hyderabad

8086 Address bus

 BITS Pilani

ADDRESS & DATA signals are MULTIPLEXED

GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD
HLDA
RQ/GT0
AD5 11 30 RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
 BITS Pilani

ADDRESS & DATA signals are MULTIPLEXED

De-multiplexed externally using latch

ALE
BITS Pilani

Indicates that address/data bus contains address

information
The address can be for addressing a memory or
an I/O device.
 BITS Pilani

74LS273

Octal Latch
G OE

ALE
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD
HLDA
RQ/GT0
AD5 11 30 RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
ALE/BHE’
BITS Pilani

Indicates that address/data bus contains address

information
The address can be for addressing a memory or
an I/O device.

The BHE’ pin enables data bus bits (D15–D8)

during a read or a write operation.
Memory Access BHE’ A0
Word (16-bit) at 0 0
Even Address

16 bit odd address 0 1

Byte even 1 0
Byte odd 0 1
 A16-A19
S6-S3
A16-A19
LS373
BITS Pilani

BHE’/S7 BHE’
G OE’

ALE

8086
AD8-AD15 LS373 A8-A15
G OE’

AD0-AD7 LS373 A0-A7

G OE’

MN/MX’ 5V
System Bus of 8086 (Address)
 BITS Pilani
Signal Address Status

AD16/S3 AD16 S3 Segment

Access
AD17/S4 AD17 S4

AD18/S5 AD18 S5 Interrupt Flag

bit
AD19/S6 AD19 S6 0

BHE’/S7 BHE S7 1
 A16-A19
S6-S3
A16-A19
LS373
BITS Pilani

BHE’/S7 BHE’
G OE’

ALE

8086
AD8-AD15 LS373 A8-A15
G OE’

AD0-AD7 LS373 A0-A7

G OE’

MN/MX’ 5V
System Bus of 8086 (Address)
 BITS Pilani BITS Pilani
Pilani | Dubai | Goa | Hyderabad

8086 Data bus

GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD
HLDA
RQ/GT0
AD5 11 30 RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Buffered Systems
BITS Pilani

Buffering of control/data/addr busses  signals

sufficiently strong to drive various IC chips
Bus buffering  Boosting the bus signals to increase the FANOUT
Unidirectional Buffer - 74LS244
Bidirectional Buffer - 74LS245
Unidirectional Buffer
BITS Pilani

A Bus B Bus
Input Output

0
Bidirectional Buffer
BITS Pilani

A Bus
B Bus

E DIR

0 1/0
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD
HLDA
RQ/GT0
AD5 11 30 RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Bidirectional Buffer – 8086 Data bus
BITS Pilani

A Bus B Bus
Inputs/Outputs Inputs/Outputs

E DIR

DEN DT/R
 BITS Pilani
8086

AD8-AD15 LS245 D8-D15

DT/R’ DIR OE’
DEN’

AD0-AD7 LS245 D0-D7

DIR OE’

MN/MX’ 5V

System Bus of 8086(Data)

GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7 MN/MX’ –
AD8 8 33 MN/MX logic 1
(Minimum
AD7 9 32 RD mode)
AD6 10 8086 31 HOLD
HLDA
RQ/GT0
MN/MX’ –
AD5 11 30 RQ/GT1 logic 0
AD4 12 29 WR LOCK (Maximum
AD3 13 28 M/IO S2 mode)

AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
 BITS Pilani

Instruction Cycle

Bus/Machine Cycle

T states

A basic operation such as

Reading/writing a byte/word from/to memory or
Reading/writing a byte/word from/to a port
is referred to as a machine cycle
 BITS Pilani

ADD [1234H], AX
Machine code : 0106 3412
Machine cycle: 4
 BITS Pilani

CBW
Machine code: 98
Machine cycle: 1
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7 MN/MX’ –
AD8 8 33 MN/MX logic 1
(Minimum
AD7 9 32 RD mode)
AD6 10 8086 31 HOLD
HLDA
RQ/GT0
MN/MX’ –
AD5 11 30 RQ/GT1 logic 0
AD4 12 29 WR LOCK (Maximum
AD3 13 28 M/IO S2 mode)

AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Memory Access BHE’ A0
Word (16-bit) at 0 0
Even Address

16 bit odd address 0 1

Byte even 1 0
Byte odd 0 1

The BHE’ pin enables data bus bits (D15–D8) during a read or a write
operation.
 A16-A19
S6-S3
A16-A19
LS373
BITS Pilani

BHE’/S7 BHE’
G OE’

ALE

8086
AD8-AD15 LS373 A8-A15
G OE’

AD0-AD7 LS373 A0-A7

G OE’

MN/MX’ 5V
System Bus of 8086 (Address)
 BITS Pilani
8086

AD8-AD15 LS245 D8-D15

DT/R’ DIR OE’
DEN’

AD0-AD7 LS245 D0-D7

DIR OE’

MN/MX’ 5V

System Bus of 8086(Data)

 BITS Pilani BITS Pilani
Pilani | Dubai | Goa | Hyderabad

8086 Control bus

GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD
HLDA
RQ/GT0
AD5 11 30 RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
 BITS Pilani

M/IO’- Indicates that microprocessor address bus

contains memory/IO address
WR’ – Low indicates that the bus contains valid
data for Memory or I/O

RD’- Processor is ready to receive data from

Memory or I/O
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 8086 31 HOLD
HLDA
RQ/GT0
AD5 11 30 RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
 M/IO’ IOR’ BITS Pilani

RD’
M/IO’ RD’ WR’ Bus cycle

1 0 1 MEMR’

M/IO’ IOW’ 1 1 0 MEMW’

WR’ 0 0 1 IOR’

0 1 0 IOW’

M/IO’ MEMR’
RD’

M/IO’ MEMW’
WR’
 RD MEMR
LOGIC MEMW
BITS Pilani

WR LS244
CIRCUIT IOR
IO/M OE’
IOW

MN/MX’ 5V
System Bus of 8086( Control)
 A16-A19
S6-S3
A16-A19
LS373
BITS Pilani

BHE’/S7 BHE’
G OE’

ALE

8086
AD8-AD15 LS373 A8-A15
G OE’

AD0-AD7 LS373 A0-A7

G OE’

MN/MX’ 5V
System Bus of 8086 (Address)
 MEMR
RD
LOGIC MEMW
BITS Pilani

WR LS244
CIRCUIT IOR
IO/M OE’
IOW

8086
AD8-AD15 LS245 D8-D15
DT/R’ DIR OE’
DEN’

AD0-AD7 LS245 D0-D7

DIR OE’

MN/MX’ 5V
System Bus of 8086(Data + Control)
Signals of 8086 used during a bus transfer
AD15 – AD0 – Multiplexed Address & Data BITS Pilani

A19/S6 – A16/S3 – Higher order Address / Status

M/IO’ – Indicates whether access is to
memory or I/O Device
RD’ - Read Operation from Memory/IO
WR’ - Write Operation to Memory/IO
ALE - When set – Multiplexed AD0 – AD15
has address
DT/R’ - 8086 is transmitting/receiving data
DEN’ - Enable data buffers connected to
8086
 Tw
T1 T2 T3 T4
CLK BITS Pilani

A19-A16/S6–S3 A19 – A16 S6 – S3

AD15- AD0 A15-A0 tDaata

Address Setup Data Setup
M/IO’

ALE
DT/R’

RD’

DEN’

200 ns
800 ns

Bus Timings for a Read Operation

Prof. Meetha V Shenoy, Prof. Vinay Chamola
 Tw
T1 T2 T3 T4
CLK

A19-A16/S6–S3 A19 – A16 S7 – S3

AD19- AD16 A15-A0 Data

Address Setup Data Setup
M/IO’

ALE
DT/R’

RD’

DEN’

200 ns
800 ns

Bus Timings for a Read Operation

Memory access time:

Time taken by the memory to decode the address and provide

valid data after receiving the request.
Memory access time starts when the address appears on the
memory address bus and continues until the microprocessor
samples the memory data at T3.

(600-110-30)ns= 460ns

Time taken by the memory to decode the address and provide

valid data after receiving the request.
 Tw
T1 T2 T3 T4
CLK

A19-A16/S6–S3 A19 – A16 S7 – S3

AD19- AD16 A15-A0 Data

Address Setup Data Setup
M/IO’

ALE
DT/R’

RD’

DEN’

200 ns
800 ns

Bus Timings for a Read Operation

GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
31
AD6 10
11
8086 30
HOLD
HLDA
RQ/GT0
AD5 RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
READY Signal & WAIT States

If READY is a logic 0 at the end of T2, T3 is delayed and Tw

is inserted between T2 and T3.
READY is next sampled at the middle of Tw to
determine whether the next state is Tw or T3.
READY pin is tested for a logic 0 on the 1-to-0 transition of
the clock at the end of T2, and for a 1 on the 0-to-1
transition of the clock in the middle of Tw
 T1 T2 Tw T3 T4
CLK

A19-A16/S6–S3 A19 – A16 S7 – S3

AD0- AD15 A15-A0 Data

Address Setup Data Setup
M/IO’

ALE
DT/R’

RD’

DEN’

200 ns
1000 ns

Bus Timings for a Read Operation

WAIT States

A wait state (Tw) is an extra clocking period, inserted between

T2 and T3 to lengthen the bus cycle.

If one wait state is inserted, then the memory access time,

normally 460 ns with a 5 MHz clock, is lengthened by one
clocking period (200 ns) to 660 ns
WR’ – Low indicates that the bus contains valid data for
Memory or I/O
 T1 T2 T3 T4
CLK

A19-A16/S6–S3 A19 – A16 S7 – S3

AD0- AD15 A15-A0 Data

Address Setup
M/IO’

ALE
DT/R’

WR’

DEN’

200 ns
800 ns

Bus Timings for a Write Operation

GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
31
AD6 10
11
8086 30
HOLD
HLDA
RQ/GT0
AD5 RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
 Interrupt Handling

NMI

INTR

INTA’ (output)
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
31
AD6 10
11
8086 30
HOLD
HLDA
RQ/GT0
AD5 RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
 DMA Access

HOLD

HLDA (output)

Direct Memory Access (DMA) is a method that allows peripheral

devices to transfer data directly to/from memory without involving
the CPU.
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
31
AD6 10
11
8086 30
HOLD
HLDA
RQ/GT0
AD5 RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
TEST ’

The TEST' pin of the microprocessor is usually connected to

the BUSY pin of the 8087 numeric coprocessors.

This connection allows the microprocessor to wait until the

coprocessor finishes a task.
Functionality of WAIT Instruction

The WAIT instruction in 8086 is used to pause the execution of

the processor until the TEST’ pin (active-low) is cleared to 0.

How WAIT Works

• The CPU fetches the WAIT instruction.

• The CPU checks the TEST' pin:
• If TEST' = 1 (high) → The CPU waits indefinitely.
• If TEST' = 0 (low) → The CPU resumes execution of the next
instruction.
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
31
AD6 10
11
8086 30
HOLD
HLDA
RQ/GT0
AD5 RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Interfacing to Processor
8088
 Address Bus

 Data Bus

 Control Signals

 Based on the memory capacity of the chip

A 2K Memory Chip

A0 -
A10

D0 -
2K x 8
D7

RD

WR
CS
 8K Memory – 4 – 2K chips of memory

 Memory Mapping

 RAM1 00000H – 007FFH

 RAM2 00800H- 00FFFH
 RAM3 01000H- 017FFH
 RAM4 01800H-01FFFH
 MEMW WR
MEMR RD
Data Bus of CPU D0-D7

A0 –A10 of CPU A0-A10

Remaining Address CS
address lines of Decoding
CPU Logic
Interfacing to Processor
8088
 Address Bus

 Data Bus

 Control Signals

 Based on the size of the chip

 8K Memory – 4 – 2K chips of memory

 Memory Mapping

 RAM1 00000H – 007FFH

 RAM2 00800H- 00FFFH
 RAM3 01000H- 017FFH
 RAM4 01800H-01FFFH
A 2K Memory Chip

A0 -
A10

D0 -
2K x 8
D7

RD

WR
CS
 MEMW WR
MEMR RD
Data Bus of CPU D0-D7

A0 –A10 of CPU A0-A10

Remaining Address CS
address lines of Decoding
CPU Logic
 Memory Address Decoding

INPUT OUTPUT
S O0 ENABLE SELECT
A E
L O1 G1 G2A G2B A B C O0 O1 O2 O3 O4 O5 O6 O7

B E 0 X X X X X 1 1 1 1 1 1 1 1
C O2 X 1 X X X X 1 1 1 1 1 1 1 1
C T
O3 X X 1 X X X 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1 1 1 1 1 1 1
LS138 O
4 1 0 0 0 0 1 1 0 1 1 1 1 1 1
E 1 0 0 0 1 0 1 1 0 1 1 1 1 1
O5
G1 N 1 0 0 0 1 1 1 1 1 0 1 1 1 1
G2A A O6 1 0 0 1 0 0 1 1 1 1 0 1 1 1
G2B B O7 1 0 0 1 0 1 1 1 1 1 1 0 1 1
L
E 1 0 0 1 1 0 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
RAM1 00000H – 007FFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
RAM2 00800H- 00FFFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
RAM3 01000H-017FFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1
RAM4 01800H-01FFFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
 Memory Address Decoding

INPUT OUTPUT
S O0 ENABLE SELECT
A E
L O1 G1 G2A G2B A B C O0 O1 O2 O3 O4 O5 O6 O7

B E 0 X X X X X 1 1 1 1 1 1 1 1
C O2 X 1 X X X X 1 1 1 1 1 1 1 1
C T
O3 X X 1 X X X 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1 1 1 1 1 1 1
LS138 O
4 1 0 0 0 0 1 1 0 1 1 1 1 1 1
E 1 0 0 0 1 0 1 1 0 1 1 1 1 1
O5
G1 N 1 0 0 0 1 1 1 1 1 0 1 1 1 1
G2A A O6 1 0 0 1 0 0 1 1 1 1 0 1 1 1
B
G2B L O7 1 0 0 1 0 1 1 1 1 1 1 0 1 1
E 1 0 0 1 1 0 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
 S O0 RAM1
A13 A E
L O1 RAM2
A12 B E
A11 C O2 RAM3
C T
A16 O3 RAM4
A17 LS138 O
A18 4
E
A19 O5
G1 N unused
A14 G2A A O6
B
A15 G2B L O7
E

Absolute Addressing
 S O0 RAM1
A E
L O1 RAM2
A12 B E
A11 C O2 RAM3
C T
O3 RAM4
LS138 O
4
E
O5
5V G1 N unused
G2A A O6
B
G2B L O7
E

Incremental Addressing
 MEMW WR
MEMR RD
Data Bus of CPU D0-D7

A0 –A10 of CPU A0-A10

Remaining Address CS
address lines of Decoding
CPU Logic
 No of Memory chips

 Address Space

 Decoding logic
8088
For the memory chips available each do the
interfacing for 8088

Ex: Interface
4K - 2716 (ROM) starting at 00000H
8K - 6116 (SRAM) starting at 08000H
Memory Requirements

2716 – ROM - size 2K (16/8)

ROM – 4k
Number of 2716 required – 2

6116 – RAM size 2k (16/8)

RAM – 8k
Number of 6116 required - 4
Memory Map
ROM 1 - 00000H – 007FFH
ROM2 - 00800H – 00FFFH
RAM1 - 08000H – 087FFH
RAM2 - 08800H – 08FFFH
RAM3 - 09000H – 097FFH
RAM4 - 09800H – 09FFFH
ROM1 00000H – 007FFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1

ROM2 00800H- 00FFFH

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
RAM1 08000H-087FFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
RAM2 08800H- 08FFFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
RAM3 09000H-097FFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1
RAM4 09800H-09FFFH

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
 S O0 ROM1
A15 A E
L O1 ROM2
A12 B E
A11 C O2
C T unused
A16 O3
A17 LS138 O RAM1
A18 4
E
A19 O5 RAM2
G1 N
A14 G2A A O6 RAM3
B
A13 G2B L O7 RAM4
E

Absolute Addressing
 D0-D7
A0-A10

D0- A0- D0- A0-

D7 A10 D7 A10

ROM1 ROM2
A15 A OO CS’
A12 B
CS’
O1
A11 C O2
OE’ OE’
O3
Unused
MEMR’
LS138
O4 MEMW’
A13 G2A
O5
A14 G2B CS’ RD’ WR’ CS’ RD’ WR’ CS’ RD’ WR’ CS’ RD’ WR’
G1 O6

O7
RAM1 RAM2 RAM3 RAM4

D0- A0- D0- A0- D0- A0- D0- A0-

A16 D7 A10 D7 A10 D7 A10 D7 A10
A17
A18
A0-A10
A19
D0-D7
8086/80286
 8086 has 20 bit address bus / 80286 has 24 bit address
 1 MB / 16 MB - each address represent a byte
 An Inst such as MOV [437AH] , BX
 Word written to two consecutive locations 0437AH & 0437BH
 To complete the write in one cycle memory set up as two banks
 512 K bytes each
 ODD Bank & EVEN Bank
 Byte- Wide Addr Even -Address Odd -Address
8088 FFFFF FFFFE 8086 FFFFF
FFFFE FFFFC FFFFD
FFFFD FFFFA FFFFB
A0- A19 A1- A19 A1- A19
FFFFC FFFF8 FFFF9

00002 00004 00005

00001 00002 00003
00000 00000 00001

D0- D7 D0- D7 D8- D15

A0 BHE’
1 MB 512 KB even 512 KB odd
BHE’ A0 Selection
0 0 Whole Word
0 1 High byte to/from odd address
1 0 Low byte to/from even address
1 1 No Selection
Address Data BHE’ A0 Bus Data lines
Type Cycles used
00000 Byte 1 0 one D0 –D7
00000 Word 0 0 one D0 –D15
00001 Byte 0 1 one D8 –D15
00001 Word 0 1 first D8 –D15
1 0 second D0 –D7
8086
 8086 has 20 bit address bus / 80286 has 24 bit address
 1 MB / 16 MB - each address represent a byte
 An Inst such as MOV [437AH] , BX
 Word written to two consecutive offset locations 437AH & 437BH
 To complete the write in one cycle memory set up as two banks
 512 K bytes each (8086)
 ODD Bank & EVEN Bank
 Byte- Wide Addr Even -Address Odd -Address
8088 FFFFF FFFFE 8086 FFFFF
FFFFE FFFFC FFFFD
FFFFD FFFFA FFFFB
A0- A19 A1- A19 A1- A19
FFFFC FFFF8 FFFF9

00002 00004 00005

00001 00002 00003
00000 00000 00001

D0- D7 D0- D7 D8- D15

A0 BHE’
1 MB 512 KB even 512 KB odd
Address Data BHE’ A0 Bus Data lines
Type Cycles used
00000 Byte 1 0 one D0 –D7
00000 Word 0 0 one D0 –D15
00001 Byte 0 1 one D8 –D15
00001 Word 0 1 first D8 –D15
1 0 second D0 –D7
8086
Example 1:

If memory chips available are only 2KB each do

the interfacing for 8086

Ex: Interface
4K 2716 (ROM) starting at 00000H
8K 6116 (SRAM) starting at 08000H
Memory Requirements

2716 – size 2K
ROM – 4k ROM – 4k
Number of 2716 – 2

6116 – size 2k
RAM – 8k RAM – 8k
Number of 6116 -4
 ROM – 4k

2k even 2k odd

RAM – 8k

4K 4K

2k even 2k odd 2k even 2k odd

Memory Map
ROM 1E - 00000H ,00002H, 00004H …….. 00FFEH
ROM 1O - 00001H, 00003H, 00005H …….. 00FFFH
RAM 1E - 08000H, 08002H, 08004H …….. 08FFEH
RAM 1O - 08001H, 08003H, 08005H ........ 08FFFH
RAM 2E - 09000H, 09002H, 09004H …….. 09FFEH
RAM 2O - 09001H, 09003H, 09005H …….. 09FFFH
ROM1 00000H – 00FFFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

RAM1 08000H- 08FFFH

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
RAM2 09000H-09FFFH
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
 BHE
A0
S ROM1 ROM1E
O0
A16 A E
L O1 ROM1O
A15 B E
A12 C O2 RAM1 RAM1E
C T
O3 RAM2
A17 RAM1O
A18 LS138 O
4
A19 E
O5
G1 N RAM2E
A14 G2A A O6
B RAM2O
A13 G2B L O7
E

Absolute Addressing
 A11 A10 D15 –D8 A11 D7 –D0
A10
2K
2K

A1 A0 A1
A17 CS A0
A18 CS
A19

G1
7
A12 C 4 A0
BHE
A15 B 1
3 3
A16 A 2
8
0
G2A G2B

A13 A14
Example 2:

Interface 1M of SRAM to 8086

Chips available are of size 256K each

OR gates not available,

Assume system bus signals are available
A19A18A17A16 A15A14A13A12 A11A10A9A8 A7A6A5A4 A3A2A1A0

0 0 0 0 0 0 0 0 0 0 00 0000 0000
512KB
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1
1 0 0 0 0 0 0 0 0 0 00 0000 0000
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 512KB
 A18 A17 D15 –D8 D7 –D0
A18 A17
256K
256K

A1 A0
CS A1 A0
CS
VCC VCC
GND GND
G1 G1
7 7
C 4 C 4
B 1 B 1
3 3
A19 A 1 A19 A 1
8 8
G2A G2B 0 G2A G2B 0

BHE GND A0 GND

 Example 3:

Interface 16K of RAM to 8086 starting at 00000H

Chips available are 2KB(4 Chips) and 4KB (2 Chips)

RAM1even 00000H, 00002H, 00004H, ………….00FFEH

RAM1odd 00001H, 00003H, 00005H, ………….00FFFH
RAM2even 01000H, 01002H, 01004H, ………….01FFEH
RAM2odd 01001H, 01003H, 01005H, ………….01FFFH
RAM3even 02000H, 02002H, 02004H, ………….03FFEH
RAM3odd 02001H, 02003H, 02005H, ………….03FFFH
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
 S O0 RAM1
A14 A E
L O RAM2
1
A13 B E
A12 C O2 RAM3
C T
O3 RAM3
A17
A18 LS138 O
4
A19 E
O5
G1 N
A15 G2A A O6
B
A16 G2B L O7
E

Absolute Addressing
 4K 4K
A11 A10 D15 –D8 A11 D7 –D0
A
A1010
A1 A0 2K A1
WR A
A00 2K
2K WR
2K
BHE WR’ WR’
A17 RD’ CS A0
RD’ CS
A18
A19

G2A RD BHE A0
7 RD
A12 C 4
A13 B 1 3
2
A 3
A14 1
8 0

G1 G2B
A16
M/IO’ A15
80286
 Example 1:
Interface 4K of ROM to 80286 starting at 080000H

Chips available are 2716. 2 decoders, One 2i/p OR

gate available
ROMeven 080000H, 080002H, 080004H, ………….080FFEH
ROModd 080001H, 080003H, 080005H, ………….080FFFH

080000H - 080FFFH
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
 A11 A10 D15 –D8
A11 A10 D7 –D0
2K
2K

A0
A1 CS A1 A0
CS
A A’
19 19

A12 7 A12 7
C 4 C 4
A13 B 1 A13 B 1
A14 3 A14 3
A 1 A 1
8 8
0 0

BHE A0

A15A16A17A18
Example 2:

Interface 8K of ROM to 80286 starting at 080000H

Chips available are 2 KB each.

2 Decoders, 2, four i/p OR gate available

ROM1even 080000H, 080002H, 080004H, ………….080FFEH

ROM1odd 080001H, 080003H, 080005H, ………….080FFFH

ROM2even 081000H, 081002H, 081004H, …………. 081FFEH

ROM1odd 081001H, 081003H, 081005H, …………. 081FFFH
 080000H - 080FFFH
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

081000H - 081FFFH
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
 A11 A10 D15 –D8 D7 –D0
A11 A10
2K
2K

A0
A1 CS A1 A0
CS
A19 A19

A12 7 A12 7
C 4 C 4
A13 B 1 A13 B 1
A14 3 A14 3
A 1 A 1
8 8
0 0

BHE A0

A15A16A17A18 A20 A21 A22 A23

Input-Output (I/O)
Interfacing
I/O Interfacing
I/O Instructions

IN and OUT instructions

Address Size Instruction Format Port Range

8-bit IN AL, imm8 / OUT imm8, AL 0x00 – 0xFF
16-bit IN AL, DX / OUT DX, AL 0x0000 – 0xFFFF
I/O Interfacing
I/O Interfacing
8255
 8255 – Programmable Peripheral
Interface (PPI)
BITS Pilani
Pilani Campus
8255
Intel has developed several peripheral control chips for 80x86
family
8255 –PPI provides 3, 8-bit I/O ports in one package
Chip can be directly interfaced to the data bus of 8086
Chip ports can be programmed to function as input or output

BITS Pilani, Pilani Campus

 PA3 1 40 PA4
Port A PA2 2 39 PA5 Port A
PA1 3 38 PA6
PA0 4 37 PA7
RD 5 36 WR
CS 6 35 RESET
GND 7 34 D0
A1 8 33 D1
A0 9 32 D2
PC4 10 8255 31 D3
Upper Port C PC5 11 30 D4
PC6 29 D5
12
PC7 28 D6
13
PC0 14 27 D7
Lower Port C PC1 15 26 VCC
PC2 25 PB7
16
PC3 24 PB6
17
PB0 PB5 Port B
18 23
Port B PB1 PB4
19 22
PB2 20 21 PB3
8255 Internal Diagram
CS’ A1 A0 Selected

0 0 0 Port A

0 0 1 Port B

0 1 0 Port C

0 1 1 Control Register

1 X X 8255 Not Selected

BITS Pilani, Pilani Campus

D7 D6 D5 D4 D3 D2 D1 D0
1 – I/O Port A Mode Port A Port C Port B Port B Port C
Mode 0 0 - Mode 0 1 – i/p Upper Mode 1 – i/p Lower
0 1 - Mode 1 0 – o/p 1 – i/p 0- Mode0 0 – o/p 1 – i/p
1 x – Mode2 0 – o/p 1- Mode1 0 – o/p

Group A Group B

BITS Pilani, Pilani Campus

Modes of Operation
D7

0 –BSR 1 – I/O
Affects only Port C

Mode 0 Mode 1 Mode 2

Simple I/O Handshake Handshake
(A,B,C) I/O -- (A,B) Bi-directional I/O (A)
C - Handshake C – Handshake
B – Mode 0,1

BITS Pilani, Pilani Campus

Modes
Mode 0 – Basic Input/Output:
Ports operate as simple, unidirectional I/O channels.
Data is transferred directly without handshaking or additional control
signals.

Mode 1 – Strobed (Handshake) I/O:

Provides additional handshaking signals to coordinate data transfer
between the 8255 and external devices.
Involves strobes or control lines to indicate readiness and ensure data
is transferred only when both sides are ready.
Useful when timing and data integrity are critical.

Mode 2 – Bidirectional I/O:

Allows one port (typically Port A) to operate as a bidirectional data bus.
Utilizes specific lines in Port C to control the direction (input or output)
dynamically.

BITS Pilani, Pilani Campus

Modes of Operation
D7

0 –BSR 1 – I/O
Affects only Port C

Mode 0 Mode 1 Mode 2

Simple I/O Handshake Handshake
(A,B,C) I/O -- (A,B) Bi-directional I/O (A)
C - Handshake C – Handshake
B – Mode 0,1

BITS Pilani, Pilani Campus

D7 D6 D5 D4 D3 D2 D1 D0

0 -BSR x x x Bit2 Bit1 Bit0 Bit Set/Reset

PC 0 1 2 3 4 5 6 7 1 – Set
Don’t Care
Condition B0 0 1 0 1 0 1 0 1 0 - Reset
B1 0 0 1 1 0 0 1 1
B2 0 0 0 0 1 1 1 1

BITS Pilani, Pilani Campus

BSR Mode of 8255 Port C
Example: Connect 3 LEDs to Port C. Blink one LED after another
at regular intervals of 1ms
8255- Base address 00H

BITS Pilani, Pilani Campus

 D0 – D7 PA0 – PA7

A0
System PB0 – PB7
A1
I/f Device
RD
8255
WR I/f

CS
PC0 – PC3
RESET
PC4 – PC7

BITS Pilani, Pilani Campus

 A1 A0
A2 A1

A0 CS
A3
A4
M/IO’
A5
8255
A6
A7 RD RD
WR WR

D0 – D7 D0 – D7

RESET from 8284

RESET

Interface to the processor

BITS Pilani, Pilani Campus
Output Device
Common cathode configuration
Ex: LED
A R
1

BITS Pilani, Pilani Campus

Output Device
Common anode configuration

Ex: LED
A R
0 Vcc

BITS Pilani, Pilani Campus

1 1 0 PC2

1 0 1 PC1

0 1 PC0

5V
8255

Interface to the I/O Devices

 8255 – Programmable
Peripheral Interface (PPI)
BITS Pilani
Pilani Campus
 Power + 5V
Supply GND Group Port PA0 –
A A (8) PA7
Control

D0 – D7 Data Group A PC0 –

Bus Port C PC3
Buffer Upper(4)
8 –bit intren al
data bus Group B PC4 –
RD Port C PC7
WR Group Lower(4)
A0 R/W B
A1 Control Control
Port PB0 –
Logic
RESET B(8) PB7

CS 8255A Internal
BITS Pilani, Pilani Campus
CS’ A1 A0 Selected

0 0 0 Port A

0 0 1 Port B

0 1 0 Port C

0 1 1 Control Register

1 X X 8255 Not Selected

BITS Pilani, Pilani Campus

 D7

0 –BSR 1 – I/O
Affects only Port C

Mode 0 Mode 1 Mode 2

Simple I/O Handshake Handshake
(A,B,C) I/O -- (A,B) Bi-directional I/O (A)
C - Handshake C – Handshake
B – Mode 0,1

BITS Pilani, Pilani Campus

Modes

Mode 0 – Basic Input/Output:

Ports operate as unidirectional I/O.

Any of the ports -A,B,CL,CU can be programmed as i/p or o/p

Data is transferred directly without handshaking or additional

control signals.

BITS Pilani, Pilani Campus

D7 D6 D5 D4 D3 D2 D1 D0
1 – I/O Port A Mode Port A Port C Port B Port B Port C
Mode 0 0 - Mode 0 1 – i/p Upper Mode 1 – i/p Lower
0 1 - Mode 1 0 – o/p 1 – i/p 0- Mode0 0 – o/p 1 – i/p
1 x – Mode2 0 – o/p 1- Mode1 0 – o/p

Group A Group B

BITS Pilani, Pilani Campus

 D7

0 –BSR 1 – I/O
Affects only Port C

Mode 0 Mode 1 Mode 2

Simple I/O Handshake Handshake
(A,B,C) I/O -- (A,B) Bi-directional I/O (A)
C - Handshake C – Handshake
B – Mode 0,1

BITS Pilani, Pilani Campus

D7 D6 D5 D4 D3 D2 D1 D0

0 -BSR x x x Bit2 Bit1 Bit0 Bit Set/Reset

Don’t Care PC 0 1 2 3 4 5 6 7 1 – Set

Condition B0 0 1 0 1 0 1 0 1 0 - Reset
B1 0 0 1 1 0 0 1 1
B2 0 0 0 0 1 1 1 1

BITS Pilani, Pilani Campus

BSR Mode of 8255 Port C
Example: Connect 3 LEDs to Port C. Blink one LED after another
at regular intervals of 1ms
8255- Base address 00H

CS’ A1 A0 Selected
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control Register
1 X X 8255 Not Selected
BITS Pilani, Pilani Campus
 D0 – D7 PA0 – PA7

System A0
PB0 – PB7
A1
I/f
Device
RD
8255
WR I/f

CS
PC0 – PC3
RESET
PC4 – PC7

BITS Pilani, Pilani Campus

 A1 A0
A2 A1

A0 CS
A3
A4
M/IO’
8255
A5
A6
A7 RD RD
WR WR

D0 – D7 D0 – D7

RESET from 8284

RESET

Interface to the processor

BITS Pilani, Pilani Campus
Output Device
Common cathode configuration
Ex: LED
A R
1

BITS Pilani, Pilani Campus

Output Device
Common anode configuration

Ex: LED
A R
0 Vcc

BITS Pilani, Pilani Campus

 PC2

PC1

PC0

5V
8255

Interface to the I/O Devices

 creg equ 06h
mov al,80h
out creg,al

D7 D6 D5 D4 D3 D2 D1 D0
1 – I/O Port A Mode Port A Port C Port B Port B Port C
Mode 0 0 - Mode 0 1 – i/p Upper Mode 1 – i/p Lower
0 1 - Mode 1 0 – o/p 1 – i/p 0- Mode0 0 – o/p 1 – i/p
1 x – Mode2 0 – o/p 1- Mode1 0 – o/p

Group A Group B

BITS Pilani, Pilani Campus

 creg equ 06h
mov al,80h
out creg,al
X1: mov al,00
out creg,al
mov al,03
out creg,al
mov al,05
out creg,al
call delay_1ms
mov al,01
out creg,al
mov al,02
out creg,al
mov al,05
out creg,al

BITS Pilani, Pilani Campus

call delay_1ms
mov al,01
out creg,al
mov al,03
out creg,al
mov al,04
out creg,al
call delay_1ms
jmp x1

BITS Pilani, Pilani Campus

Mode 0 : Simple Input/Output
E.g. Read 12 switches and display switch condition on 12 LEDs
8255H – Base Address – 00H

Inputs connected to - PA0-PA7, PC4-PC7

Outputs connected to - PB0-PB7, PC0-PC3

BITS Pilani, Pilani Campus

 PB0
Switch open- Led off

Switch closed - Led on

PB7
PC0
PC3
8255 PA0 5V

PA
PC47

PC7

5V
Interface to the I/O Devices
BITS Pilani, Pilani Campus
 A1 A0
A2 A1

A0 CS
A3
A4
M/IO’
8255
A5
A6
A7 RD RD
WR WR

D0 – D7 D0 – D7

RESET from 8284

RESET

Interface to the processor

BITS Pilani, Pilani Campus
Inputs connected to - PA0-PA7, PC4-PC7

Outputs connected to - PB0-PB7, PC0-PC3

BITS Pilani, Pilani Campus

 8255 – Programmable
Peripheral Interface (PPI)
BITS Pilani
Pilani Campus
 Input a data from a matrix keyboard
 Output data on seven-segment- display

f b
g

e c
h

BITS Pilani, Pilani Campus

 Column I/ps
D0 – D7 PC0 – PC3

A0
System PC4 – PC7 Row O/ps
A1
I/f
RD
8255
WR

CS
PB0 – PB7 7407
RESET (02 no)
Hex buffer

Current
limiting
resistors Vcc
Key Debounce
 When a mechanical key is pressed or released- the metallic
contacts bounce before they make steady state contact
 Bouncing is noise and should not be treated as i/p

 Debounce RC-debouncer

 s/w – using software delay of 10-20 ms

 h/w –dedicated hardware device

7414 – hex inverter with

Schmitt trigger inputs

BITS Pilani, Pilani Campus

 keyboard
Output zero to
one column
Zero to all
X0
columns
Read
Read rows

X1 rows
encode
NO
NO All Keys Key found?
Open ?
yes
yes
Read Convert
X3
rows to hex
detect
NO return
Key pressed ?
X2
yes
Wait 20 De-bounce
ms

Read rows

NO
Key pressed ?

yes
 E.g. Mode 0 – Keypad I/f
5V
0 1 2 3
1
O0
4 5 6 7
0
1
O1
8255 I/P port 8 9 A B
Pc4 – Pc7 1
O2
C D E F
O3 1
8255 O/P port
Pc0 – Pc3

I0

I1
I2
I3
Key O3 O2 O1 O0 I3 I2 I1 I0 HEX
0 1 1 1 0 1 1 1 0 EE
1 1 1 1 0 1 1 0 1 ED
2 1 1 1 0 1 0 1 1 EB
3 1 1 1 0 0 1 1 1 E7
4 1 1 0 1 1 1 1 0 DE
5 1 1 0 1 1 1 0 1 DD
6 1 1 0 1 1 0 1 1 DB
7 1 1 0 1 0 1 1 1 D7
8 1 0 1 1 1 1 1 0 BE
9 1 0 1 1 1 1 0 1 BD
A 1 0 1 1 1 0 1 1 BB
B 1 0 1 1 0 1 1 1 B7
C 0 1 1 1 1 1 1 0 7E
D 0 1 1 1 1 1 0 1 7D
E 0 1 1 1 1 0 1 1 7B
F 0 1 1 1 0 1 1 1 77

BITS Pilani, Pilani Campus

 8255 – Programmable
Peripheral Interface (PPI)
BITS Pilani
Prof. Meetha V Shenoy
Pilani Campus
 Input a data from a matrix keyboard
 Output data on seven-segment- display

f b
g

e c
h

BITS Pilani, Pilani Campus

Key O3 O2 O1 O0 I3 I2 I1 I0 HEX
0 1 1 1 0 1 1 1 0 EE
1 1 1 1 0 1 1 0 1 ED
2 1 1 1 0 1 0 1 1 EB
3 1 1 1 0 0 1 1 1 E7
4 1 1 0 1 1 1 1 0 DE
5 1 1 0 1 1 1 0 1 DD
6 1 1 0 1 1 0 1 1 DB
7 1 1 0 1 0 1 1 1 D7
8 1 0 1 1 1 1 1 0 BE
9 1 0 1 1 1 1 0 1 BD
A 1 0 1 1 1 0 1 1 BB
B 1 0 1 1 0 1 1 1 B7
C 0 1 1 1 1 1 1 0 7E
D 0 1 1 1 1 1 0 1 7D
E 0 1 1 1 1 0 1 1 7B
F 0 1 1 1 0 1 1 1 77

BITS Pilani, Pilani Campus

 Key Debounce

 When a mechanical key is pressed or released- the metallic

contacts bounce before they make steady state contact
 Bouncing is noise and should not be treated as i/p

 Debounce
 s/w – using software delay of 10-20 ms

BITS Pilani, Pilani Campus

 keyboard
Output zero to
one column
Zero to all
X0
columns
Read
Read rows

X1 rows
encode
NO
NO All Keys Key found?
Open ?
yes
yes
Read Convert
X3
rows to hex
detect
NO return
Key pressed ?
X2
yes
Wait 20 De-bounce
ms

Read rows

NO
Key pressed ?

yes
 Column I/ps
D0 – D7 PC0 – PC3

A0
System PC4 – PC7 Row O/ps
A1
I/f
RD
8255
WR

CS
PB0 – PB7 7407
RESET (02 no)
Hex buffer

Current
limiting
resistors Vcc
.Model Tiny

.DATA

TABLE_D DB 3FH, 06H, 5BH, 4FH, 66H, 6DH ;Common cathode display codes

DB 7DH, 07H, 7FH, 67H, 77H, 7CH,

DB 39H, 5EH, 79H, 71H

TABLE_K DB EEH,, EDH, EBH, E7H, DEH, DDH, ;Keyboard key-press codes

DB DBH, D7H, BEH, BDH, BBH, B7H

DB 7EH, 7DH, 7BH, 77H,

BITS Pilani, Pilani Campus

.Model Tiny

.DATA

TABLE_D DB 3FH, 06H, 5BH, 4FH, 66H, 6DH ;Common cathode display codes

DB 7DH, 07H, 7FH, 67H, 77H, 7CH,

DB 39H, 5EH, 79H, 71H

TABLE_K DB EEH,, EDH, EBH, E7H, DEH, DDH, ;Keyboard key-press codes

DB DBH, D7H, BEH, BDH, BBH, B7H

DB 7EH, 7DH, 7BH, 77H,

BITS Pilani, Pilani Campus

Key O3 O2 O1 O0 I3 I2 I1 I0 HEX
0 1 1 1 0 1 1 1 0 EE
1 1 1 1 0 1 1 0 1 ED
2 1 1 1 0 1 0 1 1 EB
3 1 1 1 0 0 1 1 1 E7
4 1 1 0 1 1 1 1 0 DE
5 1 1 0 1 1 1 0 1 DD
6 1 1 0 1 1 0 1 1 DB
7 1 1 0 1 0 1 1 1 D7
8 1 0 1 1 1 1 1 0 BE
9 1 0 1 1 1 1 0 1 BD
A 1 0 1 1 1 0 1 1 BB
B 1 0 1 1 0 1 1 1 B7
C 0 1 1 1 1 1 1 0 7E
D 0 1 1 1 1 1 0 1 7D
E 0 1 1 1 1 0 1 1 7B
F 0 1 1 1 0 1 1 1 77

BITS Pilani, Pilani Campus

.CODE
.STARTUP
MOV AL,10011000B
Initialize
OUT 06H,AL 8255
X
0
:

X
1
:
.CODE
.STARTUP
MOV AL,10011000B
Initialize
OUT 06H,AL 8255
X0: MOV AL,00H
OUT 04H,AL
X1: IN AL, 04H Check for key
release
AND AL,F0H
CMP AL,F0H
JNZ X1
 MOV AL,00H
OUT 04H ,AL
X2: IN AL, 04H Check for
AND AL,F0H Key press
CMP AL,F0H
JZ X2
Debounce
CALL DELAY_20ms time
MOV AL,00H
OUT 04H ,AL
IN AL, 04H Check for
AND AL,F0H Key press
CMP AL,F0H
JZ X2
MOV AL, 0EH
MOV BL,AL
OUT 04H,AL Check for
IN AL,04H
Key press
AND AL,F0H
CMP AL,F0H Column1
JNZ X3
MOV AL, 0DH
MOV BL,AL
OUT 04H ,AL Check for
IN AL,04H
AND AL,F0H Key press
CMP AL,F0H Column2
JNZ X3
MOV AL, 0BH
MOV BL,AL
OUT 04H,AL Check for
IN AL,04H
Key press
AND AL,F0H
CMP AL,F0H Column3
JNZ X3
MOV AL, 07H
MOV BL,AL
OUT 04H,AL Check for
IN AL,04H
AND AL,F0H Key press
CMP AL,F0H Column4
JZ X2
X3: OR AL,BL
MOV CX,0FH
MOV DI,00H Decode
X4: CMP AL,TABLE_K[DI]
JZ X5 key
INC DI
LOOP X4
X5: MOV AX,DI
LEA BX, TABLE_D Display
XLAT
OUT 02H,AL
JMP X0
.EXIT
END
The XLAT instruction replaces the value in
AL with the value found at DS:[BX + AL]
 Column I/ps
D0 – D7 PC0 – PC3

A0
System PC4 – PC7 Row O/ps
A1
I/f
RD
8255
WR

CS
PB0 – PB7 7407
RESET (02 no)
Hex buffer

Current
limiting
resistors Vcc
 BITS Pilani

Interrupt Handling
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3 BITS Pilani
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
10 31
AD6
11
8086 HOLD
HLDA
RQ/GT0
AD5 30 RQ/GT1
AD4 12 29 WR LOCK
AD3 13 28 M/IO S2
AD2 14 27 DT/R S1
AD1 15 26 DEN S0
AD0 16 25 ALE QS0
NMI 17 24 INTA QS1
INTR 18 23 TEST
19 22 READY
CLK
GND 20 21 RESET
8086 Interrupt sources
BITS Pilani

Hardware Interrupt
External input applied at non-maskable interrupt NMI
External input applied at maskable interrupt INTR

Flag Register x86

If I=1, the INTR pin is enabled STI

If I=0, the INTR pin is disabled CLI
8086 Interrupt sources
BITS Pilani

Software Interrupt
Execution of INT instruction
Exception in program execution
Trap

Flag Register x86

Interrupt Handling in Real Mode
BITS Pilani

How to handle an Interrupt?

Execute Interrupt Service Routine/Handler (ISR)
Before execution of ISR, Save the state of processor so that after the execution of ISR, the normal
instruction execution can be resumed

Where is ISR stored?

Interrupt vectors are used to find the starting address of ISR.
Interrupt vectors are stored in Interrupt Vector Tables (IVT)- Starting from 00000H
Each vector (4 byte value) contains a value for IP and CS that forms the address of the interrupt
service procedure.
The first 2 bytes contain the IP, and the last 2 bytes contain the CS.
8086 supports 256 interrupt types (INT 00H- INT FFH )
In 80x86 - the memory location from which an interrupt fetches the vector is 4 times the
value of the interrupt type number
IVT Size 00000H–003FFH (1024 bytes)
Interrupt Vector Table IVT

BITS Pilani

Int Vector No. Physical Address Contains

INT 00H 00000H IP0
00002H CS0
INT 01H 00004H IP1
00006H CS1
INT 02H 00008H IP2
0000AH CS2
…………….

INT FFH 003FCH IP255

003FEH CS255
ISR Handling in Real Mode
BITS Pilani

The contents of the flag register are pushed onto the stack.
Both the interrupt (IF) and trap (TF) flags are cleared. This disables the INTR pin and the
trap or single-step feature.
The contents of the code segment register (CS) are pushed onto the stack.
The contents of the instruction pointer (IP) are pushed onto the stack.
The interrupt vector contents are fetched, and then placed into both IP and CS so that the
next instruction executes at the interrupt service procedure addressed by the vector.
Eg: INT 4H, CS:1P- 0100:0400, Flag: 0080

BITS Pilani

SP-6 00

SP-5 04

SP-4 00

SP-3 01

SP-2 80

SP-1 00

Address of IVT- 16d= 10H

0010 00
IP
0011 08

0012 00

0013 02 SEG

0200:0800
 BITS Pilani

Interrupt Handling
ISR Handling in Real Mode
BITS Pilani

The contents of the flag register are pushed onto the stack.
Both the interrupt (IF) and trap (TF) flags are cleared. This disables the INTR pin and the
trap or single-step feature.
The contents of the code segment register (CS) are pushed onto the stack.
The contents of the instruction pointer (IP) are pushed onto the stack.
The interrupt vector contents are fetched, and then placed into both IP and CS so that the
next instruction executes at the interrupt service procedure addressed by the vector.
Interrupts - 8086
BITS Pilani

Interrupt Type 0 –INT 0

▪ Divide by zero interrupt

▪ If the quotient is too large to fit into AL/AX

▪ Divide by zero is attempted

▪Automatically invoked by the processor on Error

Interrupts - 8086
BITS Pilani

Interrupt Type 1 – INT 1

▪ Single step Interrupt

▪ If trap flag is set 80X86 will do a type 1 interrupt after every instruction execution

▪ Automatically invoked by the processor if TF-1

Enable Trace/ Single Step
BITS Pilani

PUSHF

PUSH AX

MOV BP,SP
MOV AX,[BP+2]
OR AX, 0000000100000000H

MOV [BP+2],AX

POP AX

POPF

Flag Register x86

Interrupts- 8086
BITS Pilani

Interrupt Type 2 – INT 2

When 8086 receives a low to high transition on its NMI input

Type 2 interrupt response cannot be disabled (masked) by any program instruction

Interrupts - 8086
BITS Pilani

Break Point Interrupt – Type 3

▪ INT 3 instruction – to implement breakpoint routines

▪ The system execute instruction up to break point and then goes to break point routine debugging

▪ Triggered by INT 3 instruction – to implement breakpoint routines

Overflow Interrupt – Type 4

▪ INTO

▪ Invoking an interrupt after overflow in an arithmetic operation

▪ If no overflow it will be a NOP instruction

▪ Interrupt is conditional – will be serviced only if there is an overflow error

MOV AL, 127 ;

ADD AL, 1 ;
INTO ; Will trigger INT 4 if OF is set
Interrupts - 8086
BITS Pilani

8086 INTR input (Level triggered)

Allows some external signal to interrupt execution of a program
INTR can be masked ( disabled)
Clearing IF flag disables INTR

CLI - clears IF
STI - sets IF flag

8086 when reset, IF = 0

When 8086 branches to ISR, IF -0
IRET – IF -1
Interrupts - 8086
BITS Pilani

 In response to INTR 8086 expects a vector number

 It enters to INTA machine cycle to

 Acknowledge the interrupting device.

 Get the interrupt vector (if needed), so it knows which interrupt service routine (ISR) to
execute.
 BITS Pilani

D0 Tri –State Buffer to generate Vector

No.
D1
D2
D3
D4
D5
D6
D7
O7 O6 O5 O4 O3 O2 O1 O0
vCC
LS 244
I7 I7 I6 I6 I5 I5 I4 I4 I3 I3 I2 I2 I1 I1 I0 I0 G1’ G21’’
G
INTA’ G’