Scribd
Upload
15 views

Computer Architecture Answers

The document provides an answer key for questions related to computer organization and architecture, covering topics such as floating-point representation, addressing modes, micro-operations, BCD addition, restoring division, memory hierarchy, and types of memory. It details various concepts including single and double precision formats, different addressing modes, and the functioning of micro-programmed and hardwired control units. Additionally, it discusses memory systems, asynchronous transfer, and DMA control lines.

Uploaded by

sv84826
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
15 views

Computer Architecture Answers

The document provides an answer key for questions related to computer organization and architecture, covering topics such as floating-point representation, addressing modes, micro-operations, BCD addition, restoring division, memory hierarchy, and types of memory. It details various concepts including single and double precision formats, different addressing modes, and the functioning of micro-programmed and hardwired control units. Additionally, it discusses memory systems, asynchronous transfer, and DMA control lines.

Uploaded by

sv84826
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

Computer Organization and Architecture - Answer Key

Q2. Attempt any Two parts of the following.

(a) Floating-point representation (IEEE 754 standard)...

Single Precision (32-bit):

1 bit for sign (S), 8 bits for exponent (E), 23 bits for mantissa (M)

Formula: Value = (-1)^S x 1.M x 2^(E - 127)

Double Precision (64-bit):

1 bit for sign, 11 bits for exponent, 52 bits for mantissa

Formula: Value = (-1)^S x 1.M x 2^(E - 1023)

Range:

Single precision: ±3.4x10^38 (overflow), ±1.4x10^-45 (underflow)

Double precision: ±1.8x10^308 (overflow), ±4.9x10^-324 (underflow)

(b) Addressing Modes:

Immediate: Operand part of instruction (MOV R1, #5)

Register: Operand in register (ADD R1, R2)

Direct: Address is in instruction (MOV R1, [1000])

Register Indirect: Address in register (MOV R1, [R2])

Indexed: Effective address = base + index (MOV R1, [R2 + R3])

(c) Micro-operations for ADD R1, M[R2]:

1. MAR <- R2

2. MBR <- Memory[MAR]

3. TEMP <- MBR

4. R1 <- R1 + TEMP

Functional Units: Registers, ALU, Control Unit, MAR, MBR, Memory

Q3. Attempt any Two parts of the following.

(a) BCD Addition:

Each digit uses 4 bits. If result > 9, add 0110.

Example: 9(1001) + 5(0101) = 1110 -> +0110 = 1 0100


Computer Organization and Architecture - Answer Key

Output bits: Carry, S3, S2, S1, S0 = 1 0100

(b) Restoring Division:

Steps: A = 0, shift (A,Q), A = A - M, restore if A < 0

Example: 7 ÷ 3 (0111 ÷ 0011)

Circuit: Registers (A, Q, M), Subtractor, Shifter, Control Logic

(c) 8x8 Pipeline Multiplier:

Stage 1: Generate partial products

Stage 2-3: Use CSA tree to reduce

Stage 4: Final sum with CLA

Components: PPG, CSA, CLA

Q4. Attempt any Two parts of the following.

(a) Memory Hierarchy:

Registers -> Cache -> Main Memory -> Secondary -> Tertiary

Faster memories are costlier and closer to CPU

(b) SRAM vs DRAM:

SRAM: Faster, uses flip-flops, costly, no refresh

DRAM: Slower, uses capacitors, cheaper, needs refresh

(c) 16-word Memory using 4x4 chips:

4 chips needed. Use 2-to-4 decoder for chip select (A3-A2)

Internal address: A1-A0 for word selection

Q5. Attempt any Two parts of the following.

(a) Micro-programmed Control Unit:

Control Memory, CAR, CDR, Sequencer, Decoder

Steps: Fetch, Decode, Execute, Next Address


Computer Organization and Architecture - Answer Key

(b) Hardwired vs Microprogrammed:

Hardwired: Fast, complex, hard to change

Microprogrammed: Slower, flexible, easier to modify

(c) Micro-program for LDA:

T0: MAR <- PC

T1: MBR <- Memory[MAR], PC <- PC + 1

T2: IR <- MBR

T3: MAR <- IR(address)

T4: MBR <- Memory[MAR]

T5: AC <- MBR

Q6. Attempt any Two parts of the following.

(a) Memory System:

Components: CPU, Address/Data/Control Buses, MMU, Memory Modules

Mapping: Direct, Associative, Set-Associative

(b) Asynchronous Transfer:

Uses Request (REQ) and Acknowledge (ACK)

Handshaking protocol, timing diagram shows signal transitions

(c) DMA Control Lines:

DREQ, DACK, Read/Write, Address/Data, Bus Control

Comparison:

- Programmed I/O: CPU handles transfer

- Interrupt I/O: CPU interrupted

- DMA: Direct memory access without CPU

You might also like