5/6/2017

UNIT 7
COMPUTER ARITHMETIC

CO(2140707) Prepared By: Prof. Chirag Bhalodia

Outline
• Introduction
• Addition and subtraction
• Multiplication Algorithms (Booth Multiplication
Algorithm)
• Division Algorithms
• Floating Point Arithmetic operations
• Decimal Arithmetic Unit

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Introduction

• Based on the number system two basic data types are implemented
in the computer system: fixed point number and floating point
number.

• Representing numbers in such data types is commonly known as

fixed point representation and floating point representation,
respectively.

• In binary number system, a number can be represented as an

integer or fraction.

• Depending on the design, the hardware can interpret number as an

integer or fraction.

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• In integer numbers, radix point is fixed and assumed to be to the

right of the right most digit.

• As radix point is fixed, the number system is referred to as fixed

point number system.

• With fixed point number we can represent positive or negative

integer numbers.

• Floating point number system allows the representation of

numbers having both integer and fraction part.

GTU Questions
1. Explain addition and subtraction operations with signed 2’s
complement integer data. Support your answer by taking
appropriate example(s).

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Addition and
substraction

• There are 3 ways of representing negative fixed point binary

numbers: signed-magnitude, signed 1’s complement, or signed-2’s
complement.

• Most computers use the signed-2’s complement representation

when performing arithmetic operations with integers.

• For floating-point operations, most computer use the signed-

magnitude representation for the mantissa.

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Addition and Subtraction with Signed-magnitude Data

• The flowchart is shown in Figure. The two signs A, and B, are
compared by an exclusive-OR gate.
– If the output of the gate is 0 the signs are identical;
– If it is 1, the signs are different.

• For an add operation, identical signs dictate that the magnitudes be

added. For a subtract operation, different signs dictate that the
magnitudes be added.

• The magnitudes are added with a micro-operation EAA + B,

where EA is a register that combines E and A. The carry in E after
the addition constitutes an overflow if it is equal to 1. The value of
E is transferred into the add-overflow flip-flop AVF.

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Addition and Subtraction with Signed-magnitude Data

• The two magnitudes are subtracted if the signs are different for an add
operation or identical for a subtract operation. The magnitudes are
subtracted by adding A to the 2's complemented B. No overflow can
occur if the numbers are subtracted so AVF is cleared to 0.

• 1 in E indicates that A >= B and the number in A is the correct result. If

this numbs is zero, the sign A must be made positive to avoid a negative
zero.

• 0 in E indicates that A < B. For this case it is necessary to take the 2's
complement of the value in A. The operation can be done with one
micro-operation A A' +1.

• However, we assume that the A register has circuits for micro-operations

complement and increment, so the 2's complement is obtained from
these two micro-operations.

Addition and Subtraction with Signed-magnitude Data

• In other paths of the flowchart, the sign of the result is the same as
the sign of A. So no change in A is required. However, when A <
B, the sign of the result is the complement of the original sign of
A. It is then necessary to complement A, to obtain the correct sign.

• The final result is found in register A and its sign in As. The value
in AVF provides an overflow indication. The final value of E is
immaterial.

• Figure shows a block diagram of the hardware for implementing

the addition and subtraction operations.

• It consists of registers A and B and sign flip-flops As and Bs.

• Subtraction is done by adding A to the 2's complement of B.

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Addition and Subtraction with Signed-magnitude Data

Fig : Hardware for signed magnitude addition and subtraction

Addition and Subtraction with Signed-magnitude Data

• The output carry is transferred to flip-flop E , where it can be
checked to determine the relative magnitudes of two numbers.

• The add-overflow flip-flop AVF holds the overflow bit when A

and B are added.

• The A register provides other micro operations that may be needed

when we specify the sequence of steps in the algorithm.

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GTU Questions

1. Draw and explain flowchart for addition and subtraction

operations with sign-magnitude data. (June-16)

Booth Multiplication
Algorithm

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Booth’s Algorithm
• Booth algorithm gives a procedure for multiplying binary integers
in signed- 2’s complement representation.

• It operates on the fact that strings of 0’s in the multiplier require

no addition but just shifting, and a string of 1’s in the multiplier
from bit weight 2k to weight 2m can be treated as 2k+1 – 2m.

• For example, the binary number 001110 (+14) has a string 1’s
from 23 to 21 (k=3, m=1).

• The number can be represented as 2k+1 – 2m. = 24 – 21 = 16 – 2 =

14. Therefore, the multiplication M X 14, where M is the
multiplicand and 14 the multiplier, can be done as M X 24 – M X
21.

Booth’s Algorithm

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Booth’s Algorithm
• Thus the product can be obtained by shifting the binary multiplicand
M four times to the left and subtracting M shifted left once.

• As in all multiplication schemes, booth algorithm requires

examination of the multiplier bits and shifting of partial product.

• Prior to the shifting, the multiplicand may be added to the partial

product, subtracted from the partial, or left unchanged according to
the following rules:
– The multiplicand is subtracted from the partial product upon encountering the
first least significant 1 in a string of 1’s in the multiplier.
– The multiplicand is added to the partial product upon encountering the first 0 in
a string of 0’s in the multiplier.
– The partial product does not change when multiplier bit is identical to the
previous multiplier bit.

Booth’s Algorithm
• The algorithm works for positive or negative multipliers in 2’s
complement representation.

• This is because a negative multiplier ends with a string of 1’s

and the last operation will be a subtraction of the appropriate
weight.

• The two bits of the multiplier in Qn and Qn+1 are inspected.

• If the two bits are equal to 10, it means that the first 1 in a
string of 1 's has been encountered. This requires a subtraction
of the multiplicand from the partial product in AC.

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Booth’s Algorithm
• If the two bits are equal to 01, it means that the first 0 in a
string of 0's has been encountered. This requires the addition of
the multiplicand to the partial product in AC.

• When the two bits are equal, the partial product does not
change.

Exercise: Multiply the (7) with (3) using Booth’s algorithm. Give
each step.

Answer: 7 X 3 =21 => 00010101

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• Exercise: Multiply the (15) with (13) using Booth’s algorithm.

Give each step.

• Exercise: Multiply the (15) with (13) using Booth’s algorithm.

Give each step.

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• Exercise: Multiply the (15) with (-13) using Booth’s algorithm.

Give each step.

• Exercise: Multiply the (15) with (-13) using Booth’s algorithm.

Give each step.

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• Exercise: Multiply the (-9) with (-13) using Booth’s algorithm.

Give each step.

• Exercise: Multiply the (-9) with (-13) using Booth’s algorithm.

Give each step.

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• Exercise: Multiply the (-9) with (-13) using Booth’s algorithm.

Give each step.

GTU Questions

1. Assume A = (+8) and B = (+5). Multiply these two numbers

using Booth algorithm. Show the step-by-step multiplication
process. (June-16)

2. Explain booth algorithm for multiplication with a flowchart.

(May-14, Dec-14, Dec-15)

3. Multiply the (-9) with (-13) using Booth’s algorithm. Give each
step. (May-14)

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Division Algorithm

• The division process for binary numbers is similar to the decimal

numbers. The diagram shows binary division process.

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• In this division process, first the bits of the dividend are examined
from left to right, until the set of bits examined represents a
number greater then or equal to the divisor.

• Until the condition occurs, 0’s are placed in the quotient from left
to right.

• When the condition is satisfied, a 1 is placed in the quotient and

the divisor is subtracted from the partial dividend. The result is
referred to as a partial reminder.

• From this point onwards, the division process is required. In each

repetition cycle, additional bits from the dividend are brought
down to the partial remainder until the result is greater than or
equal to the divisor and the divisor is subtracted from the result to
produce a new partial remainder.

• The process continues until all bits of the dividend are brought
down and result is still less than the divisor.

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Restoring division algorithm

• Division operation steps:
1. Shift A and Q left one binary position.

2. Subtract divisor (i.e. Add 2’s complement of divisor (B)) from

A and place answer back in A (A A-B).

3. If the sign bit of A is 1, set Q0 to 0 and add divisor back to A

(that is, restore A); Otherwise, set Q0 to 1.

4. Repeat steps 1,2, and 3...n times.

• A flowchart for division operation is as shown in figure.

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Floating Point
Arithmetic Operation

Floating point multiplication

• The multiplication of two floating-point numbers requires that we
multiply the mantissas and add the exponents.

• No comparison of exponents or alignment of mantissas is

necessary.

• The multiplication of the mantissas is performed in the same way

as in fixed-point to provide a double-precision product.

• The double-precision answer is used in fixed-point numbers to

increase the accuracy of the product.

• In floating-point, the range of a single-precision mantissa

combined with the exponent is usually accurate enough so that
only single-precision numbers are maintained.

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• Rules of multiplication algorithm:

1. If either 0, report 0 as result.
2. Add the exponents and subtract bias. (single precision=127 and
double precision=1023)
3. Multiply the mantissas and determine the sign of the result.
4. Normalize the result.

• The flowchart for floating-point multiplication is shown in Figure.

The two operands are checked to determine if they contain a zero.

• If either operand is equal to zero, the product in the AC is set to

zero and the operation is terminated.

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• If neither of the operands is equal to zero, the process continues with the
exponent addition.

• The exponent of the multiplier is in q and the adder is between

exponents a and b.

• It is necessary to transfer the exponents from q to a, add the two

exponents, and transfer the sum into a.

• Since both exponents are biased by the addition of a constant, the

exponent sum will have double this bias.

• The correct biased exponent for the product is obtained by subtracting

the bias number from the sum.

• The multiplication of the mantissas is done as in the fixed-point case

with the product residing in A and Q.

• The correct biased exponent for the product is obtained by

subtracting the bias number from the sum.

• Overflow cannot occur during multiplication, so there is no need

to check for it.

• The product may have an underflow, so the most significant bit in

A is checked. If it is a 1, the product is already normalized.

• If it is a 0, the mantissa in AQ is shifted left and the exponent

decremented.

• Note that only one normalization shift is necessary. The multiplier

and multiplicand were originally normalized and contained
fractions. The smallest normalized operand is 0.1, so the smallest
possible product is 0.01.

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• Therefore, only one leading zero may occur.

• Although the low-order half of the mantissa is in Q, we do not use

it for the floating point product. Only the value in the AC is taken
as the product.

Floating point Division

• Rules of division algorithm:
1. Checks for zeros
2. Initialize registers and evaluate the sign
3. Align the dividend
4. Subtract the exponent
5. Divide the mantissa

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GTU Questions
1. Develop an algorithm for multiplication of two binary numbers,
which are stored as per floating point representation. (June-15,
Dec-16)

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Decimal Arithmetic
Unit

BCD Adder
• BCD representation is a class of binary encodings of decimal
numbers where each decimal digit is represented by a fixed
number of bits.

• BCD adder is a circuit that adds two BCD digits in parallel and
produces a sum digit in BCD form.

• Since each input digit does not exceed 9, the output sum cannot be
greater than 19(9+9+1). For example: suppose we apply two BCD
digits to 4-bit binary adder.

• The adder will form the sum in binary and produce a result that
may range from 0 to 19.

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BCD Adder

BCD Adder

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BCD Adder
• In following figure, these binary numbers are represented by K,
Z8, Z4, Z2, and Z1.

• K is the carry and subscripts under the Z represent the weights 8,

4, 2, and 1 that can be assigned to the four bits in the BCD code.

• When binary sum is equal to or less than or equal to 9,

corresponding BCD number is identical and therefore no
conversion is needed.

• The condition for correction and output carry can be expressed by

the Boolean function:
C= K + Z8Z4 + Z8Z2
• When it is greater than 9, we obtain non valid BCD representation,
then additional binary 6 to binary sum converts it to correct BCD
representation.

BCD Adder
• The two decimal digits, together with the input-carry, are first
added in the top 4-bit binary adder to produce the binary sum.
When the output-carry is equal to 0, nothing is added to the binary
sum.

• When C is equal to 1, binary 0110 is added to the binary sum

using bottom 4-bit binary adder. The output carry generated from
the bottom binary-adder may be ignored.

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GTU Questions
1. Draw the block diagram for BCD adder and explain it. (Dec-14)

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