2.

Background on Reversible Logic

This section introduces basics of reversible logic including different types of reversible gates
like Toffoli gate, Freedkin gate, Swap gate, Peres gate and its diagram truth table and unitary
matrix, circuits and cost constraints.
2.6.1 Logic Function
In classical computing, logic operations are defined as functions over Boolean variables B ϵ
{0, 1}.
Definition 2.1: A multi-output Boolean function is a mapping f : Bn → Bm, where B = {0,
1} is a Boolean domain and n, m ϵ N. In fact, it is a system of m Boolean functions fi ( x1,
x2,....... xn ), where 1 ≤ i ≤ m.
Such function can be expressed in terms of logical operations which are AND, OR, NOT,
NAND, NOR, exclusive-OR (EXOR), and exclusive-NOR (EXNOR) operations. A logic
gate implements a logical operation. In traditional irreversible logic, AND, OR, NOT,
NAND, NOR, EXOR, and EXNOR gates are used as standard gates. Among all the logic
gates, only NAND and NOR gates are universal since NAND gates alone (or alternatively
NOR gates alone) can be used to implement any logic function. A circuit which is an
electronic representation of a function is made from gates by interconnecting the outputs of
some gates to the inputs of others. Logic synthesis is the process of transforming a logic
function into a circuit design in terms of gates. The resultant circuit is called a realization of
the given function.
Example 2.1: Table 2.1 shows the truth table of the 3-input, 2-output Full Adder function.

Table 2.1: The irreversible full Adder function.

Reversible computation deals with any computational process that is time-invertible, meaning
that the process can also be computed backwards to construct inputs from their corresponding
outputs and thus no information is lost during a reversible computation. The Full Adder
function in Table 2.1 is irreversible in that it is not always possible to obtain a unique input
pattern by knowing the output pattern.
2.6.2 Reversible Function

Boolean reversible functions are a subset of Boolean logic functions with certain conditions.

Definition 2.2 : Let A be any set and defined f : A → A as a one-to-one and surjective
function. The function f is called a permutation function if applying f to A leads to a set
with the same elements as A and possibly in a different order. For example, if A = {1, 2,
3,....m } for any ai ϵ A there exists a unique aj ϵ A such that f(ai) = aj .

Definition 2.3 : An n-input, n-output fully specified Boolean function f : Bn → Bn is called

reversible if it is a permutation function.

A function is reversible if it is bijective (i.e., one-to-one and onto) . In other words, a

reversible function has the same number of inputs as outputs and there is a one-to-one
mapping between its input and output vectors. A reversible gate realizes a reversible function.
An irreversible function can be embedded into a reversible function by adding extra
inputs/outputs and assigning values to the generated don't-cares to create a permutation
function.

Example 2.2: In the Full Adder function of Table 2.1, the maximum number of times that an
output pattern is repeated is 3 (for output patterns 10 and 01). Hence, at least Γlog2(3)˥, = 2
garbage outputs and one constant input are required to make the Full Adder function
reversible. Table 2.2 shows a reversible form of the Full Adder function where go1 and go2
are the garbage outputs and gi is the constant input. Note that assigning 0 to gi leads to
obtaining outputs cout and sum, but the don't-cares are assigned in the way that assigning 1 to
gi inverts the cout output.
 Table 2.2: A reversible Full Adder

There is more than one reversible function associated with each irreversible function
depending on the number of constant inputs and garbage outputs used and don't care
assignments. The circuits that result from synthesizing these embedded reversible functions
are different in terms of the number of gates and the number of qubits and hence have
different implementation costs. Consequently, the process of embedding an irreversible
function into a reversible function is of significant importance and has remained an open
problem while being studied in many articles [96-99].

2.6.3 Reversible Gates and Unitary Matrix

A logic gate is reversible if the mapping of inputs to outputs is bijective, that is, every distinct
input yields a distinct output, and the number of output bits is equal to that of input ones and
realizes a reversible function.A reversible gate with k input bits and k output bits is called a k
× k reversible gate. A different set of reversible logic gates are used to build reversible
circuits since traditional logic gates other than the NOT gate are not applicable in reversible
logic. A reversible gate with n inputs and n outputs in an r-valued logic is represented by an
rn x rn unitary matrix.

Definition 2.5. Operator U is called unitary iff UU = I which means that the result of the
product of U and its adjoint (complex conjugate transpose) is the identity matrix [13].

2.6.3.1 The NOT Gate

A NOT gate is a 1x1 gate represented as shown in Figure. 2.7 (a). It inverts the input. Since
it is a 1x1 gate.

Input Output
A P=A x x/ Output
0 1

Input
0 1 0 0 1
1 1 0
(a) (b) 1 0 (c)
Figure 2.7 : (a) NOT gate (b) Truth Table of NOT gate (c) Unitary Matrix of NOT gate
2.6.3.2 The Controlled-V and Controlled-V+ Gates

The controlled-V gate is shown in Figure. 2.8 (a). In the controlled-V gate, when the control
signal A=0 then the qubit B will pass through the controlled part unchanged, i.e., we will
1 -i
have Q=B. When A=1 then the unitary operation V = i+1/2( ) is -iapplied
1
to the input B,
i.e., Q=V(B). The controlled-V + gate is shown in Figure. 2.8 (b). In the controlled-V + gate
when the control signal A=0 then the qubit B will pass through the controlled part
unchanged, i.e., we will have Q=B. When A=1 then the unitary operation V + = V −1 is
applied to the input B, i.e., Q=V +(B).
The V and V + quantum gates have the following properties:
V × V = NOT
V×V+=V+×V=I
V + × V + = NOT
The properties above show that when two V gates are in series they will behave as a NOT
gate. Similarly, two V + gates in series also function as a NOT gate. A V gate in series with V
+ gate, and vice versa, is an identity. For more details of the V and V + gates, the reader is
referred to [126], [104],[107].

A P=A A P=A

B V Q=If (A) then B V+ Q=If (A) then

V(B) Else B V+(B) Else B

(a) (b)

Figure 2.8 : (a) Controlled-V gate (b) Controlled-V + gate

2.6.3.3 The Feynman Gate (CNOT Gate)

The Feynman gate (FG) or the Controlled-NOT gate (CNOT) is a 2 inputs 2 outputs
reversible gate having the mapping (A, B) to (P=A, Q=A⊕B) where A, B are the inputs and
P, Q are the outputs, respectively. Figure 2.9 (a) and 2.9(b) show the block diagrams and
Graphical notation of the Feynman gate. The Feynman gate can be used for copying the
signal thus avoiding the fan-out problem in reversible logic. The truth table and unitary
matrix are shown in Fig.2.9(c) and Fig.2.9(d).

A P=A
A P=A

CNOT
B Q= A⊕
⊕B B Q=A ⊕ B

(a) CNOT Gate (b) Graphical notation

Input Output
A B P Q
0 0 0 0
0 1 0 1
1 0 1 1
1 1 1 0

(c) Truth Table of CNOT gate (d) Unitary Matrix of CNOT gate

Figure 2.9 : (a) CNOT Gate (b) Graphical notation (c) Truth Table of CNOT gate (d) Unitary
Matrix of Toffoli gate
2.6.3.4 The Toffoli Gate

The Toffoli Gate (TG) (also called 2-CNOT) is a 3x3 two-through reversible gate as shown in
Figure 2.10 (a). It has two control lines and a target line. Two through means two of its
outputs are the same as the inputs with the mapping (A, B, C) to (P=A,Q=B, R=A.B⊕C),
where A, B, C are inputs and P, Q, R are outputs, respectively i.e. the control inputs passes
through and the target output is inverted if both the control lines are 1, else remain
unchanged[100].
A P=A

B TG Q= B

C R=A.B⊕
⊕C

(a)
Input Output
A P=A A B C P Q R
0 0 0 0 0 0
0 0 1 0 0 1
B Q=B 0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
C R=A.B⊕
⊕C 1 0 1 1 0 1
1 1 0 1 1 1
(b) 1 1 1 1 1 0
(c)
Output
000 001 010 011 100 101 110 111
000 1 (e)
0 Unitary
0 matrix
0 of Toffoli
0 0gate 0 0
001 0 1 0 0 0 0 0 0
010 0 0 1 0 0 0 0 0
Input

011 0 0 0 1 0 0 0 0
100 0 0 0 0 1 0 0 0
101 0 0 0 0 0 1 0 0
110 0 0 0 0 0 0 0 1
111 0 0 0 0 0 0 1 0
(d)

Figure. 2.10 : (a) Toffoli gate (b) Graphical notation (c)Truth Table (d) Unitary matrix of
Toffoli gate
2.6.3.5 The Peres Gate

The Peres gate is a 3 inputs 3 outputs (3x3) reversible gate having the mapping (A, B, C) to
(P=A, Q=A⊕B, R= A.B⊕C), where A, B, C are the inputs and P, Q, R are the outputs,
respectively [104]. Figure 2.11 (a) shows the Peres gate and Fig. 2.10 (b) shows its quantum
implementation.
 A
A P=A
B
B PG Q=A⊕Β
⊕Β

C
C R=A.B⊕
⊕C
(b)
(a) Input Output
A B C P Q R
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0
(c)
Figure 2.11: (a) Peres gate (b) Graphical notation (c) Truth Table

2.6.3.6 Fredkin Gate

Fredkin gate is a (3x3) conservative reversible gate, having the mapping (A, B, C) to (P=A,
Q=A’B+AC, R=AB+A’C), where A, B, C are the inputs and P, Q, R are the outputs,
respectively [105]. It is called a 3x3 gate because it has three inputs and three outputs. Figure
2.12(a) shows the Fredkin gate and Figure 2.12(b) shows its quantum implementation [106].
Please note that each dotted rectangles in Fig. 2.12(b) is equivalent to a 2x2 Feynman gate.

A A P=A
P=A

B F Q=AB+AC
B V V V Q=AB+AC

C R=AB+AC
C R=AB+AC

(a) Fredkin gate (b) Quantum representation of the Fredkin gate

A P
Input Output
A B C P Q R
0 0 0 0 0 0
B Q 0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
Figure 2.11: a) Fredkin gate (b) Quantum
C R 1 0 0 1 1 0
1 1 0 1 0 1
1 1 1 1 1 1
(c) Graphical notation (d) Truth Table

(e) Unitary matrix

Figure 2.12: (a) Fredkin gate (b) Quantum representation of the Fredkin gate(c) Graphical
notation (d)Truth Table (e) Unitary matrix of Fredkin gate

2.6.3.7 Generalized Reversible Gates

The gates described above are basic reversible gates. Generalized reversible gates were also
proposed in addition to basic reversible gates. These gates are called Multiple-Control Toffoli
(MCT) and Multiple-Control Fredkin (MCF) gates. They are described for n-bits; where n-bit
can be any positive integer.
Multiple-Control Toffoli Gates: A Multiple-Control Toffoli gate is a generalized Toffoli
gate which has some control lines with a single target line [108]. The value on the target line
is inverted when all control lines having value 1. An MCT gate is defined for m control lines
and 1 target line makes total n = m + 1 lines. The gate maps input vectors (I1, I2…..Im) to
output vectors (O1, O2…..Om) with same values for control lines and On can be obtained by
operation I1I2….In-1⊕In as shown in Figure 2.13 (a). A Generalized MCT is defined as
CmNOT gate. A NOT gate is a generalized Toffoli gate with no control lines (i.e. m = 0). The
CNOT gate, also known as Feynman gate is an MCT gate with only one control line (for m =
1). The well known Toffoli gate with two control lines is known as C2NOT gate.
 Multiple-Control Fredkin Gates: A Multiple-Control Fredkin (MCF) gate [108] is a
generalized Fredkin gate which has some control lines and two target lines. The values on
target lines are interchanged with each other iff all control lines have value 1 at their inputs.
For n-bit MCF, there are m control lines and n target lines. This gate with no control lines is
known as Swap gate. An n*n multiple-control Fredkin gate is as shown in Figure 2.13(b).

Figure 2.13: Generalized Reversible Gates

2.6.4 Reversible Circuit

2.6.4.1 Reversible Logic Circuit and its unitary Matrix
Reversible logic circuits have been first motivated in the 1960s by theoretical considerations
of zero-energy computation as well as practical improvement of bit-manipulation transforms
in cryptography and computer graphics. Since the 1980s, reversible circuits have attracted
interest as components of quantum algorithms, and more recently in photonic and nano-
computing technologies where some switching devices offer no signal gain. A well-formed
reversible circuit is constructed by starting with wires, forming the basic circuit, and
iteratively concatenating reversible gates to some subset of the output wires of the previous
circuit. The outputs of each reversible gate replace the wires at its input i.e A reversible
circuit consists of only reversible gates which are interconnected without fanout and feedback
[144]. The fan-out refers to the maximum number of inputs that can be driven from one
output of a gate. In a reversible circuit, the fan-out of a gate is at most one.This iterative
construction naturally gives us the notion of levels in the circuit; the inputs to the circuit are
at level 0, and the outputs of any gate are at one plus the highest level of any of its inputs. For
convenience in cases where a wire at the input of a gate is at level and the outputs are at level,
we say the input is at all levels between and inclusively. This gives us wires at each level.
Figure 2.14 shows an example of a reversible circuit with the levels denoted by dotted lines.
The propagation of an input vector through the circuit is shown to illustrate the circuit’s
operation. The depth of the circuit is the maximum level, which can be no larger than the
number of gates in the circuit. We will often find it convenient to use an -bit vector to refer to
the values of the wires at a given level in the circuit. A binary vector has weight if it contains
exactly 1’s, and we denote the all-0’s and all-1’s vectors by 0 and 1 and , respectively.

Input 0 Output 0
RC RC RC
Input 1 Output 1
Input 2 Output 2

Input (n-1) Output (n-1)

d0 d1 d2 dn-1

Figure 2.14: General diagram of a reversible circuit.

Unitary matrix of a reversible circuit (Figure 2.15(a) ) is shown in Figure 2.15(b). The
Unitary matrix of a reversible circuit is obtained from the output function of the circuit or
multiplying the unitary matrices of the reversible logic gates present in the circuit.

(a)

Output
00
001 010 011 100 101 110 111
0
000 0 0 0 0 0 0 0 1
001 1 0 0 0 0 0 0 0
010 0 1 0 0 0 0 0 0
Input

011 0 0 0 1 0 0 0 0
100 0 0 0 0 1 0 0 0
101 0 0 1 0 0 0 0 0
110 0 0 0 (b)0 0 0 1 0
111 0 0 0 0 0 1 0 0
Figure 2.15: (a) A 3-qbit reversible benchmark circuit (b) Unitary matrix of the reversible
circuit.
2.6.4.2 Cost Metrics

In order to address various technical constraints in the synthesis stage, metrics have been
proposed that are used to evaluate the respective results. Among them, gate count, constant
inputs, garbage outputs, and quantum cost received most attractions [128,167]. Hardware
complexity of the gate is another issue but not received yet so much attraction from the
researchers. These are described as follows:
2.6.4.2.1 Ancilla inputs/constant inputs

This refers to the number of inputs that are to be maintaining constant at either 0 or 1 in order
to synthesize the given logical function.

2.6.4.2.2 Gate Count

Gate count refers to the number of reversible gates required in order to realize a reversible
circuit. It also defines the number of clock cycles required to make a complete round of the
given circuit. For example the gate count of the reversible circuit depicted in Figure 2.15 (a)
is 6.
2.6.4.2.3 Garbage

Additional inputs or outputs can be added so as to make the number of inputs and outputs
equal whenever necessary. This also refers to the number of outputs which are not used in the
synthesis of a given function. In certain cases these become mandatory to achieve
reversibility. Garbage is the number of outputs added to make an n-input k-output function
reversible. The following simple formula shows the relation between the number of garbage
outputs and constant inputs.

Input + constant input = output + garbage

2.6.4.2.4 Quantum Cost

Quantum costs are used to measure the implementation cost of quantum circuits. Quantum
cost refers to the cost of the circuit in terms of the cost of a primitive gate. It is calculated
knowing the number of primitive reversible logic gates (1*1 or 2*2) required to realize the
circuit. The quantum cost of a circuit is the minimum number of 2*2 unitary gates to
represent the circuit keeping the output unchanged.

The quantum cost is a very popular measure to compare reversible circuits. According to
Maslov and Dueck [124], the quantum cost of a gate is defined as the number of basic
quantum operations needed to realize the gate. Any reversible gate can be decomposed into
basic quantum (1×1 and 2×2) gates. The number of basic quantum gates is the quantum cost.
The quantum cost calculation of an n-bit Toffoli gate is presented in [121], and improved in
[123] by adding CNOT gates, and further improved in [122] by applying templates [125].The
quantum costs of the NOT gate, CNOT (2-bit Toffoli) gate, and 3-bit Toffoli gate are 1,1, and
5, respectively. The number of bits in a Toffoli gate increases the quantum cost. Forexample,
a 4-bit Toffoli gate has a cost of 13, whereas a 6-bit Toffoli gate has a cost of up to 61 [122].
The quantum costs of different reversible gates are shown in Table 2.3.

Table 2.3: QUANTUM COST OF REVERSIBLE GATES

Gate Type Quantum Cost

t0, t1 (NOT, CNOT) 1 [126]
t2 (Toffoli) 5 [104]
12 × m – 22
tm (3 ≤ m ≤ n/2
[127]
12 × m – 64
tm (n/2+1≤ m ≤ n-2
[127]
tn – 1 2n - 3 [104]
f0 (SWAP) 3 [126]
2 + Cost tm+1
fm (1≤ m≤ n-2)
[126]
Peres 4 [104]

2.6.6 Fault Models in Reversible Circuits

Fault is an error occurred in the system by which system deviates from its normal operation.
Fault models simplify complexity of testing by reducing number of faults that have to be
considered. Conventional computing uses several fault models for fault testing of digital
circuits. A typical fault model for conventional irreversible logic circuits is the stuck-at fault
model, which is based on the model that one or more wires in a circuit are stuck with some
fixed logic value. The stuck-at fault model is not adequate to represent all error effects in
reversible logic circuits since it does not cover the situations where some of the reversible
gates do not work correctly. The various fault models for reversible logic have been reported
including stuck-at, bit and missing gate fault model [130, 131] in literature.
2.6.6.1 Stuck-at Fault Model
The stuck-at fault [15] of a logic gate causes one of its inputs and outputs to be fixed at either
0 (stuck-at-0) or 1 (stuck-at-1) without considering the input value. This is a very common
fault model used for irreversible circuits. According to [16] the stuck-at fault model can be
used for the next generation technologies. For example we have a reversible circuit shown in
Figure 2.15. A stuck-at-1 on first output of the first gate gives value 1 to output O1 without
going for considering the input value. Patel et al. [132] shows testing of all single and
multiple stuck-at faults occurred in a reversible circuit.

stuck-at-1

I1 O1=1

I2 O2

I3 O3

I4 O4

Figure 2.16 : Stuck -at Fault in reversible circuits

Zhong J.[133] et al. shown that the stuck-at fault model, on its own, is inadequate for
modeling the behavior of different faults in reversible circuits. They introduce a new type of
fault model, labeled the cross point fault model.
2.6.6.2 Cross point Faults

A crosspoint fault in a reversible logic circuit is defined as either an extra or a missing

control point in a generalized Toffoli gate. It is classified into two categories: disappearance
faults and appearance faults.
A disappearance fault happens when a control point in a Toffoli gate missing. For example,
consider the structure of the full adder shown in Figure 2.17(a), in the first Toffoli gate a
disappearance fault happens if the control point from line b is missing. This fault changes the
Toffoli gate into a CNOT gate. It transpires that this disappearance fault model is the same as
the partial missing-gate fault model introduced in [131].
Control point disappears Extra control point appears

I1 O1 I1 O1

I2 O2 I2 O2

I3 O3 I3 O3

I4 O4 I4 O4
(b)
(a)

Figure 2.17 : Cross point Faults

Similarly, an appearance fault happens when an extra control point is introduced to a Toffoli
gate. For instance, consider the same fuller adder in Figure 2.17(b), a possible appearance
fault can be adding one additional control point from line a to the third gate. This appearance
fault results in transforming the 2-input Toffoli gate into a 3-input Toffoli gate. Multiple
crosspoint faults are defined as situations where two of more single crosspoint faults exist in
a reversible circuit at the same time. They are categorized into three types: multiple
disappearance faults, multiple appearance faults, and mixed multiple faults. A multiple
disappearance fault happens when at least two control points disappear from the circuit at the
same time. Similarly, a multiple appearance fault means that two or more extra control points
are added to the circuit. And a mixed multiple cross point fault happens when both
appearance fault and disappearance fault exist in a reversible circuit at the same time. The
cross point fault model is suitable for describing the faults that can happen on the control
points of generalized Toffoli gates, but it is also suitable for other reversible logic gates with
control points such as the Fredkin gates.
Several New fault models that are mainly motivated by the ion-trap quantum computing
technologies discussed in [131, 136]. The trapped-ion technology is considered as a
promising candidate to implement quantum computers as well as reversible circuits [134],
[136]. The basic assumptions are that qubits are represented by the ion state, gates correspond
to external pulses which control the interactions of the qubits, and the gate operations are
error-prone. These fault models, mainly inspired from ion-trap quantum computing
technologies, are the single missing gate fault (SMGF), the repeated-gate fault (RGF), the
multiple missing gate fault (MMGF) and the partial missing-gate fault (PMGF) models.
These fault models are described as follows:
2.6.6.3 Single missing-gate fault (SMGF)

A single missing-gate fault (SMGF) corresponds to the missing-gate fault discussed in [136].
It is defined as a complete disappearance of one CNOT gate from the circuit. The physical
justification for a SMGF is that the pulse(s) implementing the gate operation is (are) short,
missing, misaligned or mistuned.

a
a
b a⊕
⊕b

c ab⊕
⊕c

d
d
 Figure 2.18: Single missing-gate fault
Figure 2.18 shows an SMGF marked by the dotted box in the reversible circuit, where the 2nd
gate is missing. The number of possible SMGFs is equal to the number of gates in the circuit.

2.6.6.4 Multiple missing-gate faults (MMGF)

In this model, it is assumed that several consecutive gates are completely removed from the
circuit. In the circuit of Figure 2.18, it is shown that the circuit has an MMGF marked by the
dotted box. In contrast to traditional definition of multiple faults, MMGF is not necessarily
the same as multiple SMGF. In this model, all of the missed gates must be consecutive gates,
while multiple SMGF implies that several distinct arbitrary gates are missed which are not
necessarily consecutive [136]. In [136] Polian et al. described an automatic test pattern
generation (ATPG) method for detecting various missing gate fault in a reversible circuits
and results on several benchmark circuits. This model assumes the gate operations are
disturbed for several consecutive cycles, so that several consecutive gates are missing from a
circuit. An example involving two missing gates is shown in Figure 2.19.

a
a
b
b
ab⊕
⊕c
c
d
d

Figure 2.19: Multiple missing-gate faults

2.6.6.5 Repeated-gate fault (RGF)

In this fault, a gate is replaced by several instances of the same gate [136]. Figure 2.20 shows
the case in which second gate is repeated marked by the dotted box. If a gate is replaced by
even number of instances of the same gate, then fault effect is identical to SMGF of that gate
[136].The physical justification for an RGF is the occurrence of long or duplicated pulses If a
gate is replaced by even number of instances of the same gate, then fault effect is identical to
SMGF of that gate [136].If the RGF replaces a gate by odd number of instances of the same
gate, the fault is redundant, i.e., it does not change the function of the circuit.
 a
a
a⊕
⊕b
b

c
d
d

Figure 2.20: Repeated-gate fault

Further, it has been shown that any SMGF test set detects all detectable RGFs [136].

2.6.6.6 Partial missing-gate fault (PMGF)

This fault, also known as a disappearance fault, assumes a subset of control inputs of a gate is
removed. This fault turns a K-CNOT gate into K_-CNOT gate, where K_ < K. If m of the K
control inputs of a K-CNOT is removed, then the gate will be transferred to (K−m)-CNOT
gate, where m is called the order of PMGF [137]. Figure. 2.21 shows one of the possible
PMGFs on the first gate.

a
a
a⊕
⊕b
b

c b⊕
⊕c

( b⊕
⊕c ) ⊕ d
d

Figure 2.21 : Partial missing-gate fault

2.6.6.7 Bridging Fault

A test generation problem of reversible circuits are simpler than that of classical circuit due to
inherent ease of controllability and observability [94] and always yields an unique vector at
the input. Bridging faults are caused by shorts between two (or more) lines. Logically all the
lines are involved in a bridging fault may be classical AND-OR type. A bridging fault is
activated by input vector t, if the two lines are assigned opposite logic values (‘01’ or ‘10’)
then the error can be propagate to the output of the reversible circuit. Since a reversible
circuit is bijective, fault free output is different from faulty output of a reversible circuit. A
single input bridging fault (SIBF) is a bridging fault, involving two input lines at a time of
a circuit. A multiple input-bridging fault (MIBF) is a bridging fault involving more than
two input lines at a time of a circuit. An intra level bridging fault (ILBF) is a bridging faults
involving two or more intra lines into the any level of the circuit.

2.6.7 Redundancy in Reversible Circuits

Traditionally, redundancy in circuit design has been closely tied to testability. A

combinational circuit that contains an undetectable stuck-at fault is said to be redundant,
since such a circuit can always be simplified by removing at least one gate or gate input [17,
page 100]. While the presence of redundancy in digital designs may often be intentional, as in
fault tolerant systems, or for hazard avoidance, it is obvious that one would normally wish for
a synthesis algorithm to avoid the inclusion of unnecessary redundant elements.
For our purposes, a reversible logic circuit is said to be redundant if it contains a gate, or a
line (an input-output pair in a reversible logic gate), which can be removed without affecting
the logical output of the circuit. So, if one reversible logic circuit is redundant, we can
remove at least one gate or gate input-output pair from the circuit in order to reduce cost.
The Figure 2.21(a) denotes a situations where at least one gate could be removed from the
circuit, or replacing a network with one of fewer gates, such as consecutive duplicated gates.
This is one type of redundancy.

(a) Duplicated Gates (b) Gates with less inputs

Figure 2.21 : Redundancy in reversible circuits

Most of the templates introduced by Maslov, et al. ([138]) belong to this category as
templates use a simpler network to replace one with more gates.
The Figure 2.21(b) denotes another situations where gate inputs and outputs could be
removed from the circuit, such as the Toffoli network where both of the four-input
generalized Toffoli gates can be replaced with a three-input Toffoli gate. This is another one
type of redundancy. In this case although the number of gates is not decreased, the new gates
have a reduced number of control inputs and control outputs and thus the cost of the circuit is
also reduced.