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Electrical Engineering Department

ECO 223 Credits: 3

Computer Design

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William Stallings
Computer Organization
and Architecture
8th Edition
 3

+
Chapter 3
A Top-Level View of Computer
Function and Interconnection
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Outline

◼ Computer Components
◼ Computer Function
◼ Instruction Fetch and Execute
◼ Interrupts
◼ I/O Function
◼ Interconnection Structures
◼ Bus Interconnection
◼ Bus Structure
◼ Multiple-Bus Hierarchies
◼ Elements of Bus Design
◼ PCI
◼ Bus Structure
◼ PCI Commands
◼ Data Transfers
◼ Arbitration

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Computer Components

◼ Contemporary computer designs are based on concepts

developed by John von Neumann at the Institute for
Advanced Studies, Princeton

◼ Referred to as the von Neumann architecture and is based on

three key concepts:
◼ Data and instructions are stored in a single read-write memory
◼ The contents of this memory are addressable by location, without
regard to the type of data contained there
◼ Execution occurs in a sequential fashion (unless explicitly
modified) from one instruction to the next

◼ Hardwired program
◼ The result of the process of connecting the various components in
the desired configuration
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Hardware
and Software
Approaches

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Software
• A sequence of codes or instructions Software
• Part of the hardware interprets each instruction and
generates control signals
• Provide a new sequence of codes for each new
program instead of rewiring the hardware
Major components:
• CPU I/O
• Instruction interpreter Components
• Module of general-purpose arithmetic and logic
functions
• I/O Components
+ • Input module
• Contains basic components for accepting data
and instructions and converting them into an
internal form of signals usable by the system
• Output module
• Means of reporting results
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Memory Memory buffer MEMORY

address register (MBR)
register (MAR) • Contains the data
• Specifies the to be written into
address in memory memory or
for the next read or receives the data
write read from memory

MAR

I/O address I/O buffer

register (I/OAR) register (I/OBR)
• Specifies a • Used for the
+ particular I/O exchange of data
device between an I/O
module and the
CPU MBR

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Computer
Components:
Top Level
View

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Computer Function
Basic Instruction Cycle

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Fetch Cycle
◼ At the beginning of each instruction cycle the processor
fetches an instruction from memory

◼ The program counter (PC) holds the address of the

instruction to be fetched next

◼ The processor increments the PC after each instruction

fetch so that it will fetch the next instruction in sequence

◼ The fetched instruction is loaded into the instruction

register (IR)

◼ The processor interprets the instruction and performs the

required action

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 Action Categories
12

•Data transferred from •Data transferred to or

processor to memory from a peripheral
or from memory to device by transferring
processor between the processor
and an I/O module

Processor- Processor-
memory I/O

Data
Control
processing

•An instruction may •The processor may

specify that the perform some
sequence of execution arithmetic or logic
be altered operation on data

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Example
of
Program
Execution

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Instruction Cycle State Diagram

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Interrupts
Classes of Interrupts

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 Program Flow Control 17

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Transfer of Control via Interrupts

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Instruction Cycle With Interrupts

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Program
Timing:
Short I/O
Wait

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Program
Timing:
Long I/O
Wait

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 Instruction Cycle State Diagram 22

With Interrupts

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Transfer of
Control

Multiple
Interrupts

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Multiple Interrupts

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I/O Function
◼ I/O module can exchange data directly with the processor

◼ Processor can read data from or write data to an I/O module

◼ Processor identifies a specific device that is controlled by a
particular I/O module
◼ I/O instructions rather than memory referencing instructions

◼ In some cases it is desirable to allow I/O exchanges to occur

directly with memory
◼ The processor grants to an I/O module the authority to read from
or write to memory so that the I/O memory transfer can occur
without tying up the processor
◼ The I/O module issues read or write commands to memory
relieving the processor of responsibility for the exchange
◼ This operation is known as direct memory access (DMA)

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Interconnection Structures

◼ A computer consists of a set of components or modules of

three basic types (processor, memory, I/O) that
communicate with each other.

◼ In effect, a computer is a network of basic modules. Thus,

there must be paths for connecting the modules.

◼ The collection of paths connecting the various modules is

called the interconnection structure. The design of this
structure will depend on the exchanges that must be made
among modules.

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+ Computer
Modules

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 The interconnection structure must support the 28

following types of transfers:

Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory

An I/O
module is
allowed to
exchange
data
Processor Processor
directly
reads an Processor reads data Processor
with
instruction writes a from an I/O sends data
memory
or a unit of unit of data device via to the I/O
without
data from to memory an I/O device
going
memory module
through the
processor
using direct
memory
access

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A communication pathway Signals transmitted by any
connecting two or more one device are available for
devices reception by all other
• Key characteristic is that it is
devices attached to the bus
I
n
a shared transmission • If two devices transmit during the
same time period their signals will
medium overlap and become garbled
n
e
Typically consists of
t
multiple communication
Computer systems contain a
number of different buses B c
lines
• Each line is capable of
that provide pathways
between components at e
transmitting signals various levels of the u t
r
representing binary 1 and computer system hierarchy
binary 0

s i
c
System bus
The most common o
• A bus that connects
major computer
computer interconnection
structures are based on the
o
components (processor, use of one or more system n
memory, I/O)

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buses
n
 30

Data Bus
◼ Data lines that provide a path for moving data among system
modules

◼ May consist of 32, 64, 128, or more separate lines

◼ The number of lines is referred to as the width of the data

bus

◼ The number of lines determines how many bits can be

transferred at a time

◼ The width of the data bus

is a key factor in
determining overall
system performance

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31

◼ Used to designate the source or ◼ Used to control the access and the
destination of the data on the use of the data and address lines
data bus
◼ If the processor wishes to ◼ Because the data and address lines
read a word of data from are shared by all components there
memory it puts the address of must be a means of controlling their
the desired word on the use
address lines
◼ Control signals transmit both
◼ Address width determines the command and timing information
maximum possible memory among system modules
capacity of the system
◼ Timing signals indicate the validity
◼ Also used to address I/O ports of data and address information
◼ The higher order bits are
used to select a particular ◼ Command signals specify operations
module on the bus and the to be performed
lower order bits select a
memory location or I/O port
within the module
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Control Bus
◼ Typical control lines include:
◼ Memory write: Causes data on the bus to be written into the
addressed location
◼ Memory read: Causes data from the addressed location to be placed
on the bus
◼ I/O write: Causes data on the bus to be output to the addressed I/O
port
◼ I/O read: Causes data from the addressed I/O port to be placed on
the bus
◼ Transfer ACK: Indicates that data have been accepted from or
placed on the bus
◼ Bus request: Indicates that a module needs to gain control of the bus
◼ Bus grant: Indicates that a requesting module has been granted
control of the bus
◼ Interrupt request: Indicates that an interrupt is pending
◼ Interrupt ACK: Acknowledges that the pending interrupt has been
recognized
◼ Clock: Is used to synchronize operations
◼ Reset: Initializes all modules

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Bus Interconnection Scheme

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C
o a
n t
B
f i
u
i o
s
g n
u s
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Elements of Bus Design

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Elements of Bus Design

◼ Bus Types: Bus lines can be separated into two generic types:
dedicated and multiplexed.

◼ A dedicated bus line is permanently assigned either to one

function or to a physical subset of computer components.
◼ An example of functional dedication is the use of separate dedicated
address and data lines, which is common on many buses.

◼ Physical dedication refers to the use of multiple buses, each of

which connects only a subset of modules.
◼ A typical example is the use of an I/O bus to interconnect all I/O
modules; this bus is then connected to the main bus through some
type of I/O adapter module.
◼ The potential advantage of physical dedication is high throughput,
because there is less bus contention. A disadvantage is the increased
size and cost of the system.

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Elements of Bus Design

◼ Method of arbitration: In all but the simplest systems, more than one
module may need control of the bus.
◼ Because only one unit at a time can successfully transmit over the bus, some method
of arbitration is needed.

◼ In a centralized scheme, a single hardware device, referred to as a bus

controller or arbiter, is responsible for allocating time on the bus. The
device may be a separate module or part of the processor.

◼ Distributed scheme: there is no central controller. Rather, each module

contains access control logic and the modules act together to share the
bus.

◼ BUS WIDTH:
◼ The width of the data bus has an impact on system performance, The wider the
data bus, the greater the number of bits transferred at one time.
◼ The width of the address bus has an impact on system capacity, the wider
the address bus, the greater the range of locations that can be referenced.

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Elements of Bus Design

Timing: Timing refers to the way in which events are coordinated on the
bus. Buses use either synchronous timing or asynchronous timing.
◼ Synchronous timing:
◼ The occurrence of events on the bus is determined by a clock.
◼ A single 1–0 transmission is referred to as a clock cycle or bus cycle and defines a time slot.
◼ All other devices on the bus can read the clock line, and all events start at the beginning of a clock cycle.

◼ Figure 3.18 shows a typical, but simplified, timing diagram for synchronous read and write
operations :

◼ For a read operation,

◼ The processor issues a read command at the start of the second cycle.
◼ A memory module recognizes the address and, after a delay of one cycle, places the data on the
data lines.
◼ The processor reads the data from the data lines and drops the read signal.

For a write operation,

◼ The processor puts the data on the data lines at the start of the second cycle and issues a write command
after the data lines have stabilized.
◼ The memory module copies the information from the data lines during the third clock cycle.

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Timing of
1
Synchronous
Bus
2 Operations
4
3
5

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1

2
3 Timing of
4 Asynchronous
Bus
Operations

2
3
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Bus Data
Transfer
Types

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Peripheral Component
Interconnect (PCI)
◼ A popular high bandwidth, processor independent bus that can
function as a mezzanine or peripheral bus
◼ Delivers better system performance for high speed I/O subsystems
◼ The current standard allows the use of up to 64 data lines at 66 MHz.
◼ PCI is specifically designed to meet economically the I/O
requirements of modern systems;
◼ it requires very few chips to implement and supports other buses
attached to the PCI bus.
◼ PCI is designed to support a variety of microprocessor-
based configurations, including both single- and multiple-
processor systems.
◼ It makes use of synchronous timing and a centralized arbitration
scheme.
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Example PCI
Configurations

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PCI Bus Structure

◼ PCI may be configured as a 32- or 64-bit bus.

◼ 49 mandatory signal lines for PCI.
◼ 51 optional signal lines for PCI.
➢ Oral Discussion in sheet3 :
➢ Table 3.3: Mandatory PCI Signal Lines.
➢ Table 3.4: Optional PCI Signal Lines

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PCI Commands

◼ Interrupt Acknowledge ◼ Special Cycle

◼ I/O Read ◼ I/O Write

◼ Memory Read ◼ Memory Read Line

◼ Memory Read Multiple

◼ Memory Write ◼ Memory Write and

Invalidate

◼ Configuration Read ◼ Configuration Write

◼ Dual address Cycle

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Data Transfers

c
a

a
c
h
d
d

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Arbitration

◼ PCI makes use of a centralized, synchronous arbitration scheme

in which each master has a unique request (REQ) and grant
(GNT) signal.

◼ These signal lines are attached to a central arbiter and a simple

request–grant handshake is used to grant access to the bus.

◼ The PCI specification does not dictate a particular arbitration

algorithm. The arbiter can use a first-come-first-served
approach or some sort of priority scheme.

◼ A PCI master must arbitrate for each transaction that it wishes to

perform, where a single transaction consists of an address phase
followed by one or more contiguous data phases.

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Arbitration

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Spring 2023
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50
A Top-Level View of
Computer Function
and Interconnection
Chapter 3
◼ PCI express
◼ Computer components
◼ PCI physical and logical
◼ Computer function
architecture
◼ Instruction fetch and
◼ PCI commands
execute
◼ PCI data transfer
◼ Interrupts
◼ I/O function
◼ Interconnection structures
◼ Bus interconnection
◼ Bus structure
◼ Multiple bus hierarchies
◼ Elements of bus design
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