An-Najah National University ‫جامعة النجاح الوطنية‬

Faculty of Engineering and IT ‫كلية الهندسة‬

‫وتكنولوجيا المعلومات‬

Electrical and Computer Engineering Department

Digital Circuit Design II Lab : (10636391)
Report Grading Sheet

Instructor Name: Dr.Ashraf Armoush Experiment #: 4

Academic Year: 2024-2025 Performed on: 13/3/2025
Semester: second 2024 Submitted on:
Student Names:
1- Reem Salahat 2- Marah Sirhed
Evaluation Criterion CLO Grade Points
Abstract and Aims
Aims and idea of the experiment are clearly stated in 10
simple words
Introduction, Apparatus and Procedures
Introduction is complete and well-written, all
grammar/spelling correct, Appropriate background
information related to the principles of the experiment is 15
provided. The list of apparatus and procedures are also
provided
Experimental Results, Calculations and Discussion
Results analyzed correctly. Experimental findings
adequately and specifically summarized, in graphical,
tabular, and/or written form. Comparison of theoretical 50
predictions to experimental results, including discussion of
accuracy and error analysis as needed.
Conclusions
Conclusions summarize the major findings from the
experimental results with adequate specificity. 15
Highlighting the most important results
Appearance
Title page is complete, page numbers applied, content is
well organized, correct spelling, fonts are consistent, good 10
visual appeal. You have also to use reference for the
information you provide
Total
100

Abstract and Aims

An-Najah National University ‫جامعة النجاح الوطنية‬
Faculty of Engineering and IT ‫كلية الهندسة‬
‫وتكنولوجيا المعلومات‬
In this experiment , we implemented an algorithmic state machine (ASM) on the ZedBoard
(using VHDL language) to implement a traffic light controller with a countdown timer ,by using
2 digits BCD countdown timer for timing,3 LEDS for lights : red, yellow and green. and extra
modules such as: debouncer ,seven segment decoder, clock divider and time multiplexer. the aim
of this experiment is to use ASM to demonstrate a real and simple life application with deep
understanding of the extra modules used.

Introduction
In this experiment, we simulated a traffic light system using an Algorithmic State Machine
(ASM) on the ZedBoard. Starting with a countdown timer for the timing for each light,3 LEDS
for the light signals : red ,yellow and green. The timer shows time in seconds displayed on two
seven-segment displays. we used a clock divider to slow down the ZedBoard clock from
100MHz to 1Hz to count in real seconds .we used Other components, like a debouncing circuit
for push buttons and a BCD-to-seven-segment decoder, helped improve the accuracy of the
system.

Tools
1. Xilinx Vivado tool ZedBoard.
2. Power supply
3. Seven-Segment

Apparatus and procedures

Part 1: Two-Digit BCD Countdown Timer:
A countdown timer to countdown the time the light is on until it reaches zero, it consists of 2
digits counting in seconds. We implemented this module :

We did the simulation for the countdown timer

to make sure it works properly with an
indicator timer done that turns 1 when we
reach 00.

Here’s the testbench code:

An-Najah National University ‫جامعة النجاح الوطنية‬
Faculty of Engineering and IT ‫كلية الهندسة‬
‫وتكنولوجيا المعلومات‬

here are the results :

An-Najah National University ‫جامعة النجاح الوطنية‬
Faculty of Engineering and IT ‫كلية الهندسة‬
‫وتكنولوجيا المعلومات‬
timer done stays 1 because we ended the counting down without returning it to 0 after.

Part 2: clock divider

The system works on 100MHz frequency , and we are counting in seconds ,so we will divide the
input clock to generate output clock with 1Hz frequency. We made the clock divider module, it
is used in the experiment before (same concept) .

Toggling K each 49999999 to create the positive and negative pulse.

An-Najah National University ‫جامعة النجاح الوطنية‬
Faculty of Engineering and IT ‫كلية الهندسة‬
‫وتكنولوجيا المعلومات‬
Part 3: ASM
Implementing the traffic light controller using algorithmic state machine (ASM)

The traffic light controller works in this sequence :

Sequence R Y G Duration

a) Red 1 0 0 20 seconds

b) Red + Yellow 1 1 0 3 seconds

c) Green 0 0 1 20 seconds

d) Yellow 0 1 0 3 seconds

Using 3 processes to represent the system , the first is for the combinational inputs, the second is
for the next state and the third is for the synchronous changes in the registers .
An-Najah National University ‫جامعة النجاح الوطنية‬
Faculty of Engineering and IT ‫كلية الهندسة‬
‫وتكنولوجيا المعلومات‬

we declared a type (state_type) for the states to implement the ASM easily, and 2 signals for
current and next state.

The processes shown below :

the processes for combinational inputs
and next state:
An-Najah National University ‫جامعة النجاح الوطنية‬
Faculty of Engineering and IT ‫كلية الهندسة‬
‫وتكنولوجيا المعلومات‬
The rest of the next state process and the process for synchronous changes in the registers :
coded according to the ASM in the manual
An-Najah National University ‫جامعة النجاح الوطنية‬
Faculty of Engineering and IT ‫كلية الهندسة‬
‫وتكنولوجيا المعلومات‬

Part 4 : push button debouncer

Here we implemented a debouncer that would debounces the push buttons before they are
connected to the ASM machine, it is a delay to make sure we take the right value of the button,
we did a delay of 10 ms. (each pulse is 10ns so we need 10^6 pulses for debouncing).
An-Najah National University ‫جامعة النجاح الوطنية‬
Faculty of Engineering and IT ‫كلية الهندسة‬
‫وتكنولوجيا المعلومات‬
Part 5 : time mux
We can’t display both digits in the same time on the 2 seven segments LED displays. So each
time, we display a digit on each display continuously faster than the human eye recognition so
both displays will appear to be shown on the same time, so in this part we made a time
multiplexer to select between the 2 digits of the countdown timer, on each 7-segment LED
display the digit will be shown for 10ms.to indicate the current active digit we use the output
digSelect (with values 0 : for digit0 and 1 : for digit1), digit0 is the ones and digit1 is the tens.
An-Najah National University ‫جامعة النجاح الوطنية‬
Faculty of Engineering and IT ‫كلية الهندسة‬
‫وتكنولوجيا المعلومات‬
Part 6 : seven segment decoder
The BCD to 7 Segment Decoder converts a 4-bit BCD number to a 7-bit code which can be
displayed on a 7-segment display. We are working with common cathode so it is active
high(output).
An-Najah National University ‫جامعة النجاح الوطنية‬
Faculty of Engineering and IT ‫كلية الهندسة‬
‫وتكنولوجيا المعلومات‬
Part 7 : top module
Here we made the top module that includes all of the modules we made before
the module :

here’s the code of the top module that contains 2PBDebouncers,ASM module ,countdown
timer ,clock divider, time_mux , and BCD_to_sevenSeg.
An-Najah National University ‫جامعة النجاح الوطنية‬
Faculty of Engineering and IT ‫كلية الهندسة‬
‫وتكنولوجيا المعلومات‬
An-Najah National University ‫جامعة النجاح الوطنية‬
Faculty of Engineering and IT ‫كلية الهندسة‬
‫وتكنولوجيا المعلومات‬

Divided the code’s screenshots to display it bigger and better

Conclusion
In this experiment ,we learned how to implement ASM in VHDL ,with a real life application .
we gained deeper understanding for ASM in our life . we implemented other modules such as
An-Najah National University ‫جامعة النجاح الوطنية‬
Faculty of Engineering and IT ‫كلية الهندسة‬
‫وتكنولوجيا المعلومات‬
clock divider which helped us to count in seconds, learning how to control the FPGA input clock
by coding, and finally implemented the multiplexing with BCD to seven segment decoder to
display the counting .