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Lab 04

The document outlines a lab exercise focused on using the Spartan 6 FPGA kit with the Xilinx ISE Design Suite. It provides step-by-step instructions for creating a project, implementing digital circuits, and simulating designs using Verilog. The lab task involves implementing a full subtractor circuit on the FPGA kit.

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Abdul 123
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11 views8 pages

Lab 04

The document outlines a lab exercise focused on using the Spartan 6 FPGA kit with the Xilinx ISE Design Suite. It provides step-by-step instructions for creating a project, implementing digital circuits, and simulating designs using Verilog. The lab task involves implementing a full subtractor circuit on the FPGA kit.

Uploaded by

Abdul 123
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Lab:4

To Demonstrate the Use of FPGA Kit (Spartan 6) and its Integration with Xilinx ISE
Design Suite

Objective(s):

⮚ To demonstrate the use of FPGA kit and new tool Xilinx ISE.

⮚ To practice the implementation of digital circuits on the kit.

Creating Project in Xilinx

Open ISE 14.7 Suite

Step:1

Click File and then select New Project.

Step:2

A window named new project wizard will be opened. Give the Name and select location for your project
and select next.
Step:3
The next window asks you for the project settings. Specify here the family, device and package of FPGA
you are using. Preferred language Verilog. Leave the other settings as mentioned in the figure. Click next
and then finish.
Now a new project
file is opened having
your project file and
name at left most corner
in the hierarchy
pane. For simulation
of a design, select
simulation option
given above the project
name.

Step:4

Right click your project


name and select new
source.

Step:5

Select Verilog Module from the next window, give the file name and move further.
Step:6

Specify here
the inputs
and outputs
of your verilog
module. You
can select
input/output
from the drop
down menu
given in the
“direction”
column. Click
next and then finish to proceed.

Step:7
The next window is your verilog module created for a particular operation. Add the instance here(i.e the
function to be performed by the module). In the figure highlighted one “or(c,a,b);” Save your module
and now create a test bench/stimulus to check the main module
Step:8

After instantiating the module, repeat step 4 and 5 to create verilog test fixture for simulation

test.

Step:9

The verilog test bench module window will be opened. Specify the input values to drive the output in

the initial begin block (highlighted part in the figure). Save the test bench.
Step:10

Now check the syntax of your code by expanding the “ISim Simulator” option in the left bottom corner
of the same window. Double click “Behavioral Check Syntax”. If there is no error the option will be
checked with a green tick mark otherwise it will show a red cross and locate the error at the very bottom
of the window.

Step:11
After the syntax is checked, double click the “Simulate Behavioral Model” to simulate your design. A
figure showing the timing diagram will appear i.e. the simulated result of your code.
Connecting Ports in a Module

There are two methods to connect ports in a module:

1. By Order list: Using same port names and order (in stimulus) as in the module definition.

Example:

module xnor_gate(c,a,b);
input a,b;
output c;
xnor(c,a,b);
endmodule

module stimulus;
reg a,b;
wire c;
xnor_gate g1(c,a,b);
initial begin
a=1’b1;
b=1’b1;
end endmodule
2. By Name: Using different names and order of ports in stimulus with dot operator and the port
name(e.g. .a(input2)).
Example:

module xnor_gate(c,a,b);
input a,b;
output c;
xnor(c,a,b);
endmodule
module stimulus;
reg input1, input2;
wire output;
xnor_gate g1(.b(input1), .c( output), .a(input2));

initial begin
a=1’b1;
b=1’b1;

end endmodule

Lab Task(s):

1. Implement a full subtractor circuit on FPGA kit using Verilog Language.

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