Module-5

Introduction to the ARM Instruction set:

Introduction, Data processing instructions,
Load–Store instruction,Software interrupt
instructions, Program​ status register
instructions, Loading​ constants, ARM v5E
extensions,ConditionalExecution. Text
book 2: Chapter 3
DataProcessingInstructions
•​ The​ data​ processing​ instructions​ manipulate​ data​ within
registers.
•​ They are move instructions, arithmetic instructions, logical
instructions, comparison instructions, and multiply
instructions.
•​ Most data processing instructions can process one of their
operands using the barrel shifter.
•​ If you use the S suffix on a data processing instruction,then it
Updates the flags in the cpsr.
•​ Move and logical operations update the carry flag C,negative
Flag N,and zero flagZ.
•​ The carry flag is set from the result of the barrel shift as the
last bit shifted out.
•​ TheN flag is set to bit31 of the result.
•​ The Z flag is set if the result is zero.
​ Move Instructions

•​ Move is the simplest ARM instruction.

•​ It copies N into a destination register Rd,
•​ Where N is a register or immediate value.
•​ This instruction is useful for setting initial values and
Transferring data between registers.
​ BarrelShifter

•​ N can be more than just a register or immediate value; it can also be a

register Rm that has been preprocessed by the barrel shifter prior to being
used by a data processing instruction.
•​ Data processing instructions are processed within the arithmetic logic unit
(ALU).
•​ A unique and powerful feature of the ARM processor is the ability to shift the
32-bit binary pattern in one of the source registers left or right by a specific
number of positions before it enters the ALU.
•​ This shift increases the power and flexibility of many data processing
operations.
•​ There are data processing instructions that do not use the barrel shift, for
example, the MUL (multiply), CLZ (count leading zeros), and QADD (signed
saturated 32-bit add) instructions.
•​ Pre-processing or shift occurs within the cycle time of the instruction. This is
particularly useful for loading constants into a register and achieving fast
multiplies or division by a power of 2.
3.1.2BarrelShifter
3.1.2BarrelShifter
3.1.2BarrelShifter
3.1.2BarrelShifter
3.1.2BarrelShifter
 3.1.3ArithmeticInstructions

•​ The arithmetic instructions implement addition and subtraction of

32-bit signed and unsigned values.
3.1.3ArithmeticInstructions
​ LogicalInstructions

•​ Logical instructions perform bitwise logical operations on the

Two source registers.
​ LogicalInstructions
​ ComparisonInstructions

•​ The comparison instructions are used to compare or test a

register with a 32-bit value.
•​ They update the cpsr flag bits according to the result,but do
Not affect other registers.
•​ After the bits have been set,the information can then be used
To change program flow by using conditional execution.
•​ You​ do​ not​ need​ to​ apply​ the​ S​ suffix​ for​ comparison
instructions to update the flags.
​ Comparison Instructions
•​ The CMP is effectively a subtract instruction with the result
discarded; similarly the TST instruction is a logical AND
operation, and TEQ is a logical exclusive OR operation.
•​ For each, the results are discarded but the condition bits
are updated in the cpsr.
•​ It is important to understand that comparison instructions
only modify the condition flags of the cpsr and do not
affect the registers being compared.
​ MultiplyInstructions
•​ The multiply instructions multiply the contents of a pair of
registers and, depending upon the instruction, accumulate the
results in with another register.
•​ The long multiplies accumulate onto a pair of registers
Representing a 64-bitvalue.
•​ The final result is placed in a destination register or a pair of
registers.
​ Multiply Instructions
3.1.7Multiply Instructions
3.1.7Multiply Instructions

The long multiply instructions (SMLAL, SMULL, UMLAL, and UMULL) produce a
64-bit result. The result is too large to fit a single 32-bit register so the result is
placed in two registers labeled RdLo and RdHi. RdLo holds the lower 32 bits of
the 64-bit result, and RdHi holds the higher 32 bits of the 64-bit result.
​ BranchInstructions
•​ A branch instruction changes the flow of execution or is
used to call a routine. This type of instruction allows
programs to have subroutines, if-then-else structures, and
loops.
Branch Instructions
The address label is stored in the instruction as a signed pc-relative off set and must
be within approximately 32MB of the branch instruction.T refers to theThumb bit in
the cpsr.When instructions set T, the ARM switches to Thumb state.
3.2Branch Instructions
​ Load-StoreInstructions

•​ Load-store​ instructions​ transfer​ data​ between​ memory​ and

Processor registers.
•​ There are three types of load-store instructions:
1.​ single-register transfer,
2.​ multiple-register transfer,
3.​ swap.
​ Single-Register Transfer
•​ These instructions are used for moving a single data item in and
Out of a register.
•​ The data types supported are signed and unsigned words(32-bit),
half words (16-bit), and bytes.
•​ Here​ are​ the​ various​ load-store​ single-register​ transfer
instructions.
​ Single-Register Transfer
​ Single-Register Load-Store Addressing Modes
•​ The ARM instruction set provides different modes for
addressing memory.
•​ These modes incorporate one of the indexing methods:
preindex with writeback, preindex, and postindex (see Table
3.4).
​ Multiple-Register Transfer
•​ Load-store multiple instructions can transfer multiple
registers between memory and the processor in a single
instruction.
•​ The transfer occurs from a base address register
Rn pointing into memory.
•​ Multiple-register transfer instructions are more efficient
from single-register transfers for moving blocks of data
around memory and saving and restoring context and
stacks.
3.3.3Multiple-RegisterTransfer
3.3.3Multiple-RegisterTransfer
3.3.3Multiple-RegisterTransfer
3.3.3Multiple-RegisterTransfer
​ Multiple-RegisterTransfer
​ StackOperations

•​ The ARM architecture uses the load-store multiple

instructions to carry out stack operations.
•​ The pop operation (removing data from a stack)
uses a load multiple instruction; similarly, the push
operation (placing data onto the stack) uses a store
multiple instruction.
•​ When using a stack you have to decide whetherthe
stack will grow up or down in memory.
•​ A stack is either ascending (A) or descending (D).
Ascending stacks grow towards higher memory
addresses; in contrast, descending stacks grow
towards lower memory addresses.
3.3.3.1StackOperations
3.3.3.1StackOperations
3.3.3.1StackOperations
​ SwapInstruction

1.​ The swap instruction is a special case of a load-store

instruction.It swaps the contents of memory with the contents
of a register. This instruction is an atomic operation—it reads
2.​ and writes a location in the same bus operation, preventing
any other instruction from reading or writing to that location
until it completes.
 ​ Software Interrupt Instruction
•​ A software interrupt instruction (SWI) causes a software interrupt
exception, which provides a mechanism for applications to call operating
system routines.

•​ When the processor executes an SWI instruction, it sets the program counter pc to
the offset 0x8 in the vector table.
•​ The instruction also forces the processor mode to SVC,which allows an operating
System routine to be called in a privileged mode.
•​ Each SWI instruction has an associated SWI number,which is used to represent a
Particular function call or feature.
​ Software Interrupt Instruction
​ Program Status Register Instructions

•​ The ARM instruction set provides two instructions to directly

Control a program status register(psr).
•​ The MRS instruction transfers the contents of either the cpsr or
spsr into a register; in the reverse direction, the MSR instruction
transfersthe contentsof a register intothe cpsr or spsr.
•​ Together these instructions are used to read and write the cpsr
And spsr.
•​ In the syntax you can see a label called fields.
•​ This can be any combination of control (c), extension (x), status
(s),andflags(f). Thesefields relateto particularbyteregionsin a psr,
as shown in Figure 3.9.
​ Program Status Register Instructions
​ Program Status Register Instructions
​ Co processor Instructions
•​ Co processor instructions are used to extend the
instruction set.
•​ A coprocessor can either provide additional computation
capability or be used to control the memory subsystem
including caches and memory management.
•​ The coprocessor instructions include data processing,
Register transfer,and memory transfer instructions.
 ​ LoadingConstants
•​ You might have noticed that there is no ARM instruction to
move a 32-bit constant into a register. Since ARM instructions
are 32 bits in size,they obviously cannot specify a general 32-bit
constant.
•​ To aid programming there are two pseudo instructions to move
A 32-bit value into a register.
​ Loading Constants
ARM v 5EExtensions
•​ The ARM v5 Eextensions provide many new instructions(seeTable
3.13).
•​ One of the most important additions is the signed multiply accumulate
instructions that operate on 16-bit data.
•​ These operations are single cycle on many ARMv5E implementations.
•​ ARMv5E provides greater flexibility and efficiency when manipulating
16-bit values, which is important for applications such as 16-bit digital
audio processing.
Assignment
Explain the following instructions with suitable examples.
1.​ Data Processing Instructions.
2.​ Multiple-Register Transfer(21EC060-66)
3.​ Single-Register Load-Store Addressing
Modes (21EC067-73)
4.​ Load-Store Instructions(21EC074-80)
5.​ Branch Instructions(21EC080-88)
6.​ Multiply Instructions(21EC089-98)
7.​ Data Processing Instructions(21EC099-106)
8.​ Move Instructions(21EC107-404)
9.​ Arithmetic Instructions(21EC054-59)
10.​Logical Instructions(22EC0409-415)
11.​Comparison Instructions(22EC420-421,VAISHNAVIR)