Table of Contents

1. GATE Syllabus …………………………………………………………………………….. 3

2. Programming and Data Structures………………………………………………... 5
3. Design And Analysis Of Algorithms ……………………………………………………… 57
4. Compiler Design ……………………………………………………………………. 69
5. Operating System …………………………………………………………………… 90
6. Databases …………………………………………………………………………... 124
7. Software Engineering ………………………………………………………………. 154
8. Computer Networks………………………………………………………………… 160
9. Web technologies……………………………………………………………………. 179
10. Computer Organization….……………………………………………………. 185
11. Digital Logic ……………………………………………………………………. 237

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 GATE SYLLABUS
1. COMPUTER SCIENCE AND INFORMATION TECHNOLOGY – CS & IT

Engineering Mathematics

Mathematical Logic: Propositional Logic; First Order Logic.

Probability: Conditional Probability; Mean, Median, Mode and Standard Deviation; Random
Variables; Distributions; uniform, normal, exponential, Poisson, Binomial.

Set Theory & Algebra: Sets; Relations; Functions; Groups; Partial Orders; Lattice; Boolean
Algebra.

Combinatorics: Permutations; Combinations; Counting; Summation; generating functions;

recurrence relations; asymptotics.

Graph Theory: Connectivity; spanning trees; Cut vertices & edges; covering; matching;
independent sets; Colouring; Planarity; Isomorphism.

Linear Algebra: Algebra of matrices, determinants, systems of linear equations, Eigen values
and Eigen vectors.

Numerical Methods: LU decomposition for systems of linear equations; numerical solutions

of non-linear algebraic equations by Secant, Bisection and Newton-Raphson Methods;
Numerical integration by trapezoidal and Simpson's rules.

Calculus: Limit, Continuity & differentiability, Mean value Theorems, Theorems of integral
calculus, evaluation of definite & improper integrals, Partial derivatives, Total derivatives,
maxima & minima.

GENERAL APTITUDE(GA):
Verbal Ability: English grammar, sentence completion, verbal analogies, word groups,
instructions, critical reasoning and verbal deduction.

Computer Science and Information Technology

Programming and Data Structures: Programming in C; Functions, Recursion, Parameter

passing, Scope, Binding; Abstract data types, Arrays, Stacks, Queues, Linked Lists, Trees,
Binary search trees, Binary heaps.

Algorithms: Analysis, Asymptotic notation, Notions of space and time complexity, Worst and
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average case analysis; Design: Greedy approach, Dynamic programming, Divide-and-conquer;
Tree and graph traversals, Connected components, Spanning trees, Shortest paths; Hashing,
Sorting, Searching. Asymptotic analysis (best, worst, average cases) of time and space, upper
and lower bounds, Basic concepts of complexity classes P, NP, NP-hard, NP-complete.

Compiler Design: Lexical analysis, Parsing, Syntax directed translation, Runtime

environments, Intermediate and target code generation, Basics of code optimization.

Operating System: Processes, Threads, Inter-process communication, Concurrency,

Synchronization, Deadlock, CPU scheduling, Memory management and virtual memory, File
systems, I/O systems, Protection and security.

Databases: ER-model, Relational model (relational algebra, tuple calculus), Database design
(integrity constraints, normal forms), Query languages (SQL), File structures (sequential files,
indexing, B and B+ trees), Transactions and concurrency control.

Information Systems and Software Engineering: information gathering, requirement and

feasibility analysis, data flow diagrams, process specifications, input/output design, process life
cycle, planning and managing the project, design, coding, testing, implementation,
maintenance.

Computer Networks: ISO/OSI stack, LAN technologies (Ethernet, Token ring), Flow and
error control techniques, Routing algorithms, Congestion control, TCP/UDP and sockets,
IP(v4), Application layer protocols (icmp, dns, smtp, pop, ftp, http); Basic concepts of hubs,
switches, gateways, and routers. Network security basic concepts of public key and private key
cryptography, digital signature, firewalls.

Theory of Computation: Regular languages and finite automata, Context free languages and
Push-down automata, Recursively enumerable sets and Turing machines, Undecidability.

Digital Logic: Logic functions, Minimization, Design and synthesis of combinational and
sequential circuits; Number representation and computer arithmetic (fixed and floating point).

Computer Organization and Architecture: Machine instructions and addressing modes, ALU
and data-path, CPU control design, Memory interface, I/O interface (Interrupt and DMA mode),
Instruction pipelining, Cache and main memory, Secondary storage.

Web technologies: HTML, XML, basic concepts of client-server computing.

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 Programming and Data Structures
1. Which one of the following is the tightest upper bound that represents the time complexity
of inserting an object into a binary search tree of n nodes?
(A) O(1) (B) O(log n) (C) O(n) (D) O(n log n) (GATE 2013)
Answer: (C)
Explanation: For skewed binary search tree on n nodes, the tightest upper bound to insert a
node is O(n).
2. Which one of the following is the tightest upper bound that represents the number of
swaps required to sort n numbers using selection sort?
(A)O(log n) (B) O(n) (C) O(n log n) (D) O(n2) (GATE 2013)

Answer: (B)
Explanation: The maximum number of swaps that takes place in selection sort on n numbers is
n
3. Consider the following operation along with Enqueue and Dequeue operations on queues,
where k is global parameters
MultiDequeue(Q) {
m=k
while (Q is not empty) and (m >0) {
Dequeue(Q)
m=m-1
} }
What is the worst case time complexity of a sequence of n queue operations on an initially
empty queue?
(A) ϴ(n) (B) ϴ(n+k) (C) ϴ(nk) (D) ϴ(n2) (GATE 2013)
Answer: (C)
4. The preorder traversal sequence of a binary search tree is 30, 20, 10, 15, 25, 23, 39, 35, 42.
Which one of the following is the postorder traversal sequence of the same tree?
(A) 10,20,15,23,25,35,42,39,30 (B) 15,10,25,23,20,42,35,39,30
(C) 15,20,10,23,25,42,35,39,30 (D) 15,10,23,25,20,35,42,39,30

5
Answer: (D)

Explanation:
Preorder : 30,20,10,15,25,23,39,35,42
Inorder :10,15,20,23,25,30,35,39,42

5. What is the return value of f p,pif the value of p is initialized to 5 before the call? Note that the first
parameter is passed by reference, whereas the second parameter is passed by value.

int f(int&x,int c)
{
c=c-1;
if (c==0) return 1;
x=x+1;
return f(x,c)*x;
}
(A) 3024 (B) 6561 (C) 55440 (D) 161051 (GATE 2013)
Answer: (B)

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Explanation:

Common Data Questions 6 & 7:

The procedure given below is required to find and replace certain characters inside an input
character string supplied in array A. The characters to be replaced are supplied in array oldc,
while their respective replacement characters are supplied in array newc. Array A has a fixed
length of five characters, while arrays oldc and newc contain three characters each. However,
the procedure is flawed

voidfind_and_replace( char *A, char *oldc, char *newc)

{
for (inti=0;i<5;i++)
for (int j=0;j<3;j++)
if (A[i]==oldc[j])
A[i]=newc[j];
}

The procedure is tested with the following four test cases

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(1) oldc= "abc ", newc= "dab" (2) oldc= " cde", newc= "bcd"
(3) oldc= "bca", newc= "cda" (4) oldc= "abc ", newc= "bac "

6. The tester now tests the program on all input strings of length five consisting of characters
‘a’, ‘b’, ‘c’, ‘d’ and ‘e’ with duplicates allowed. If the tester carries out this testing with the four
test cases given above, how many test cases will be able to capture the flaw?
(A) Only one (B) Only two (C) Only three (D) All four (GATE 2013)
Answer: (B)
Explanation: Flaw in this given procedure is that one character of Array ‘A’ can be replaced by
more than one character of newc array, which should not be so.Test case (3) and (4) identifies
this flaw as they are containing ‘oldc’ and ‘newc’ array characters arranged in specific manner.
Following string can reflect flaw, if tested by test case (3).

Likewise single character ‘b’ in A is replaced by ‘c’ and then by ‘d’. Same way test case (4) can
also catch the flaw.
7. If array A is made to hold the string “abcde”, which of the above four test cases will be
successful in exposing the flaw in this procedure?
(A) None (B) 2 only (C) 3 and 4 only (D) 4 only (GATE 2013)
Answer: (C)
Explanation: Now for string “abcde” in array A, both test case (3) and (4) will be successful in
finding the flaw, as explained in above question.
8. What will be output of the following program?
8
char inChar=’A’;
switch(inChar)
{
case ‘A’: print(“Choice A\n”);
case ‘B’:
case ‘C’: printf(“Choice B”);
case ‘D’:
case ‘E’:
default: printf(“No Choice”);
}
(A) No Choice
(B) Choice A
(C) Choice A
Choice B No Choice
(D) Program gives no output as it is erroneous (GATE 2012)
Answer: (C)
Explanation:-Since there is no ‘break’ statement, the program executes all the subsequent
case statements after printing “choice A”.
9. Supposeacircularqueueofcapacity(n–1)elementsisimplementedwithan
arrayofnelements.Assumethattheinsertionanddeletionoperationsarecarriedoutusi
ngREARandFRONTasarrayindexvariables,respectively.Initially,REAR=FRONT=0.Thecond
itionstodetectqueuefullandqueueemptyare
(A)full:(REAR+1)modn==FRONT (B)full:(REAR+1)mod n==FRONT
empty:REAR==FRONT empty:(FRONT+1)modn==REAR

(C)full:REAR==FRONT(D)full:(FRONT+1)mod n==REAR
empty:(REAR+1)modn==FRONTempty:REAR==FRONT
(GATE 2012)
Answer:(A)
Explanation:-
Thecounterexamplefortheconditionfull:REAR=FRONTis
InitiallywhentheQueueisemptyREAR=FRONT=0bywhichtheabovefullcondition
issatisfiedwhichisfalse
Thecounterexamplefortheconditionfull:(FRONT+1)modn=REARis
InitiallywhentheQueueisemptyREAR=FRONT=0andletn=3,soafterinsertingone
elementREAR=1andFRONT=0,atthispointtheconditionfullaboveissatisfied,buts
tillthereisplacefor onemoreelementinQueue,sothisconditionisalsofalse
Thecounterexamplefortheconditionempty:(REAR+1)modn=FRONTis
InitiallywhentheQueueisemptyREAR=FRONT=0andletn=2,soafterinsertingone
elementREAR=1andFRONT=0,atthispointtheconditionemptyaboveissatisfied,b
utthequeueofcapacityn-1isfullhere
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Thecounterexamplefortheconditionempty:(FRONT+1)modn=REARis
InitiallywhentheQueueisemptyREAR=FRONT=0andletn=2,soafterinsertingone
elementREAR=1andFRONT=0,atthispointtheconditionemptyaboveissatisfied,b
utthequeueofcapacityn-1isfullhere

COMMON DATA QUESTIONS 10 & 11

Consider the following C program (2012)
int a, b, c = 0;
voidprtFun (void);
int main ()
{
staticint a = 1; /* line 1 */
prtFun();
a += 1;
prtFun();
printf ( "\n %d %d " , a, b) ;
}

voidprtFun (void)
{
staticint a = 2; /* line 2 */
int b = 1;
a += ++b;
printf (" \n %d %d " , a, b);
}
10.What output will be generated by the given code segment?
(A) 3 1 (B) 4 2 (c) 4 2 (D) 3 1
41 61 62 52
42 61 20 52
Answer (C)
Explanation:
‘a’ and ‘b’ are global variable. prtFun() also has ‘a’ and ‘b’ as local variables. The local
variables hide the globals (See Scope rules in C). When prtFun() is called first time, the local ‘b’
becomes 2 and local ‘a’ becomes 4.
When prtFun() is called second time, same instance of local static ‘a’ is used and a new
instance of ‘b’ is created because ‘a’ is static and ‘b’ is non-static. So ‘b’ becomes 2 again and
‘a’ becomes 6.
main() also has its own local static variable named ‘a’ that hides the global ‘a’ in main. The
printf() statement in main() accesses the local ‘a’ and prints its value. The same printf()
statement accesses the global ‘b’ as there is no local variable named ‘b’ in main. Also, the
defaut value of static and global int variables is 0. That is why the printf statement in main()
prints 0 as value of b.

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11.What output will be generated by the given code d\segment if: (GATE 2012)
Line 1 is replaced by “auto int a = 1;”
Line 2 is replaced by “register int a = 2;”
(A) 3 1 (B) 4 2 (C) 4 2 (D) 4 2
41 61 62 42
42 61 20 20

Answer (D)
Explanation:
If we replace line 1 by “auto int a = 1;” and line 2 by “register int a = 2;”, then ‘a’
becomes non-static in prtFun(). The output of first prtFun() remains same. But, the output of
second prtFun() call is changed as a new instance of ‘a’ is created in second call. So “4 2″ is
printed again. Finally, the printf() in main will print “2 0″. Making ‘a’ a register variable won’t
change anything in output.

12. What does the following fragment of C-program print? (GATE 2011)
char c[] = "GATE2011";
char *p =c;
printf("%s", p + p[3] - p[1]) ;
(A) GATE2011
(B) E2011
(C) 2011
(D) 011
Answer: (C)
Explanation:
See comments for explanation.
char c[] = "GATE2011";
// p now has the base address string "GATE2011"
char *p =c;

// p[3] is 'E' and p[1] is 'A'.

// p[3] - p[1] = ASCII value of 'E' - ASCII value of 'A' = 4
// So the expression p + p[3] - p[1] becomes p + 4 which is
// base address of string "2011"
printf("%s", p + p[3] - p[1]) ;

13. A max-heap is a heap where the value of each parent is greater than or equal to the value
of its children. Which of the following is a max-heap? (GATE 2011)

11
Answer: - (B)
Explanation: - Heap is a complete binary tree
COMMON DATA QUESTIONS 14 & 15
Consider the following recursive C function that takes two arguments (2011)
unsignedint foo(unsigned int n, unsigned int r) {
if (n > 0) return (n%r + foo (n/r, r ));
else return 0;
}
14. What is the return value of the function foo when it is called as foo(513, 2)?
(A) 9
(B) 8
(C) 5
(D) 2 (GATE 2011)
Answer: (D)
Explanation:
foo(513, 2) will return 1 + foo(256, 2). All subsequent recursive calls (including foo(256, 2)) will
return 0 + foo(n/2, 2) except the last call foo(1, 2) . The last call foo(1, 2) returns 1. So, the
value returned by foo(513, 2) is 1 + 0 + 0…. + 0 + 1.
The function foo(n, 2) basically returns sum of bits (or count of set bits) in the number n.

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15. What is the return value of the function foo when it is called as foo(345, 10) ?
(GATE 2011)
(A) 345
(B) 12
(C) 5
(D) 3
Answer: (B)

Explanation:

The call foo(345, 10) returns sum of decimal digits (because r is 10) in the number n. Sum of
digits for 345 is 3 + 4 + 5 = 12.

16. WhatisthevalueprintedbythefollowingCprogram? (GATE 2010)

#include<stdio.h>
intf(int*a,intn)

13
 {
if(n<=0)return0;
elseif(*a% 2==0)return*a+ f(a+1,n-1);
elsereturn*a-f(a+1,n-1);
}
intmain()
{
inta[]={12,7,13,4,11,6};
printf("%d",f(a,6));
return0;
}
1)-9 2)5 3)15 4)19

Answer (C)
Explanation:

f() is a recursive function which adds f(a+1, n-1) to *a if *a is even. If *a is odd then f()
subtracts f(a+1, n-1) from *a. See below recursion tree for execution of f(a, 6).
.
f(add(12), 6) /*Since 12 is first element. a contains address of 12 */
|
|
12 + f(add(7), 5) /* Since 7 is the next element, a+1 contains address of 7 */
|
|
7 - f(add(13), 4)
|
|
13 - f(add(4), 3)
|
|
4 + f(add(11), 2)
|
|
11 - f(add(6), 1)
|
|
6+0
So, the final returned value is 12 + (7 – (13 – (4 + (11 – (6 + 0))))) = 15

14
17. The following C function takes a singly-linked list as input argument. It modified the list by
moving the last element to the front of the list and returns the modified list. Some part of the
code is left blank. (GATE 2010)
typedefstruct node {
int value;
struct node *next
} Node;
Node *mode )_to_front(Node *head){
Node *p,*q;
if((head==NULL) ||(head->next==NULL))return head;
q=NULL;p=head;
while(p->next!=NULL)
{
q=p;
p=p->next;
}
----------------------------------------
return head;
}
Choose the correct alternative to replace the blank line.
1) q=NULL; p->next=head; head=p;
2) q->next=NULL; head=p; p->next=head;
3) head=p; p->next=q; q->next=NULL;
4) q->next=NULL; p->next=head; head=p;
Answer: (D)
Solution:
Here the program wants to make the last node of the list, the first node.
Here q is the second last node and p is the last node
The second last node’s next should be now NULL so
q->next=NULL.

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p->next should below head node.
sop->next=head
Now the head node is p.
So head = p.
Hence (D) is correct option.
18. ThecyclomaticcomplexityofeachofthemodulesAandBshownbelowis10.Whatisthe
cyclomaticcomplexityofthesequentialintegrationshownontherighthandside?
(GATE 2010)

1)19 2)21 3)20 4)10

Answer: (1)
Explanation:
Cyclomatic complexity is defined as the no. of independent paths form begin to exit in a
module. If some dependent sub modules are there in the module then the individual
cyclomatic complexities are added & overall sum is reduced by 1.
Here CC(complete) = CC(A) + CC(B) –1
So 10+10-1=19
Hence (1) is correct option.
19. What does the following program print? (GATE 2010)
#include<stdio.h>
void f(int *p, int *q)
{
p = q;
*p = 2;}
inti = 0, j = 1;
int main()
{
f(&i, &j);
printf("%d %d \n", i, j);
getchar();
return 0;
}
(A) 2 2
(B) 2 1
(C) 0 1
(D) 0 2
Answer: (D)

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Explanation:
See below f() with comments for explanation.
/* p points to i and q points to j */
void f(int *p, int *q)
{
p = q; /* p also points to j now */
*p = 2; /* Value of j is changed to 2 now */
}

20.The following program is to be tested for statement coverage : (GATE 2010)

begin
if(a==b){S1;exit}
else if(c==d){S2;}
else {S3;exit;}
S4;
end
The test cases T1, T2, T3, and T4 given below are expressed in terms of the properties satisfied
by the values of variables a_b_cand d. The exact values are not given.
T1: a,b,c and d are equal
T2: a,b,c and d are all distinct
T3: a=b and c!=d
T4: a!=b and c=d
Which of the test suites given below ensures coverage of statements S1, S2, S3 and S4?
A) T1, T2, T3
B) T2, T4
C) T3, T4
D) T1, T2, T4
Answer: (D)
Explanation:
The following test cases covers statements.
T1: all are equal
S1 executed and then so no other execution.
T2: all are distinct
Only S3 executed
T3: a=b & c!=d
Only S1 executed
T4: a!=b & c=d
Only S2,S4only
So to have all statements the option should be either T1,T2,T4or T2,T3,T4
Option (D) is T1,T2,T4
Hence (D) is correct option.

Statement for Linked Answer Questions 21 & 22 (GATE 2010)

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A has table of length 10 uses open addressing with hash function h(k)=k mod 10, and linear
probing. After inserting 6 values into an empty has table, the table is as shown below.
0
1
2 42
3 23
4 34
5 52
6 46
7 33
8
9
21. Which one oft he following choices gives a possible order in which the key values could
have been inserted in the table ?
(A) 46, 42, 34, 52, 23, 33 (B) 34, 42, 23, 52, 33, 46
(C) 46, 34, 42, 23, 52, 33 (D) 42, 46, 33, 23, 34, 52
Answer: (C)
Explanation:
Here for hashing Linear probing is used, i.e. it finds the hash key value through hash function
and maps the key on particular position In Hash table. In case of key has same hash address
then it will find the next address then it will find the next empty position in the Has Table.
Here we check all options:
(A) Here 42 will be inserted at the 2nd position in the array next 52, also has same hash
address 2. But it already occupied so it will search for the next free place which is 3rd position.
So here 52 is misplaced and it is not possible key values.
(B) Here 46 is misplaced so it is not possible value.
(C) This is same as given hash table.
So correct order is 46, 34, 42, 23, 52, 33
Hence (C) is correct option.
22. How many different insertion sequences of the key values using the same hash function
and linear probing will result in the hash table shown above ?
(A) 10 (B) 20 (C) 30 (D) 40

Answer: (C)
Explanation:
Here the given order of insertion is 46, 34, 42, 23, 52, 33
Here 42, 23, 34, 46 are inserted direct using hash function"
But to insert 52 we have 6 vacant places."
After insertion of 52 at any of the 6 places, we have 5 places"remaining for 33.
So total combination.
6 * 5 = 30 possible ways
Hence (C) is correct option.

18
23.Whatisthenumberofswapsrequiredtosortnelements usingselectionsort,intheworst case?
(GATE 2009)
A)θ(n) B)θ(nlogn)
C)θ(n2 ) D)θ(n2logn)
Answer: (C)
24. Consider the program below: (GATE 2009)
#include<stdio.h>
int fun(int n, int *f_p){
intt,f;
if (n<=1){
*f_p=1
return 1;
}
t=fun(n-1,f_p);
f=t+*f_p;
*f_p=t;
return f;
}
int main () {
int x=15;
printf(“%d\n”, fun(5,&x));
return 0;
}
The value printed is:
A) 6 B) 8 C) 14 D) 15
Answer: B
Explanation:

Here the table column I, II, & III are during the forward calls of the recursive function fun &The
part after arrow in column III is updated value during return calls & column IV & V are the
returned values.
19
In the end 8 is returned so only this will be printed
Hence (B) is correct option.
25. What is the maximum height of any AVL-tree with 7 nodes ? Assume that the height of a
tree with a single node is 0. (GATE 2009)
(A) 2 (B) 3
(C) 4 (D) 5
Answer: (B)

Explanation:
AVL tree is a partially balanced tree with the weights assigned to thenodes can be only −1,0 or
1. This weight is assigned on the basis of difference of the no. of children in the left subtree&
right subtree. If some other weight is there then we rotate the tree to balance it.

In this tree the height is 3 and it is Also AVL balanced so maximum height will be 3
Hence (B) is correct option.

Statement for Linked Answer Question 26 & 27 (GATE 2009)

Consider a binary max-heap implemented using an array
26.Which one of the follow9ng array represents a binary max-heap?
(A) {25, 12, 16, 13, 10, 8, 14}
(B) {25, 14, 13, 16, 10, 8, 12}
(C) {25, 14, 16, 13, 10, 8, 12}
(D) {25, 14, 12, 13, 10, 8, 16}
Answer: (C)
Explanation:
If the value presented at any node is greater then all its children then the tree is called the
max heap.
Here we need to draw heap for all options

20
Hence (C) is correct option.

27. What is the content of the array after two delete operations on the correct answer to the
previous question? (GATE 2009)
(A) {14, 13, 12, 10, 8} (B) {14, 12, 13, 8, 10}
(C) {14, 13, 8, 12, 10} (D) {14, 13, 12, 8, 10}
Answer: (D)
Explanation:

21
28. Which combination of the integer variables x,y, and z makes the variable a get the value 4
in the following expression? (GATE 2008)
a = (x >y)?((x>z)?x:z): ((y >z)?y:z)

(A) x= 3,y = 4,z = 2 (B) x = 6,y = 5,z = 3

(C) x= 6,y = 3,z = 5 (D) x = 5,y = 4,z = 5

Answer: (A)
Explanation:
a = (x >y)?((x>z)?x:z): ((y >z)?y:z)
Expr 1?expr 2 : expr 3 ;
Here Expr 1 is a comparison expression whose result may be true or false. If true returned the
expr 2 is selected as choice otherwise expr3.
Here we want 4 to be printed which is only in option (A) & (D) for y = 4 to be printed.
x >y should be false since y is in true part so this expr should be true.
So both the conditions are true in option (A) only so correct.
We can check.
x=3y=4z=2
a = (x >y)?((x >z)?x:z) ((y >z)?y:z)
First we can check 3 >2 ?3 : 2 thus 3 is selected
Then 4 >2 ?4 : 2 here 4 is selected
Hence a = 3 > 4?3:4 = 4
Hence (A) is correct option.

30. What is printed by the following C program? (GATE 2008)

int f(int x, int *py, int **ppz)
{
int y, z;
**ppz += 1;
z = **ppz;

22
 *py += 2;
y = *py;
x += 3;
return x + y + z;
}

void main()
{
int c, *b, **a;
c = 4;
b = &c;
a = &b;
printf( "%d", f(c,b,a));
getchar();
}
(A) 18
(B) 19
(C) 21
(D) 22

Answer :(B)
Explanation:
/* Explanation for the answer */

/*below line changes value of c to 5. Note that x remains unaffected

by this change as x is a copy of c and address of x is different from c*/
**ppz += 1

/* z is changed to 5*/
z = **ppz;

/* changes c to 7, x is not changed */

*py += 2;

/* y is changed to 7*/
y = *py;

/* x is incremented by 3 */
x += 3;

/* return 7 + 7 + 5*/
return x + y + z;

23
31. Choose the correct option to fill ?1 and ?2 so that the program below prints an input string
in reverse order. Assume that the input string is terminated by a newline character.
(GATE 2008)
void reverse(void)
{
int c;
if (?1) reverse() ;
?2
}
main()
{
printf ("Enter Text ") ;
printf ("\n") ;
reverse();
printf ("\n") ;
}
(A) ?1 is (getchar() != ’\n’)
?2 is getchar(c);
(B) ?1 is (c = getchar() ) != ’\n’)
?2 is getchar(c);
(C) ?1 is (c != ’\n’)
?2 is putchar(c);
(D) ?1 is ((c = getchar()) != ’\n’)
?2 is putchar(c);
Answer: (D)
Explanation:
getchar() is used to get the input character from the user and putchar() to print the entered
character, but before printing reverse is called again and again until ‘\n’ is entered. When ‘\n’
is entered the functions from the function stack run putchar() statements one by one.
Therefore, last entered character is printed first.
You can try running below program
void reverse(void); /* function prototype */

void reverse(void)
{
int c;
if (((c = getchar()) != '\n'))
reverse();
putchar(c);
}
main()
{
printf ("Enter Text ") ;
printf ("\n") ;

24
reverse();
printf ("\n") ;
getchar();
}
32. The following postfix expression with single digit operands in evaluated using a stack
823^/23*+ 51*− . Note that ^ is the exponentiation operator. The top two elements of the stack
after the first* is evaluated are (GATE 2007)

(A) 6, 1 (B) 5, 7
(C) 3, 2 (D) 1, 5
Answer: (B)
Explanation:
Given postfix expression is 823^/23*+ 51*−
Scanning the string from left to right we push all the digits,& we get any operator we evaluate
the operation between top 2 elements poped from stack. Then the result is pushed again into
stack.

Stack contain 5, 7
Hence (B) is correct option
33.Consider the following C-function in which a[n] and b[n] are two sorted integer arrays and
c[n+m] be another integer array. (GATE 2006)
void xyz (int a[],int b[],int c[]){
inti, j, k;
i=j=k=0;
while((i<n))&&(j<m)
if (a[i]<b[j])
c[k++]=a[i++];

25
else
c[k++]=b[j++];
}
Which of the following condition (s) hold (s) after the termination of
the while loop ?
I j<m, k=n+j-1, and a [n-1]<b[j] if i=n
II i<n, k=m+j-1, and b[m-1]<=a[i] if j=m
(A) only (I)
(B) only (II)
(C) either (I) or (II) but not both
(D) neither (I) nor (II)
Answer: (C)
Explanation:
While loop will terminate i>= n &j >= m program is to merge a &b arrays into C .
While loop terminates after merging then either (I) or (II) should hold but not both at the same
time.
(I) says j <m & (II) say j = m vice versa
Hence (C) is correct option.
34.Consider the C code to swap two integers and these five statements:
the code (GATE 2006)
void swap(int *px,int*py){
*px=*px−*py;
*py=*px+*py;
*px=*py−*px;
}
S1: will generate a compilation error
S2: may generate a segmentation fault at runtime depending on the arguments passed
S3: correctly implements the swap procedure for all input pointers referreing to integers
stored in memory locations accessible to the process
S4: implements the swap procedure correctly for some but not all valid input pointers
26
S5: may add or subtract integers and pointers
(A) S1 (B) S2 and S3
(C) S2 and S4 (D) S2 and S5
Answer: (C)
Explanation:
Here pointers are used without initialization also the address pointed by then may be out of
segment of program, so segmentation.
 Fault may be there so. S2 correct.
 Here no compiler error S1 false.
 Correctly done swap procedure but not all valid import pointers so S4 also true.
S2 &S4 are correct.
Hence (C) is correct option.
Common Data Questions 35 & 36
(GATE 2006)
A 3-ary max heap os like a binary max heap, but instead of 2 children, nodes have 3
children, A 3-ary heap can be represented by an array as follows: The root is stored in the first
location, a [0], nodes in the next level, from left to right, is stored form a[1] to a[3]. The nodes
from the second level of the tree from left to right are stored from a[4]
location onward.
An item x can be inserted into a 3-ary heap containing n items by placing x in the location a [n]
and pushing it up the tree to satisfy the heap property.

35.Which one of the following is a valid sequence of elements in an array representing 2-ary
max heap ?
(A) 1, 3, 5, 6, 8, 9 (B) 9, 6, 3, 1, 8, 5
(C) 9, 3, 6, 8, 5, 1 (D) 9, 5, 6, 8, 3, 1
Answer: (D)
Explanation:

27
Here in option (A), (B) and (C), value present at node is not greater then all its children.
Hence (D) is correct option.
36.Suppose the elements 7, 2, 10, and 4 are inserted, in that order, into the valid 3-ary max
heap found in the above question, Q. 38. Which on of the following is the sequence of items in
the array representing the resultant heap ? (GATE 2006)
(A) 10, 7, 9, 8, 3, 1, 5, 2, 6, 4
(B) 10, 9, 8, 7, 6, 5, 4, 3, 2, 1
(C) 10, 9, 4, 5, 7, 6, 8, 2, 1, 3
(D) 10, 8, 6, 9, 7, 2, 3, 4, 1, 5
Answer: (A)
Explanation:
Given heap is as follows

To add 7, 2, 10, 4 we add the node at the end of array

28
We keep if at right place in the heap tree.
Compare elements with its parent node. Since 10 > 6 and 7 >5, we interchange

Since 10 >9, we interchange and we get

n/2=10/2=5
3 is at right position
4 is at right position
Hence (A) is correct option.
37. What does the following C-statement declare? (GATE 2005)
Int (*f) (int*)
(A) A function that takes an integer pointer as argument and returns an integer
(B) A function that takes an integer pointer as argument and returns an integer pointer
(C) A pointer to a function that takes an integer pointer as argument an returns
(D) A function that takes an integer pointer as argument returns a function pointer
29
Answer: (C)
Explanation:
Given statement int (*f) (int*)
This is not the declaration of any function since the f has *(pointer symbol) before it. So f is a
pointer to a function also the argument type is int *& the return type is int.
So overall we can say that f is a pointer to a function that takes an integer pointer as argument
and returns an integer.
Hence (C) is correct option.
38.An Abstract Data type (ADT) is (GATE 2005)
(A) same as an abstract class
(B) a data type that cannot be instantiated
(C) a data type for which only the operations defined on it can be
used, but none else
(D) all of the above
Answer: (C)
Explanation:
Abstract Data type :- It is defined as a user defined data type, specified by keyword ‘abstract’
& defines the variables & functions, these operations can only use the variables of this data
type.
So option (C) which says that Abstract data type for which only operations defined on it can be
used is correct.
Eg.stack data type
Here operations defined are push & pop. So we can apply only these 2 operations on it.
Hence (C) is correct option.
39.A common property of logic programming languages and functional languages is
(A) both are procedural language (GATE 2005)
(B) both are based onλ−calculus
(C) both are declarative
(D) all of the above
Answer: (D)
30
Explanation:
λ-calculus" It provides the semantics for computation with functions so that properties of
functional computation can be studied.
Both the languages require declaration before use of any object.
Both are procedural
So option (D) is correct.
Both the languages are based on λ calculus, procedural & declarative
Hence (D) is correct option.
40.Which of the following are essential features of an object-oriented programming
languages? (GATE 2005)
1. Abstraction and encapsulation
2. Strictly-typedness
3. Type-safe property coupled with sub-type rule
4. Polymorphism in the presence of inheritance
(A) 1 and 2 only (B) 1 and 4 only
(C) 1, 2 and 4 only (D) 1, 3 and 4 only
Answer: (B)
Explanation:
Object oriented programming languages necessarily have features like Abstraction
Encapsulation, inheritance with polymorphism. but OOPL are also strongly-typed since there
are restrictions on how operations involving values having different data types can be
intermixed.
Eg.two integers can be divided but one integer & one string can’t.
Hence (B) is correct option.
41.A program P reads in 500 integers in the range (0, 100) representing the scores of 500
students. It then prints the frequency of each score above 50. What be the best way for P to
store the frequencies? (GATE 2005)
(A) An array of 50 numbers
(B) An array of 100 numbers
(C) An array of 500 numbers
31
(D) A dynamically allocated array of 550 numbers
Answer: (A)
Explanation:
Here the no. readable are range 0 to 100 but the output of the program is interested in scores
above 50 so there are 50 values (51 to 100) in this range.
So only an array 50 integers required as we get any no. we increment the value stored at
index.
Array [x − 50] by 1.
Hence (A ) is correct option.
42.Consider the following C-program (GATE 2005)
double foo (double); /* Line 1*/
int main(){
doubleda_db;
// input da
db _foo(da);
}
double foo(double a){
returna;
}
The above code complied without any error or warning. If Line 1 is deleted, the above code
will show
(A) no compile warning or error
(B) some complier-warning not leading to unitended results
(C) Some complier-warning due to type-mismatch eventually leading to unitended results
(D) Complier errors
Answer: (C)
Explanation:
Here if line 1 which is prototype declaration of the function foo, in C compilation process this
would give an compile warning , due to type-mismatch. Since then compiler won’t know what
is the return type of foo.
So unintended results may occur.
Hence (C) is correct option.
43.Postorder traversal of a given binary search tree, T produces the following sequence of
keys10, 9, 23, 22, 27, 25, 15, 50, 95, 60, 40, 29
Which one of the following sequences of keys can be the result of an inorder traversal of the
tree T? (GATE 2005)

32
(A) 9, 10, 15, 22, 23, 25, 27, 29, 40, 50, 60, 95
(B) 9, 10, 15, 22, 40, 50, 60, 95, 23, 25, 27, 29
(C) 29, 15, 9, 10, 25, 22, 23, 27, 40, 60, 50, 95
(D) 95, 50, 60, 40, 27, 23, 22, 25, 10, 0, 15, 29
Answer: (A)
Explanation:
When we are given any no elements & even any order (preorder or post order) & we need to
calculate inorder, then inorder is simply sorted sequence of the elements.
Here 9, 10, 15, 22, 23, 25, 27, 29, 40, 50, 60, 95
Hence (A) is correct option.
44.Assume that the operators +, -,# are left associative and ^ is right associative .The order of
precedence (from highest to lowest) is ^,#, +, -. The postfix expression corresponding to the
infix expression a + b#c - d ^ e ^ f is (GATE 2004)

(A) abc#+def ^^− (B) abc#+de^f^

(C) ab+c#d−e^f^ (D) −+a#bc^^def

Answer: (A)
Explanation:
Given expression a + b)c− d/e/f
parenthesizing the expression as per given rules.
= ((a + (b)c)) − (d/(e/f)))
= ((a + (bc))) − (d/(ef/)))
= ((abc)+) − (def//))
= (abc)+def//−)
So option (A) is correct
You can also solve using stack.
Hence (A) is correct option.

45.Consider the following C program (GATE 2004)

main ()
33
{ int x, y, m, n;
scanf(“%d%d”, &x,&y);
/*Assume x>0 and y>0*/
m=x; n=y;
while (m!=n)
{ if (m>n)
m=m−n;
else
n=n−m;
}
printf(“%d”,n);
}

The program computers

(A) x'y, using repeated subtraction (B) x mod y using repeated subtraction
(C) the greatest common divisor of x and y (D) the least common multiple of x only

Answer: (A)
Explanation:
Here if m >n then m = m − n
m <n then n = n − m
Let take X = 24 Y = 9
Then m = 24 n = 9
iteration m n
1 24 − 9 = 15 9
2 15 − 9 = 6 9
3 6 9−6=3
4 6−3=3 3
Here m = n so n returned
Which is GCD (Greatest common divisor) of X &Y
Hence (C) is correct option.

46.What does the following algorithm approximate ? (Assume m>1, E> 0). (GATE 2004)
x=m;
y=1;
while (x−y>E)
{ x=(x+y)/2;
y=m/x;
}
print (x);

34
(A) log m (B) m2
(C) m1/2 (D) m1/3
Answer: (C)
Explanation:
Here we take let x = 16
Loop will stop when x − y = 0 or >0
Iteration X Y
1 (16+1)/2=8 16/8=2

2 (8+2)/2=5 16/5=3
3 (5+3)/2=4 16/4=4
Here X = Y
Then take X. which is 4.
(m)1/2 = 4 = (16)1/2
Hence (C) is correct option.

47.Choose the best matching between the programming styles in Group 1 and their
characteristics in Group 2. (GATE 2004)

Group-1 Group-2

P. Functional 1. Command-based, procedural

Q. Logic 2. Imperative, abstract data types

R. Object-oriented 3. Side-effect free, declarative,

expression evaluation
S. Imperative
4. Declarative, clausal
representation, theorem proving

35
(A) P-2, Q-3, R-4, S-1 (B) P-4, Q-3, R-2, S-1
(C) P-3, Q-4, R-1, S-2 (D) P-3, Q-4, R-2, S-1
Answer: (D)
Explanation:
p. Functional Programming is declarative in nature, involves expression evaluation, & side
effect free.
q Logic is also declarative but involves theorem proving.
r. Object oriented is imperative statement based & have abstract (general) data types.
s Imperative :- The programs are made giving commands & follows definite procedure &
sequence.
Hence (D) is correct option.
48)What is printed by the print statements in the program P1 assuming
call by reference parameter passing ? (2001)
Program P1( )
{
_ _ 1__
_ _ __
____1(*)_
_r___ x;
_r___ y;
}
func1(x,y,z)
{
y=y+4
z=x+y+z;
}
(A) 10, 3
(B) 31, 3
(C) 27, 7
(D) None of the above

36
SOLUTION
Since the function fun 1 doesn’t return the values of x & y and x & y are not passed by
reference. So in program P1( ) would print x = 10 & y = 3. So 10, 3
Hence (A) is correct option.

49)Consider the following three functions. (2001)

[P1] int *g(void)
{
Int x=10;
return (& x);
}
[P2] int *g(void)
{
int *px;
*px=10;
return px;
}
[P3] int *g(void)
{
int *px
px=(int*)malloc (size of (int));
*px=10;
return px;
}
Which of the above three functions are likely to cause problems with
pointers ?
(A) Only P3
(B) Only P1 and P3
(C) Only P1 and P2
(D) P1, P2 and P3

SOLUTION

37
P1 : Here the function is returning address of the variable x (& x ) but the return type is pointer
to integer not address. So incorrect.
P2 : *px = 0 directly assigned a value but still px doesn’t point to any memory location, so
memory initialization or allocation should be done before. So incorrect.
P3: Correction made in P2, memory pre allocated, So correct.
Hence (C) is correct option.

50)Consider the following program (2001)

Program P2
Var n:int:
procedure W (var x:int)
begin
X=X+1
Print x;
end
Procedure D
Begin
var n:int;
n=3;
W(n);
End
Begin \\begin P2
n=10;
D;
end
If the language has dynamic scooping and parameters are passed by reference, what will be
printed by the program ?
(A) 10
(B) 11
(C) 3
(D) None of the above

38
SOLUTION
n = 10 given but not passed to D. In D, n = 3 & W(n) increments by
1. So n = n + 1 = 4.
Hence (D) is correct option.

51)The results returned by function under value-result and reference parameter passing
conventions. (2002)
(A) Do not differ
(B) Differ in the presence of loops
(C) Differ in all cases
(D) May differ in the presence of exception
SOLUTION
The results returned by function under value & reference parameter passing may differ in
presence of loops.
Hence (B) is correct option.

52)Consider the following declaration of a two-dimensional array in C. (2002)

Char a[100][100]
Assuming that the main memory is byte-addressable and that array is stored starting form
memory address 0, the address of a [40] [50] is
(A) 4040 (B) 4050
(C) 5040 (D) 5050
SOLUTION
Char a[100] [100]
1 char require 1 byte
Total required 10000 bytes.
Memory format is byte addressable
A[0] … a[0][50] … a[0][99]
. … … … .
. .
. .
A[50][0] a[40][50]
.
39
.
.
A[99][0] … … … a[99][99]
100 bytes per row. I.e 40#100 = 4000
1 byte per column I. e. 50#1 = 50
Total 4050
Hence (B) is correct option.

53) Consider the following C function.(2003)

fl oat f(fl oat x, int y){
fl oat p, s; int i;
for (s=1, p=1, i=1, i<y; i++)
{
p)=x/i;
s+=p;
}
return s;
}
For large values of y, the return value of the function f best approximates
(A) xy
(B) ex
(C) In(1 + x)
(D) xx
SOLUTION
The function is rewritten as
s = _;p = _;
for _i = _;i _ y;i ++_
{ p = p)x/i;
s = s + p;
}
Here initial value of s increments every time with a factor of p)x/i
Initially s = _ _ p = _

40
1x1+x
4 x3/3! x/4 x4/4! # = 1 + x + x2/2! + x3/3! + x4/4!

Loop P S

counter (i)

1 x 1+x

2 x)x/2 : 1 = x2/2 : 1 1 + x + x2/2

3 x2/2)x/3 = x3/3 : 2 : 1 1 + x + x2/2! + x3/3!

4 x3/3! x/4 x4/4! 1 + x + x2/2! + x3/3! + x4/4!

Thus it can be checked for every value.

Here the assumption is that the value of y is very large so y " 3
So the series 1 + x + x2/2! + x3/3!................3 will have infinite terms & from our previous
knowledge we know that this 3 series is expansion of ex (exponential series) so. 1 + x + x2/2! +
x3/3!...........3 = ex
Hence (B) is correct option.

54)Assume the following C variable declaration (2003)

int)A[10], B[10][10];
Of the following expressions
(1) A[2]
(2) A[2][3]
(3) B[1]

41
(4) B[2][3]
Which will not give compile-time errors if used as left hand sides of assignment statements in a
C program ?
(A) 1, 2, and 4, only (B) 2, 3, and 4, only
(C) 2 and 4 only (D) 4 only

SOLUTION
We have int )* which is an array of 10 integer value pointer whereas B[10] [10] is an array
which stores 10#10 = 100 integers So let us try to solve it eliminating way.
" Option 3 B[1] can’t be at the left side since it is 2D array so can’t use single index. We need
not necessarily specify the size of first dimension for B[][3]
" Option 4 B[2][3] is assignment to the array B value so possible.
" Option 1 A [2] is also possible to assign some address os integer value
" Option 2 this is some what tricky. Here A[2][3] becomes a 2D array if integer where A [2]
means the 2nd integer in this array and A[2][3]o means 3rd integer in this row. eg. A[2] [3] = 5
means that at second row the third integer value is 5. Hence (*) Is correct option.

55)Let T(n) be the number of different binary search trees on n distinct elements. (2003) Then
T[n] T(k 1)T(x)
k1
n
=−
=/
, where x is
(A) n − k + 1
(B) n − k
(C) n − k − 1
(D) n − k − 2

SOLUTION

42
Binary search tree has a root node & its 2 subtrees. So for every node other than the leaves, all
the elements smaller than the node are its left subtree & all the nodes which have value equal to
or greater than that node are at right subtree. Here the given expression.
T(n) T(k 1)T(X)
K
n
1
=−
=/
Figure
n(B) = no. of nodes in left subtree
n(C) " no. of nodes in right subtree
T(n) = n(B) + n(C) + 1
T(n) T(X)T(k 1)
K
n
1
=−
=/
Expanding forT (k − 1) we get
T(n) T(X) [T(0) T(1) T(2) .....T(n 1)]
K
n
1
=:++−
= 144444444424444444443
/
no. of nodes in left subtree denoted by K
Total nodes = n
So remaining node n − (k − 1) i.e nodes in the right subtree.
So = n − k + 1
So overall we can say that the no. of different BST’s on n different
43
elements.
T(n) T(n k 1)T(k 1)
n
k
1
= −+ −
=/
Hence ( ) is correct option.

56) A data structure is required for storing a set of integers such that each of the following
operations can be done is (logn) time, where n is the number of elements in the set. (2003)
1. Delection of the smallest element.
2. Insertion of an element if it is not already present in the set.
Which of the following data structures can be used for this purpose ?
(A) A heap can be used but not a balanced binary search tree
(B) A balanced binary search tree can be used but not a heap
(C) Both balanced binary search tree and heap can be used
(D) Neither balanced binary search tree nor heap can be used
SOLUTION
Both the tasks can be performed by both the data structures but heap is a data structure where to
perform these function every element has to be checked so O(n) complexity. But the balance
binary search tree is efficient data structure since at every decision it selects one of its subtree to
no. of elements to be checked are reduced by a factor of 1/2 every time.
n/2! = x
x = logn
Hence (B) is correct option.

57) Let S be a stack of size n $ 1. Starting with the empty stack, suppose we push the first n
natural numbers in sequence, and then perform n pop operations. Assume that Push and Pop
operation take X seconds each , and Y seconds elapse between the end of the one such stack
operation and the start of the next operation. For m $ 1, define the stack-life of mcs the time

44
elapsed from the end or Push (m) to the start of the pop operation that removes m from S . The
average stack-life of an element of this stack is (2003)
(A) n(X + Y)
(B) 3Y + 2X
(C) n(X + Y) − X
(D) Y + 2X

SOLUTION
Here each of PURSH & POP operation take X seconds & Y seconds are elapsed between two
consecutive stack operations. m is the life time of element in stack. So m X is time for push.
m X is time for pop.
m Y is time for intermediate
So total m(2X + Y)
Average stack life ( )
m
= m 2X + Y
= 2X + Y
= Y + 2X
Hence (D) is correct option.

58) Consider the C program shown below.

#include <stdio.h>
#defi ne print(x)printf(“%d”,x)
int x;
void Q (int z){
z+=x; print(z);
}
void p (int)y){
int x=)y+2;
Page 13
www.gatehelp.com CS Topicwise 2001-2010
Programming & Data

45
Structure
Q(x);)y=x-1;
print(x);
}
main (void){
x=5;
p(&x);
print(x);
}
The output of this program is
(A) 12 7 6 (B) 22 12 11
(C) 14 6 6 (D) 7 6 6
SOLUTION
Figure
Here X is the global variable so still 5. Figure Here this is global X whose xy has been changed
to 6 so 6 is printed 12 66
Hence (A) is correct option.
First x=5 Then by function p(&x)
X =5+2=7 Then by function Q(x)
z =z+x
=7+5=12
Here x is global variable so still it is 5. Return to function p(&x)
Y =7-1=6
print x =7
return to main
Print x =6
Here this is global x whose *y ahs been changed to 6 so 6 is printed.
59) Consider the function - defined below.(2003)
struct item {
int data;
struct item)next;
};
46
int f (struct item )p){
return ((p==NULL)||(p−>next==NULL)||
((p−>data<=p−>next−>data)&&
f(p−>next)));
}
For a given linked list p, the function f return 1 if and only if
(A) the list is empty or has exactly one element
(B) the elements in the list are sorted in non-decreasing order of data value
(C) the elements in the list are sorted in non-increasing order of data value
(D) not all elements in the list have the same data value
SOLUTION
Here the return 1 any 1 of the following should be correct.
(A) P == NULL i.e the list is empty (ends)
(B) P " next = NULL i.e have one element.
(C) P " data <= p " next " data i.e the element is smaller than its next element also. This is true
for whole list. Since &&f(p "next) is also there. So overall it gives that the elements should be
in sorted order.
Hence (B) is correct option.

60) The goal of structured programming is to (2004)

(A) have well indented programs
(B) be able to infer the flow of control from the compiled code
(C) be able to infer the flow of control form the program text
(D) avoid the use of GOTO statements
SOLUTION
Structured programming :- It is way of programming using the sub structure method, i.e
splitting the programs into sub sections. Structured programming prevents confusing transfer of
control of avoiding the use of GOTO statements.
Hence (D) is correct option.

61) Consider the following C function (2004)

void swap (int a, int b)
{int temp;
47
temp =a;
a =b;
b =temp;
}
In the order to exchange the values of two variables x and y .
(A) call swap (x,y)
(B) call swap (&x,&y)
(C) swap (x,y) cannot be used as it does not return any value
(D) swap (x,y) cannot be used as the parameters are passed by value
SOLUTION
Here the function takes the arguments by value.
" Option (A) sends parameter by value but only the local variable
a & b will be exchanged but not the actual variables x & y so
incorrect.
" Option (B) is incorrect sending address of x & y .
" Option (C) swap (x,y) is usable there is no need to return.
" Option (D) is the opposite statement of option (A), it says that the values are passed by value
so won’t swap so the option is correct.
Hence (D) is correct option.

62) A single array A [1........MAXSIZE] is used to implement two stacks. The two stacks grow
from opposite ends of the array. Variables top 1 and top 2 (top 1<top 2) point to the location of
the topmost element in each of the stacks. If the space is to be used efficiently, the condition for
“stack full” is
(A) (top 1=MAXSIZE/2) and (top 2=MAXSIZE/.2+1)
(B) top 1+top2=MAXSIZE
(C) (top 1=MAXSIZE/2) or (top2=MAXSIZE)
(D) top 1=top 2−1
SOLUTION
Let take maxsize =10
1 2 3 4 5 6 7 8 9 10

48
Here the stack will be fuel if both top 1 & top 2 are at the adjacent index values i.e. their
difference is 1.
So top 1 = top 2 – 1
Here (D) is correct option.

63) The best data structure to check whether an arithmetic expression

has balanced parenthesis is a
(A) queue
(B) stack
(C) tree
(D) list
SOLUTION
Balanced parenthesis in an equation are such that the no. of opening and closing parenthesis and
in correct order should be there. We can check balancing using stack. When we get any opening
parenthesis then we push that in the stack & if we get a closing one then we pop the stack. After
the complete scanning of input string if
stack is found empty then the arithmetic expression is balanced.
Hence (B) is correct option.

63) Consider the following C function

int f(int n)
{static int i=1;
if (n>=5) return n;
n=n+i;
i++;
return f(n);
}
The value returned by f(1) is
(A) 5 (B) 6
(C) 7

49
(D) 8
SOLUTION
Here i is an static variable, so if it is once initialized it can’t be initialized again during its scope
n is incremented by 1 & f(n) is called then. The final return is when n>=5 i.e. n returned then
Step Call n i
(1) 1 1 1 condition false n < 5
(2) 1+1=2 2
(3) 2 2 2 false n < 5
(4) 2+2=4 3
(5) 3 4 3 false n < 5
(6) 4+3=7 4
(7) 4 7 4 true return n = 7
So return value is 7.
Hence (C) is correct option.

64) Consider the following program fragment for reversing the digits in a given integer to
obtain a new integer. Let ....... n d d d. = 1 2 m
int n, rev;
rev=0;
while(n>0){
rev=rev)10+n%10;
n=n/10;
}
The loop invariant condition at the end of the ith iteration is
(A) n = d1d2......dm−i and rev = dmdm−1......dm−i+1
(B) n = dm−i+1.....dm−1dm or rev = dm−i .....d2d1
(C) n =Y rev
(D) n = d1d2....dm or rev = dm......d2d1

SOLUTION
Here after every iteration one digit is reduced from n since n = n/10 so unit place is removed.

50
This unit place is then added into the previous reverse sum (rev) after multiplying rev by 10. So
1 digit is incremented every iteration.
So at the ith iteration n should have m − i digits d1d2.....dm−i & rev
have dmdm−1..........dm−i+1
i n rev
1 d1d2....dm−1 dm
2 d1d2......dm−2 dmdm−1
So on.
Hence (A) is correct option.

65)Consider the following C program segment. (2003)

char p[20];
char)s= “string”;
int length=strlen(s);
for (i=0;i<length; i++)
p[i]=s[length_i];
printf(“% s”, p);
The output of the program is
(A) gnirts (B) string
(C) gnirt (D) no output is printed
SOLUTION
In line 8 p[i]=S[length-i];
Here p is a character pointer variable so we can’t assign the value of a pointer variable into
character variable so no output is printed. The block of code shown here is actually outputs the
reversal of string given in S. Which is a char type pointer. But the mistake during the loop
execution is done. The statement is accessing the
s[length - i] & loop starts from 0 When i = 0, s[length - 0] & s[length]. So this value for string
is always P will start with null pointer. So the string p will start with null pointers and nothing
will be printed.
Hence (D) is correct option.

51
66) A circularly linked list is used to represent a Queue. A single variable p is used to access the
Queue. To which node should p point such that both the operations enQueue and deQueue can
be performed in
constant time ? (2003)
(A) rear node
(B) front node
(C) not possible with a single pointer
(D) node next to front
SOLUTION:
Here due to circular connection the rear & front are connected. Here if we point P to rear the P
"next point to front node & P " data will point to rear value while inserting at rear following
sequence of operations done.
These operation done is 0(1) time So constant complexity.
Hence (A) is correct option.

67) Suppose the numbers 7, 5, 1, 8, 3, 6, 0, 9, 4, 2 are inserted in that

order into an initially empty binary search tree. The binary search
tree uses the usual ordering on natural numbers. What is the inorder
transversal sequence of the resultant tree ?(2003)
(A) 7 5 1 0 3 2 4 6 8 9
(B) 0 2 4 3 1 6 5 9 8 7
(C) 0 1 2 3 4 5 6 7 8 9
(D) 9 8 6 4 2 3 0 1 5 7
SOLUTION
We can solve it in shortcut that the first given element in 7, so we need to choose that particular
option in which 7 is at the right place i.e. all the elements on its left should be smaller than it &
all the elements on the right should be equal & greater than it. So this rule is followed in option
C only. The method to make BST for given inputs is 7, 5, 1, 8, 3, 6, 0, 9, 4, 2.

52
To make in order of a binary search tree.
(i) Start with the root node.
(ii) Scan its left subtree,
(iii) If the node in subtree has any left child then store the node in stack & repeat this step for its
left child unit no. left child of any node.
(iv) If leaf reached then print the node & pop the stack, print the poped value.
(v) Check its right subtree & repeat step (III) for it.
(vi) When stack empty then stop

53
So here inorder is 0 1 2 3 4 5 6 7 8 9. Actually a fact can be remembered that inorder traversal
of a BST leads to a sorted sequence of elements.
Hence (C) is correct option

67) Consider the following 2-3-4 tree (i.e., B-tree with a minimum degree of two in which each
data item is a letter. The usual alphabetical ordering of letters is used in constructing the
tree.(2003)
What is the result of inserting G in the below tree ?

(D) None of the above

SOLUTION

54
2-3-4 B-tree means the min degree of a node is two & it can be max 4 So maximum of 3
elements can be there in a node.

Here in this node the no. of element >3. So we need a split or rotation. Since the adjacent child
has no. of element n 2 2 # = 4 = 2 so we apply a right rotation. So here.

Hence (C) is correct option.

68) The following numbers are inserted into an empty binary search tree in the given order: 10,
1, 3, 5, 15, 12, 16. What is the height of the binary search tree (tree height is the maximum
distance of a leaf node from the root) (2003)
(A) 2
(B) 3
(C) 4
(D) 6
SOLUTION
55
Given are 10, 1, 3, 5, 15, 12, 16

The height of the leaf node (5) is high 3. Hence (B) is correct option.

56
 DESIGN AND ANALYSIS OF ALGORITHMS

1.Consider a linked list of n elements. What is the time taken to insert an element after an element
pointed by some pointer?

A. O (1) B. O (n) C. O (log2 n) D .O (n log2 n)

Answer A

2.An algorithm is made up of two independent time complexities f (n) and g (n). Then the
complexities of the algorithm is in the order of

A. f(n) x g(n) B. Max ( f(n),g(n)) C. Min (f(n),g(n)) D. f(n) + g(n)

Answer B

3.Two main measures for the efficiency of an algorithm are

A. Processor and memory B. Complexity and capacity C. Time and space D. Data and space

Answer C

4.The total number of comparisons in a bubble sort is

A. 0(log n) B. 0(n log n) C. 0(n) D. None of the above

Answer B

5.Time complexities of three algorithms are given. Which should execute the slowest for large
values of N?

A. ( 1 2 ) O N B. O(N) C. O(log N) D. None of these

Answer B

6.The upper bound of computing time of m coloring decision problem is

A. O(nm) B .O(nm) C. O(nmn) D. O(nmmn)

Answer C

7.The space factor when determining the efficiency of algorithm is measured by

A. Counting the maximum memory needed by the algorithm

B. Counting the minimum memory needed by the algorithm

C. Counting the average memory needed by the algorithm

D. Counting the maximum disk space needed by the algorithm

57
Answer A

8.If the address of A[1][1] and A[2][1] are 1000 and 1010 respectively and each element occupies 2
bytes then the array has been stored in _________ order.

A. row major B. column major C. matix major D. none of these

Answer A

9.The time factor when determining the efficiency of algorithm is measured by

A. Counting microseconds

B. Counting the number of key operations

C. Counting the number of statements

D. Counting the kilobytes of algorithm

Answer B

10.The Worst case occur in linear search algorithm when

A. Item is somewhere in the middle of the array

B. Item is not in the array at all

C. Item is the last element in the array

D. Item is the last element in the array or is not there at all

Answer D

11.A list of n strings, each of length n, is sorted into lexicographic order using the merge-sort
algorithm. The worst case running time of this computation is

A. O (n log n) B. O (n2 log n) C. O (n2 + log n) D. O (n2)

Answer A

12.Which of the following case does not exist in complexity theory

A. Best case B. Worst case C. Average case D. Null case

Answer D

13.The minimum number of multiplications and additions required to evaluate the polynomial P =
4x3+3x2-15x+45 is

A. 6 & 3 B. 4 & 2 C. 3 & 3 D. 8 & 3

Answer C

58
14.The concept of order Big O is important because

A. It can be used to decide the best algorithm that solves a given problem

B. It determines the maximum size of a problem that can be solved in a given given amount of time

C. It is the lower bound of the growth rate of algorithm

D. Both A and B

Answer A

15.The worst case running time to search for an element in a balanced binary search tree with n2n
elements is

A. T(nlogn) B. T(n2n) C. T(n) D. T(logn)

Answer C

16.Which of the following sorting algorithm is of divide-and-conquer type?

A. Bubble sort B. Insertion sort C. Quick sort D. All of above

Answer C

17.The quick sort algorithm exploit _________ design technique

A. Greedy B. Dynamic programming C. Divide and Conquer D. Backtracking

Answer C

18.The number of distinct simple graphs with up to three nodes are

A. 15 B. 10 C. 7 D. 9

Answer C

19.The number of unused pointers in a complete binary tree of depth 5 is

A. 4 B. 8 C. 16 D. 32

Answer C

20.A given connected graph G is a Euler graph , if and only if all vertices of G are of

A. Same degree B .Even degree C .Odd degree D. Different degree

Answer B

21.What is the maximum number of nodes in a B-tree of order 10 of depth 3 (root at depth 0) ?

A. 111 B.999 C. 9999 D. None of the above

59
Answer D

22.One can convert a binary tree into its mirror image by traversing it in

A. Inorder B. Preorder C. Postorder D. Any order

Answer C

23.Graphs are represented using

A. Adjacency tree B. Adjacency linked list C. Adjacency graph D. Adjacency queue

Answer B

24.The data structure required for breadth first traversal on a graph is

A. Queue B. Stack C. Array D. Tree

Answer A

25.Number of edges of a complete binary tree with 16 leaf nodes are

A. 14 B. 30 C. 32 D. 28

Answer B

26.Tree
A. Is a bipartite graph
B. With n node contains n-1 edges
C. Is a connected graph
D. All of these
Answer D
27.If every node u in G is adjacent to every other node v in G, A graph is said to be

A. Isolated B. Complete C. Finite D. Strongly Connected

Answer B

28.Consider the following pseudo-code :

If (A > B) and (C > D) then
A=A+1
B=B+1
Endif
The cyclomatic complexity of the pseudo-code is

A. 2 B. 3 C. 4 D. 5

Answer D

29.Leaves of which of the following trees are at the same level ?

60
 A. Binary tree B. B-tree C. AVL-tree D. Expression tree

Answer B

30.The Inorder traversal of the tree will yield a sorted listing of elements of tree in

A. Binary tree B. Binary search tree C. Heaps D. None of the above

Answer B

31.One can make an exact replica of a Binary Search Tree by traversing it in

A. Inorder B. Preorder C. Postorder D. Any order

Answer B

32.Let A be an adjacency matrix of a graph G. The th ij entry in the matrix K A , gives

A. The number of paths of length K from vertex Vi to vertex Vj.

B. Shortest path of K edges from vertex Vi to vertex Vj.

C. Length of a Eulerian path from vertex Vi to vertex Vj.

D. Length of a Hamiltonian cycle from vertex Vi to vertex Vj.

Answer B

33. A graph in which all nodes are of equal degree is called

A. Multi graph B. Non regular graph C. Regular graph D. Complete graph

Answer C

34. The time complexity to build a heap of n elements is

A. 0(1) B. 0(lgn) C. 0(n) D. 0(nlgn)

Answer D

35. Given a binary tree whose inorder and preorder traversal are given by
Inorder : EICFBGDJHK
Preorder : BCEIFDGHJK
The post order traversal of the above binary tree is

A. IEFCGJKHDB B. IEFCJGKHDB C. IEFCGKJHDB D. IEFCGJKDBH

Answer A

36. The running time of the following sorting algorithm depends on whether the partitioning is
balanced or unbalanced

61
 A. Insertion sort B. Selection sort C. Quick sort D. Merge sort

Answer C

37. In worst case Quick Sort has order

A. O (n log n) B. O (n2/2) C. O (log n) D. O (n2/4)

Answer B

38. The sorting technique where array to be sorted is partitioned again and again in such a way
that all elements less than or equal to partitioning element appear before it and those which are
greater appear after it, is called

A. Merge sort B. Quick sort C. Selection sort D. None of these

Answer B

39. The best average behaviour is shown by

A. Quick Sort B. Merge Sort C. Insertion Sort D. Heap Sort

Answer A

40. Quick sort is also known as

A. Merge sort B. Heap sort C. Bubble sort D. None of these

Answer D

41. Assuming P ? NP, which of the following is TRUE?

A. NP-complete = NP B. NP-completenP=theta C. NP-hard = NP D. P = NP-complete

Answer B

42. If there is an NP complete language L whose complement is in NP ,then complement of any

language in NP is in

A. P B. NP C. Both A and B D. None of these

Answer B

43. Both P and NP are closed under the operation of

A. Union B. Intersection C. Concatenation D. Kleene

Answer D

44. If every node u in G is adjacent to every other node v in G, A graph is said to be

A. Isolated
62
B. Complete
C. Finite
D. Strongly Connected

Answer:B

45. Which of the following sorting algorithms has the lowest worst case complexity?

A. Merge sort
B. Bubble sort
C. Quick sort
D. Selection sort
46. Randomized quicksort is an extension of quicksort where the pivot is
chosen randomly. What is the worst case complexity of sorting n
numbers using randomized quicksort?
(a) O(n) (b) O(n log n) (c) O(n2) (d) O(n!)

47. Level of any node of a tree is

A. Height of its left subtree minus height of its right subtree

B. Height of its right subtree minus height of its left subtree
C. Its distance from the root
D. None of these

48. The total number of comparisons in a bubble sort is

A. 0(log n)
B. 0(n log n)
C. 0(n)
D. None of the above
49. Time complexities of three algorithms are given. Which should execute the slowest for
large values of N?

A. ( 1 2 ) O N
B. O(N)
C. O(log N)
D. None of these
50. The quick sort algorithm exploit _________ design technique

63
 A. Greedy
B. Dynamic programming
C. Divide and Conquer
D. Backtracking
51. A sort which relatively passes through a list to exchange the first element with any
element less than it and then repeats with a new first element is called

A. Insertion sort B. Selection sort

C. Heap sort Quick sort

52. The pre order and post order traversal of a Binary Tree generates the same output.
The tree can have maximum

A. Three nodes
B. Two nodes
C. One node
D. Any number of nodes
53. A search technique where we keep expanding nodes with least accumulated cost so far
is called

A. Hill climbing
B. Branch and bound
C. Best first
D. Divide and conquer

54. The spanning tree of connected graph with 10 vertices contains

A. 9 edges B. 11 edges C. 10 edges D.10 vertices

55. The post order traversal of a binary tree is DEBFCA. Find out the preorder
traversal.

A. ABFCDE
B. ADBFEC
C. ABDECF
D. ABDCEF
56. Which of the following statements are TRUE?
(1) The problem of determining whether there exists a cycle in an undirected graph is in
P.
(2) The problem of determining whether there exists a cycle in an undirected graph is in
NP.
64
(3) If a problem A is NP-Complete, there exists a non-deterministic polynomial time
algorithm to solve A.

A. 1,2 and 3 B. 1 and 2 only C. 2 and 3 only D. 1 and 3 only

57. A binary tree can easily be converted into q 2-tree

A. by replacing each empty sub tree by a new internal node

B. by inserting an internal nodes for non-empty node
C. by inserting an external nodes for non-empty node
D. by replacing each empty sub tree by a new external node
58. Which of the following sorting procedures is the slowest?

A. Quick sort
B. Heap sort
C. Shell sort
D. Bubble sort
59. The pre-order and post order traversal of a Binary Tree generates the same output.
The tree can have maximum

A. Three nodes
B. Two nodes
C. One node
D. Any number of nodes
60.

A. A B. B C. C D. D

61. Two isomorphic graphs must have

A. Equal number of vertices

B. Same number of edges
C. Same number of vertices
D. All of the above

62. If each node in a tree has value greater than every value in its left subtree and has
value less than every in the its right subtree ,the tree is called
65
 A. Complete tree B.Full binary tree

C. Binary search tree D. Threaded tree

63. A simple graph in which there exists an edge between pair of vertices is called

A. Regular graph B. Planner graph

C.Euler graph D. Complete graph

64. The best average behaviour is shown by

A. Quick sort B. Merge sort

C.Insertion sort D. Heap sort

65. Which of the following sorting algorithm is of divide-and-conquer type?

A. Bubble sort
B. Insertion sort
C. Quick sort
D. All of above
66. The recurrence relation capturing the optimal execution time of the Towers of Hanoi
problem with n discs is

A. T(n) = 2T(n - 2) + 2
B. T(n) = 2T(n - 1) + n
C. T(n) = 2T(n/2) + 1
D. T(n) = 2T(n - 1) + 1
67.

A. A B. B C. C D. D

68. The goal of hashing is to produce a search that takes

A. O(1) time
B. O(n2 ) time
C. O(log n ) time
D. O(n log n ) time
69. One can make an exact replica of a Binary Search Tree by traversing it in

66
 A. Inorder B. Preorder C. Postorder D. Any order

70. When converting binary tree into extended binary tree, all the original nodes in binary
tree are

A. internal nodes on extended tree

B. external nodes on extended tree
C. vanished on extended tree
D. None of above
71. The postfix form of A*B+C/D is

A. *AB/CD+ B. AB*CD/+
C. A*BC+/D D. ABCD+/*

72. For the bubble sort algorithm, what is the time complexity of the best/worst case?
(assume that the computation stops as soon as no more swaps in one pass)

(a) best case: O(n) worst case: O(n*n)

(b) best case: O(n) worst case: O(n*log(n))
(c) best case: O(n*log(n)) worst case: O(n*log(n))
(d) best case: O(n*log(n)) worst case: O(n*n)

Answer : A

73. For the quick sort algorithm, what is the time complexity of the best/worst case?

(a) best case: O(n) worst case: O(n*n)

(b) best case: O(n) worst case: O(n*log(n))
(c) best case: O(n*log(n)) worst case: O(n*log(n))
(d) best case: O(n*log(n)) worst case: O(n*n)
Answer : D

74. In
an arbitrary tree ( not a search tree) of order M. Its size is N, and its height is K.
The computation time needed to find a data item on T is

(a) O(K*K)
(b) O(M*M)
(c) O(N)
(d) O(K)
Answer : C

67
75. When we organize our data as an ordered list, what is the time complexity of
inserting/deleting a data item to/from the list?

(a) O(length_of_list*length_of_list)
(b) O(length_of_list)
(c) O(log(length_of_list * length_of_list))
(d) O(1)
Answer : B

76. Five statements about B-trees are below. Four of them are correct. Which one is
INCORRECT?

(a) All B-trees are also search trees

(b) The word B-tree stands for balanced tree
(c) The word B-tree also stands for binary tree
(d) All leaves of a B-tree must be on the same level
Answer : C

77. For any B-tree of height H (H>1), after inserting a new key, is it possible for a key, K,
which was located in a leaf-node to move up to the root in this regard which of the
following is correct?

(a) Can’t be defined without data

(b) Never
(c) Yes, only if H=2
(d) Yes
Answer : D

78. When we say the order of a tree is M, we mean

(a) Every non-leaf node must have M subtrees

(b) Every non-leaf node must have M keys
(c) Every non-leaf node can have at most M subtrees
(d) Every non-leaf node can have at most M keys
Answer : C

79. T
is a search tree of order M, its size is N, and its height is K. The computation time
needed to INSERT/DELETE a data item on T is

(a) O( 1 )
(b) O( M )
(c) O( Log K )
(d) O( K )
Answer : D

68
80. Suppose that we have a data file containing records of famous people, and we need to
build a hash table to find a record from the person's birthday. The size of the hash table is
4096. The following are hash functions which convert a birthday to an integer. Which of
the following function is the best?

(a) h1( day/month/year ) = day + month + year

(b) h2( day/month/year ) = day + month*31 + year
(c) h3( day/month/year ) = (day + month*31 + year*365) mod 4096
(d) h4( day/month/year ) = (day + month*31 + year*365) mod 4093
Answer : D

COMPILER DESIGN

1.Which of the following statements is false ?

(A) An unambiguous grammar has same left most and right most derivation
(B) An LL(1) parser is a top-down parser
(C) LALR is more powerful than SLR
(D) An ambiguous grammar can never be LR (K) for any k

SOLUTION
So (A) & (C) are, true.
An ambiguous grammar can’t be LR (K)
So option (A) is false since an unambiguous grammar has unique right most
derivation & left most derivations but both are not same. Hence (A) is correct
option
2. Dynamic linking can cause security concerns because
(A) Security is dynamic
(B) The path for searching dynamic libraries is not known till run time.
(C) Linking is insecure
(D) Cryptographic procedures are not available for dynamic linking

SOLUTION

Dynamic linking is type of linking in which libraries required by the program are linked during
run time. But at this time cryptographic procedures are not available, so make this process
insecure.
Hence (D) is correct option.

3. Which of the following suffices to convert an arbitrary CFG to an LL(1) grammar?

(A) Removing left recursion alone
69
(B) Factoring the grammar alone
(C) Removing left recursion and factoring the grammar
(D) None of this

SOLUTION

If a grammar has left recursion & left factoring then it is ambiguous. So to convert a CFG to
LL(1) grammar both removal of left recursion & left factoring need to be done.
Hence (C) is correct option.

4. Assume that the SLR parser for a grammar G has n1 states and the LALR parser for G has n2
states. The relationship between n1 and n2 is
(A) n1 is necessarily less than n2
(B) n1 is necessarily equal to n2
(C) n1 is necessarily greater than n2
(D) None of the above

SOLUTION

SLR parsue is less range of context free languages than LALR but still both n1 & n2 are same for
SLR & LALR respectively.
Hence (B) is correct option.

5. In a bottom-up evaluation of a syntax directed definition, inherited attributes can

(A) always be evaluated
(B) be evaluated if the definition is L-attributed
(C) be evaluated only if the definition has synthesized attributes
(D) never be evaluated

SOLUTION

Every S (synthesized) -attributed definitions is L- attributed. So in a bottom-up evaluation of

SDD inherited attributes can be evaluated only if the definition has synthesized attributes.
Hence (C) is correct option.

6. Which of the following statements is FALSE?

(A) In statically typed language, each variable in a program has a fixed type
(B) In up-typed languages, values do not have any types
(C) In dynamically typed languages, variables have no types
(D) In all statically typed languages, each variable in a program is associated with values of
only a single type during the execution of the program

70
 SOLUTION

(1) True for statically typed languages where each variable has fixed type. Similarly (4) is also
correct.
(2) True, in un-typed languages types of values are not defined.
But option (C) is false, since in dynamically typed language variables have dynamically
changing types but not that they have no type.
Hence (C) is correct option.

7.Consider the grammar shown below

S " | EtSS' | α
S' " eS |!
E"b
In the predictive parse table M of this grammar the entities M(S) and M[S1,$] respectively are

(A) {s' " eS }and{S' " ε}

(B) {s' " eS}and{}

(C) {s' " ε}and{S' " ε}

(D){s' " eS , S ' " ε}and{ S' " ε}

SOLUTION:D

8. Consider the grammar shown below.

S"CC
C " eC | d
The grammar is
(A) LL (1)
(B) SLR (1) but not LL (1)
(C) LALR (1) but not SLR (1)

(D) LR (1) but not LALR (1)

SOLUTION

Given grammar
S " CC
C "cC d
it can’t be LL since C " cC is recursive. LR(1) also known as CLR parser, and every CF

71
grammar is CLR grammar.
So (A) is false but (C) & (D) can be correct.
This grammar is CLR and also reducible to LALR without any conflicts. So (D) is false.
Only need to check for SLR(1) or LR(0)
This grammar is not SLR.
Hence (C) is correct option

9. Consider the translation scheme shown below

S " TR
R "+ T {print (‘+’);}R | ε

T " num {print (num.val);}

Here num is a token that represents an integer and num. val represents the corresponding
integer value. For an input string ‘9 + 5+ 2’, this translation scheme will print
(A) 9 + 5 + 2 (B) 9 5 + 2 +
(C) 9 5 2 ++ (D) ++ 9 5 2

SOLUTION

S " TR
R "+ T {pr int(' + ');}R ε
T " num{print(num.val);}
Given string 9 + 5 + 2
S " TR

T + TR {print(+);}
T+T+T {print(+);}
9+T+T {print(9);}
9+5 +T {print(5);}
9+5 +2 {print(2);}

So ++ 952 is printed
Hence (D) is correct option.

10. Consider the syntax directed definition shown below

S " id: = E
" newtemp ();
gen(t . place . place;);
.place t}
72
" .place .place;}

Here, gen is a function that generates the output code, and newtemp is a function that returns
the name of a new temporary variable on every call. Assume that t1’s are the temporary variable
names generated by newtemp.
For the statement ‘X: = Y + Z ’, the 3-address code sequence generated by this definition is
(A) X = Y + Z
(B) t1 = Y + Z; X t1
(C) t1 = Y; t2 = t1 + Z; X = t2
(D) t1 = Y; t2 = Z; t3 + t2; X = t3

SOLUTION

In 3-address code we use temporary variables to reduce complex instructions so here

t1 = Y t2 = Z
t 3 = t 1 + t2
x = t3
Hence (D) is correct option.

Solve the problems and choose the correct answers.

The following program fragment is written in a programming language that allows variables
and does not allow nested declarations of functions.

global inti
void
int i
print
i

print
}
main () { (i ) }

11. If the programming language uses static scoping and call by need parameter passing
mechanism, the values printed by the above program are
(A) 115, 220 (B) 25, 220
(C) 25, 15 (D) 115, 105

SOLUTION

In static scoping the variables are initialized at compile time only

73
So i = 100 & j = 5
P (i + j) = P (100 + 5) = P(105)
So x = 105
x + 10 = 105 + 10 = 115
So 115 & 105 will be printed.
Hence (D) is correct option.

12. If the programming language uses dynamic scoping and call by name parameter passing
mechanism, the values printed by the above program are
(A) 115, 220 (B) 25, 220
(C) 25, 15 (D) 115, 105

SOLUTION

In dynamic scoping, the local values are considered & variables are initialized at run time.
Since x = i + j & in P (x)
i = 200 & j = 20 x = 200 + 20 = 220
& printing (x + 10)
x = i + j + 10
= 10 + 5 + 10 = 25

Hence (B) is correct option

13. Consider the following class definitions in a hypothetical object oriented language that
supports inheritance and uses dynamic binding. The language should not be assumed to be
either Java or C++, thought the syntax is similar

Now consider the following program fragment:

P x =new Q();
Q y =new Q();
74
P z =new Q();
x. f (1);((P) y). f (1);z.f(1);
Here ((P) y) denotes a typecast of y to P. The output produced by executing the above program
fragment will be
(A) 1 2 1 (B) 2 1 1
(C) 2 1 2 (D) 2 2 2

SOLUTION

1. Px = newQ();
2. Qy = newQ();
3. Pz = newQ();
4. x : f(1); print 2 # i = 2
5. ((P) y) : f(1);
6. z : f(1) print 2 # i = 2
but line 5. will print 2 because typecast to parent class can’t prevent over ridding. So function
f(1) of class Q will be called not f(1) of class P .
Hence (D) is correct option.

14. Which of the following is NOT an advantage of using shared, dynamically linked libraries
as opposed to using statically linked libraries?
(A) Smaller sizes of executable
(B) Lesser overall page fault rate in the system
(C) Faster program startup
(D) Existing programs need not be re-linked to take advantage of newer versions of libraries

SOLUTION

The advantages of shared dynamically linked libraries include.

(A) smaller size of executable since less data
(B) lesser overall page fault rate.
(C) No need for re-linking if newer versions of libraries are there.
But since compilation time doesn’t include linking so a long linking time required during
runtime in DLL ' s so slow startup.
Hence (C) is correct option.

15. Which of the following grammar rules violate the requirements of an operator grammar? P,
Q, R are non-terminals, and r, s, t are terminals
75
.
(i) P " QR (ii) P " Q s R

(iii) P " ε (iv) P " Q t R r

(A) (i) only (B) (i) and (iii) only
(C) (ii) and (iii) only (D) (iii) and (iv) only

SOLUTION

(I) P " QR is not possible since two NT should include one operator as Terminal.
(II) Correct
(III) Again incorrect. (IV) Correct.
Hence (B) is correct option.

16. Consider a program P that consists of two source modules M1 and M2

contained in two different files. If M1 contains a reference to a function

defined in M2, the reference will be resolved at
(A) Edit-time (B) Compile-time
(C) Link-time (D) Load-time

SOLUTION

The two modules needed to be linked since definition exist & M2 & M1 refers it. So during
linking phase M1 links to M2.
Hence (C) is correct option.

17. Consider the grammar rule E " E1 − E2 for arithmetic expressions. The code generated is
targeted to a CPU having a single user register. The subtraction operation requires the first
operand to be in the register. If E1 and E2 do not have any common sub expression, in order to
get the shortest possible code
(A) E1 should be evaluated first
(B) E2 should be evaluated first
(C) Evaluation of E1 and E2 should necessarily be interleaved
(D) Order of evaluation of E1 and E2 is of no consequence

SOLUTION

E1 is to be kept in accumulator & accumulator is required for operations to evaluate E2 also. So

E2 should be evaluated first & then E1, so finally E1 will be in accumulator, otherwise need to
use move & load instructions.

76
Hence (B) is correct option.

18. Consider the grammar with the following translation rules and E as the start symbol.
E " E 1 #T value = .value * .value}
.value = .value}
" .value = .value + .value}
.value = .value}
"num .value =num.value}
Compute E . value for the root of the parse tree for the expression: 2
# 3 # & 5 # 6 & 4.
(A) 200 (B) 180
(C) 160 (D) 40

SOLUTION

The parse tree would be.

Now we evaluate bottom up

77
LL " left to right left most derivation no ambignity should be there

SLR or LR(0) L to R reverse right sentential form create LR(0) items.

CLR or LR(1) create LR(1) items no bound
LALR reduced CLR if while reducing any conflict found then not
LALR

Hence (C) is correct option.

19. The grammar A " AA |( A)| ε is not suitable for predictive-parsing

78
because the grammar is
(A) ambiguous (B) Left-recursive
(C) right-recurisve (D) an operator-grammar

SOLUTION

The grammar is definitely left & right recursive but it is not suitable for predictive parsing
because it is ambiguous.
Hence (A) is correct option.

20. Consider the grammar E " E + n | E # n | n

For a sentence n + n, the handles in the right-sentential form of the reduction are
(A) n, E + n and E + n # n B) n , E + n and E + E # n

(C) n , n + n and n + n # n (D) n , E + n and E # n

SOLUTION

Given grammar
E "E+n
E "E#n
E "n
String = n + n # n
Right sentential so right most non terminal will be used.
E"E#n {E " E # n}
E+n#n {E " E + n}
n+n#n {E " n}
So during reduction the order is reverse.
So {E " n , E " E + n, E " E # n}
Hence (D) is correct option.
21. Consider the grammar
S " (S)| a
Let the number of states in SLR(1), LR(1) and LALR(1) parsers for the grammar n1 n2 and n3
respectively. The following relationship holds good
(A) n1 < n2 < n3 (B) n1 = n3 < n2
(C) n1 = n2 = n3 (D) n1 $ n3 $ n2

SOLUTION
The no. of states for SLR(1) & LALR(1) are equal so n 1 = n3, but CLR(1) or LR(1) will have no.
of states greater than LALR & LR(0) both.
79
Hence (B) is correct option.

22. Consider line number 3 of the following C-program.

Identify the compiler’s response about this line while creating the object-module
(A) No compilation error
(B) Only a lexical error
(C) Only syntactic errors
(D) Both lexical and syntactic errors

SOLUTION

There are no lexical errors for C because all the wrong spelled keywords would be considered
as identifiers until the syntax is checked.
So the compiler would give syntax errors.
Hence (C) is correct option.

Data for Q. 23 & 24 are given below.

Solve the problems and choose the correct answers.
Consider the following expression grammar. The semantic rules for expression calculation are
stared next to each grammar production.

E " number Eval number val

E E .val E .VAL E .val
E # E E .val E .VAL E .val

23. The above grammar and the semantic rules are fed to a yacc tool (which is an LALR(1)
parser generator) for parsing and evaluating arithmetic expressions. Which one of the following
is true about the action of yacc for the given grammar?
(A) It detects recursion and eliminates recursion
(B) It detects reduce-reduce conflict, and resolves
(C) It detects shift-reduce conflict, and resolves the conflict in favor of a shift over a reduce
80
 action
(D) It detects shift-reduce conflict, and resolves the conflict in favor of a reduce over a shift
action

SOLUTION

Yace tool is used to create a LALR(1) parser. This parser can detect the conflicts but to resolve
the conflicts it actually prefers shift over reduce action.
Hence (C) is correct option.

24. Assume the conflicts part (a) of this question are resolved and an LALR(1) parser is
generated for parsing arithmetic expressions as per the given grammar. Consider an expression
3 # 2 + 1. What precedence and associativity properties does the generated parser realize?
(A) Equal precedence and left associativity; expression is evaluated to 7
(B) Equal precedence and right associativity, expression is evaluated to 9
(C) Precedence of 'x' is higher than that of ‘+’, and both operators are left associative;
expression is evaluated to 7
(D) Precedence of ' # ' is higher than that of ‘#’, and both operators are left associative;
expression is evaluated to 9

SOLUTION

The grammar has equal precedence and it is also ambiguous. Since LALR(1) parser prefer shift
over reduce so + operation will be executed here before ). 2 + 1 = 3 & 3 # 3 = 9 also the
operators are right associative.
Hence (B) is correct option.

25. Consider the following grammar.

S "S*E
S "E
E"F+EE"F
F " id
Consider the following LR(0) items corresponding to the grammar above.
(i) S " S * .E
(ii) E"F.+E
(iii) E " F + .E
Given the items above, which two of them will appear in the same set in the canonical sets-of-
items for the grammar?

81
(A) (i) and (ii) (B) (ii) and (iii)
(C) (i) and (iii) (D) None of these

SOLUTION

If S " S ): E is in LR(0) then E " F +: E will also be there because both of them has ' : ' before E .
Hence (C) is correct option.

26. Consider the following grammar

S " FR
R " * S | ε F " id
In the predictive parser table, M , of the grammar the entries M [ S, id] and M [ R,$] respectively
(A) {S " FR} and {R " ε} (B) {S " FR} and {}
(C) {S " FR} and {R " * S} (D) {F " id} and {R " ε}

SOLUTION

The predictive parser table is given as.

Non Terminal ) id $
S S " FR
F F " id
R R ") S R "! R "!

M [ S, id] =
So at { S " FR}

M [ R,$] = {R "!}
Hence (A) is correct option.

27. Consider the following translation scheme.

S " ER
R " * E{print{’ * ’);R | f
E " F + E{print(’ + ’); | F
F " (S) | id{print(id.value);}

Here id is a taken that represents an integer and id. value represents the corresponding integer
value. For an input ‘2 * 3 + 4’, this translation scheme prints
(A) 2 * 3 + 4 (B) 2 * + 3 4
(C) 2 3 * 4 + (D) 2 3 4 + *
82
SOLUTION
Input string 2 ) 3 + 4

S " ER
FR
idR {print(2)}
id)ER {print())}
id) F+ER {print(+)}id)
id + ER {print(3)} id) id ) id +id
So 2 )+ 3 4 are printed
Hence (B) is correct option.

28. Consider the following C code segment.

for
for
if i
#i
}
}
}

Which one to the following false?

(A) The code contains loop-in variant computation
(B) There is scope of common sub-expression elimination in this code
(C) There is scope strength reduction in this code
(D) There is scope of dead code elimination in this code

SOLUTION

All the statements are true except option (D) since there is no dead code to get eliminated.
Hence (D) is correct option.

29. Which one of the following grammars generates the language

L = (a i b i | i ! j}?

(A) S " AC | CB (B) S " aS | Sb | a | b

C " aCb | a | b
A " aA | ε
B " Bb | ε

(C) S " ACCB (D) S " AC | CB

83
 C " aCb |! C " aCb |!
A " aA |! A " aA | a
B " Bb |! B " bB | b

SOLUTION

The grammar
S " AC CB
C "aCb ! A "aA a B " bB b
Consider string aaabb
S " AC AaCb
AaaCbb
Aaabb aaabb
But string aabb
S " AC
And this string is not derivable. Hence (D) is correct option.

30.In the correct grammar above, what is the length of the derivation
(number of steps starting from S to generate the string al bm with
l ! m?
(A) max (l, m) + 2 (B) l+m+2
(C) l + m + 3 (D) max (l, m) + 3

SOLUTION

It is very clear from the previous solution that the no. of steps required depend upon the no. of
a' s & b ' s which ever is higher & exceeds by 2 due to S " AC CB & C "!
So max(l , m) + 2
Hence (A) is correct option.

31. Which one of the following is a top-down parser?

(A) Recursive descent parser (B) Operator precedence parser
(C) An LR(k) parser (D) An LALR(k) parser

SOLUTION

Clearly LR & LALR are not top down they are bottom up passers. Also not operator
precedence parser.
ut yes recursive descent parser is top down parser. Starts from start symbol & derives the
terminal string.
Hence (A) is correct option.
84
32.Consider the grammar with non-terminals N = {S , C , S}, terminals
T = {a, b , i , t, e}, with S as the start symbol, and the following of rules
S " iCtSS1 | a S1 " eS | ε
C"b
The grammar is NOTLL(1) because:
(A) It is left recursive (B) It is right recursive
(C) It is ambiguous (D) It is not context-free

SOLUTION

The grammar has production

S " iCtSS1 here the right hand side of grammar has the same symbol as left side. So the
grammar is left recursive.
The grammar is not ambiguous. Hence (A) is correct option.

33.Consider the following two statements:

P: Every regular grammar is LL(1)
Q: Every regular set has LR(1) grammar
Which of the following is TRUE?
(A) Both P and Q are true (B) P is true and Q is false
(C) P is false and Q is true (D) Both P and Q are false

SOLUTION

LL(1) parsers can recognize the regular grammars also LL(1) is subset of LR(1) or CLR
grammar so it also recognizes regular sets. So both accept regular grammar.

34. In a simplified computer the instructions are:

OP R j , Ri − Performs Rj OP Ri and stores the result in register Ri
OP m, Ri − Performs val OP Ri abd stores the result in Ri. value
denotes the content of memory location m.
MCVm, Ri −Moves the content off memory loction m to register Ri .
MCVm, Ri , m −Moves the content of register Ri to memory location m.

The computer has only two registers, and OP is either ADD or SUB. Consider the following
basic block:

85
 t1 = a + b t2 = c + d
t 3 = e − t2
t 4 = t 1 − t2
Assume that all operands are initially in memory. The final value of the computation should be
in memory. What is the minimum number of MOV instructions in the code generated for this
basic block?
(A) 2 (B) 3
(C) 5 (D) 6

SOLUTION

The operation sequence would be

MOV a, R1
ADD b , R1 {R 1 = t1
MOV c , R2
ADD d, R2 {R 2 = t2
SUB e , R2 {t 3 = e − R 2 = R2
SUB R 1, R2 {R 2 = t4
MOV R 2, t4 {finally in memory
Totally no. of move operation are 3
Hence (B) is correct option

Data for Q. 35 & 36 are given below.

Solve the problems and choose the correct answers.
Consider the CFG with {S, A, B} as the non-terminal alphabet, {a, b} as the terminal alphabet,
S as the start symbol and the following set of production rules

35.Which of the following strings is generated by the grammar?

(A) aaaabb (B) aabbbb
(C) aabbab (D) abbbba

SOLUTION

aabbab
86
 S " aB
" aaBB
" aabSB
" aabbAB
" aabbab
Hence (C) is correct option.

36.For the correct answer string to Q. 9 how many derivation trees are there?
(A) 1 (B) 2
(C) 3 (D) 4

SOLUTION

For the derivation two trees are possible

So due to ambiguity 2 trees are possible

Hence (B) is correct option.

37. Which of the following describes a handle (as applicable to LR-parsing) appropriately?
(A) It is the position in a sentential form where the next shift or reduce operation will occur
(B) It is a non-terminal whose production will be used for reduction in the next step
(C) It is a production that may be used for reduction in a future step along with a position in the
sentential form where the next shift or reduce operation will occur.
(D) It is the production p that will be used for reduction in the next step along with a position in
the sentential form where the right hand side of the production may be found

SOLUTION

Handles are the part of sentential form, & they are identified as the right side of any given
production which will be used for reduction in the net step.

87
Hence (D) is correct option.

38.Some code optimizations are carried out on the intermediate code because
(A) They enhance the portability of the complier to other target processors
(B) Program analysis is name accurate on intermediate code than on machine code
(C) The information from data flow analysis cannot otherwise be used for optimization
(D) The information from the front end cannot otherwise be used for optimization

SOLUTION

Code optimizations are carried out on the intermediate code

because program analysis is more accurte on intermediate code than on machine code.

Hence (B) is correct option.

39. Which of the following are true?

(i) A programming language option does not permit global variables of any king and has no
nesting of procedures/functions, but permits recursion can be implemented with static
storage allocation
(ii) Multi-level access link (or display) arrangement is needed to arrange activation records-
only if the programming language being implemented has nesting of procedures/function
(iii) Recursion in programming languages cannot be implemented with dynamic storage
allocation
(iv) Nesting of procedures/functions and recursion require a dynamic heap allocation scheme
and cannot be implemented with a stack-based allocation scheme for activation records
(v) Languages which permit a function to return a function as its result cannot be implemented
with a stack-based storage allocation scheme for activation records
(A) (ii) and (v) only (B) (i), (iii) and (iv) only
(C) (i), (ii) and (v) (D) (ii), (iii) and (v) only

SOLUTION

I. Statement is false since global variables are required for

recursions with static storage. This is due to unavailability of stack in static storage.
II. This is true
III. In dynamic allocation heap structure is used, so it is false. IV. False since recursion
can be implemented.
V. Statement is completely true. So only II & V are true.
Hence (A) is correct option.

88
40. An LALR(1) parser for a grammar can have shift-reduce (S-R)
conflicts if and only if
(A) The SLR(1) parser for G has S-R conflicts
(B) The LR(1) parser for G has S-R conflicts
(C) The LR(0) parser for G has S-R conflicts
(D) The LALR(1) parser for G has reduce-reduce conflicts

SOLUTION

LALR parser is reduced form of CLR or LR(1) parser, LALR parser uses the LR(1) items of CLR
parser & of any shift reduce conflicts are there then it is due to LR(1) parser.
Hence (B) is correct option.

41. Which of the following statements are TRUE ?

There exist parsing algorithms 3for some programming languages
hose complex are less than θ(n )
II A programming language which allows recursion can be implemented with static storage
allocation
III No L-attributed definition can be evaluated in the framework of bottom-up parsing
IV Code improving transformations can be performed at both source
language and intermediate code level
(A) I and II (B) I and IV
(C) III and IV (D) I, III and IV

SOLUTION
I. Statement is true since there are some parsers which take
0(n log2n) time for parsing.
II. Completely false, since there is no use of stack which is required for recursion.
III. False
IV. True since both types of optimizations are applied Hence (B) is correct
option.

42.What data structure in a complier is used for managing information about variables and their
attributes?
(A) Abstract syntax tree (B) Symbol table
(C) Semantic stack (D) Parse table

SOLUTION

Symbol table is used for storing the information about variables and their attributes by
89
compiler.
Hence (B) is correct option.

43. Which languages necessarily need heap allocation in the runtime environment ?
(A) Those that support recursion
(B) Those that use dynamic scoping
(C) Those that allow dynamic data structure
(D) Those that use global variables

SOLUTION

Dynamic memory allocation is maintained by heap data structure. So to allow dynamic data
structure heap is required.
Hence (C) is correct option.

OPERATING SYSTEMS

YEAR 2001

Question. 1

Which of the following statements is false ?

(A)Virtual memory implements the translation of a program’s address space into physical memory
address space.
(B)Virtual memory allows each program to exceed the size of the primary memory.
(C)Virtual memory increases the degree of multi-programming
(D)Virtual memory reduces the context switching overhead.

SOLUTION

Virtual memory enables a program to exceed the size of primary memory so it increases degree
of multi-programming.

Since data required by executing program is available here so context switching is reduced.

But virtual memory doesn’t translate program’s address space into physical memory.

Hence (A) is correct option.

Question. 2

90
Consider a set of n tasks with known runtimes r1,r2,........rn to be run on a uniprocessor
machine. Which of the following processor scheduling algorithms will result in the maximum
throughput ?

(A) Round-Robin (B) Shortest-Job-First

(C) Highest-Response-Ratio-Next (D) First-come-First-Served
SOLUTION

Here the running times r1....rn are already known, single processor system. In this scenario,
throughput i.e. CPU is maximum utilized in shortest job first scheduling.

Hence (B) is correct option.

Question. 3

Where does the swap space reside ?

(A) RAM (B) Disk

(C) ROM (D) On-chip cache

SOLUTION

Swap space is the memory space where the part of the program not currently in main memory
for execution is stored, this program part can be swapped into memory when required.

This space is generally in disk.

Hence (B) is correct option.

Question. 4

Consider a virtual memory system with FIFO page replacement policy. For an arbitrary page
access pattern, increasing the number of page frames in main memory will.

(A)Always decrease the number of page faults

(B)Always increase the number of page faults
(C)Sometimes increase the number of page faults
(D)Never affect the number of page faults

SOLUTION

During F1F0 page replacement policy, due to increase in the no. of page frames in memory
should decrease the no. of page faults since more frames can be kept there.

But due to Belady’s Anomaly after certain limit or in some page access instances no. of page
faults are high.

91
Hence (C) is correct option.

Question. 5

Consider a machine with 64 MB physical memory and a 32-bit virtual address space. If the
page size is 4 KB, what is the approximate size of the page table ?

(A) 16 MB (B) 8 MB
(C) 2 MB (D) 24 MB

SOLUTION

Size of main memory = 64 MB

Size of virtual memory = 232 B
No. of pages = 232/212
= 220 pages
Required 1 M enteries.
But each entry has both a virtual address & corresponding physical address.
Total bits in each entry = 32 +26 (Physical) = 58

= 58/8 = 8 Bytes.

So total memory = 8*1 MB= 8 MB

Hence (B) is correct option.

Question. 6

Consider Peterson’s algorithm for mutual exclusion between two concurrent processes i and j.
The program executed by process is shown below.

repeat
flag[i]=true;
turn=j;
while(p)do no-op;
Enter critical section, perform actions, then
exit critical section
Flag[i]=false;
Perform other non-critical section actions.
Until false;

For the program to guarantee mutual exclusion, the predicate P in the while loop should be

(A) flag [j]= true and turn =j (B) flag [j]=true and turn =j
(C) flag [i]=true and turn=j (D) flag [i]=true and turn=i

SOLUTION

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While loop if true predicate then the program enters into critical region. This program enters
into critical region of flag [i]=true act as semaphore, & true =j, the requirement of resource is
by some other process.

Hence (B) is correct option.

YEAR 2002

Question. 7

Which of the following scheduling algorithms is non-preemptive ?

(A) Round Robin
(B) First-In First-Out
(C)Multilevel Queue Scheduling
(D)Multilevel Queue Scheduling with Feedback

SOLUTION

Round robin is preemptive since processes are cycled for CPU time, & run for a particular time
stamp in one cycle. Multilevel queue scheduling maintains various quenes, each having
different priorities. But in FIFO scheme, only the process which enters once, would be
completed first, so no. preemption.

Hence (B) is correct option.Question. 8

The optimal page replacement algorithm will select the page that

(A)Has not been used for the longest time in the past.
(B)Will not be used for the longest time in the future.
(C)Has been used least number of times.
(D)Has been used most number of times

SOLUTION

Optimal page replacement algorithm assumes that the pages that will come in future are already
known, so replacement of the page which will not be used in future occurs.

Hence (B) is correct option.

Question. 9

Which combination of the following features will suffice to characterize an OS as a multi-

programmed OS ? More than one program may be loaded into main memory at the same time
for execution. (B) If a program waits for certain events such as I/O, another program is
immediately scheduled for execution. (C) If the execution of a program terminates, another
program is immediately scheduled for execution.

93
(A) A (B) A and B
(C) A and C (D) A, B and C

SOLUTION

Multi-programmed:- More than one program can run on single CPU, when one is blocked.
(A)Is true and a characteristic of multi-programmed
(B)Is true & also characterize a multi-programmed OS
(C)Is true but no necessary for this type this happens in all OS, even in batch processor.
Hence (B) is correct option.

Question. 10

In the index allocation scheme of blocks to a file, the maximum possible size of the file depends on
(A)The size of the blocks, and the size of the address of the blocks
(B)The number of blocks used for the index, and the size of the blocks.
(C)The size of the blocks, the number of blocks used for the index, and the size of the address of the
blocks.
(D)None of the above.

SOLUTION

When indexes are created, the maximum no. of blocks given to a file are totally dependent upon
size of the index which tells how many blocks can be there, & size of each block.

Hence (B) is correct option.

YEAR 2003

Question. 11

Using a larger block size in a fixed block size file system leads to

(A)better disk throughput but poorer disk space utilization

(B)better disk throughput and better disk space utilization

(C)poorer disk throughput but better disk space utilization

(D)poorer disk throughput and poorer disk space utilization

SOLUTION

Using larger block size in a fixed block size system lead to poor disk space utilization due to
data items which are very small comparable to block size cause fragmentation. But it leads to
better disk through put since no. of blocks needs to fetch & replace become less.

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Hence (A) is correct option.

Question. 12

In a system with 32 bit virtual addresses and 1 KB page size, use of one-level page tables for virtual to
physical address translation is not practical because of
(A)the large amount of internal fragmentation
(B)the large amount of external fragmentation
(C)the large memory overhead in maintaining page tables
(D)the large computation overhead in the translation process

SOLUTION

32 bit virtual address, i.e. 232 kB of virtual memory & 1 kB page size.

So total pages = 232.

So. we need to maintain a page table of 232 rows, this require 4 GB main memory which is quite
impractical due to large memory overhead.

Hence (C) is correct option.

Question. 13

A uni-processor computer system only has two processes, both of which alternate 10 ms CPU
bursts with 90 ms I/O bursts. Both the processes were created at nearly the same time. The I/O
of both processes can proceed in parallel. Which of the following scheduling strategies will
result in the least CPU utilizations (over a long period of time) for this system ?

(A)First come first served scheduling

(B)Shortest remaining time first scheduling
(C)Static priority scheduling with different priorities for the two processes
(D)Round robin scheduling with a time quantum of 5 ms.

SOLUTION

There should be no doubt that round robin scheduling would lead to maximum CPU
utilization, but since in FCFS one task would starve for a long time so min CPU utilization
would be in this case.

Hence (A) is correct option.

Data for Q. 14 & 15 are given below.

A processor uses 2-level page table fro virtual to physical address translation. Page table for
both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide.
The memory is byte addressable. For virtual to physical address translation, the 10 most
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significant bits of the virtual address are used as index into the first level page table while the
next 10 bits are used as index into the second level page table. The 12 least significant bits of
the virtual address are used as offset within the page. Assume that the page table entries in both
levels of page tables are 4 a bytes wide. Further, the processor has a translation look aside
buffer(TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and
the corresponding physical page numbers. The processor also has a physically addressed cache
with a bit ratio of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and {LB
access time is also 1ns.

Question. 14

Assuming that no page faults occur, the average time taken to access a virtual address is
approximately (to the nearest 0.5 ns)

(A) 1.5 ns (B) 2 ns

(C) 3 ns (D) 4 ns

SOLUTION

TLB is successfully 96% of total request & for remaining 4%. RAM is accessed twice.
So average time taken.
=0.96(1 +(0.9*1) +0.1*(1 +10))+0.04(21 +(0.9*0.1)) +0.1*(1 +10)
=.96(1 +.9 +1.1) +0.4(21 +.09 +1.1)
=.96*3 +0.4*23
=2.88 +0.92
=3.80≈4 ns (Nearest .5)
Hence (D) is correct option.
Question. 15

Suppose a process has only the following pages in its virtual address space; two contiguous
code pages starting at virtual address 0x0000000, two contiguous data pages starting at virtual
address 0x00400000, and a stack page starting at virtual address 0xFFFFF000. The amount of
memory required for storing the page tables of this process is

(A)8 KB (B) 12KB (C) 16 KB (D) 20KB

SOLUTION

Total no. of pages required = 5

But due to 2 level page table = 2*4 Kb*2
=16 kB

Hence (D) is correct option.

Data for Q. 16 & 17 are given below.

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Suppose we want to synchronize two concurrent processes P and Q using binary semaphores S
and T. The code for the processes P and Q is shown below.

Process P Process Q:
while(1) { while(1) {
W: Y:
print ‘0’; print ‘1’
print ‘0’; print ‘1’
X: Z:
} }

Synchronization statements can be inserted only at points W, X, Y and Z.

Question. 16

Which of the following will always lead to an output staring with ‘001100110011’?
(A) P(S) at W, V(S) at X, P(T) at Y, V(T) at Z, S and T initially 1
(B) P(S) at W, V(T) at X, P(T) at Y, V(S) at Z, S initially 1, and T initially 0
(C)P(S) at W, V(T) at X, P(T) at Y, V(S) at Z, S and T initially 1
(D)P(S) at W, V(T) at X, P(T) at Y, V(S) at Z, S initially 1, and T initially 0

SOLUTION

For output string 001100110011 alternatingly we require process P & Q to execute.

For this to happen P(s) with S = 1 should be placed at W. At the same time P(T) with T = 0 will be at Y.
At X we have V(T) which will have T = 1 so process Q starts.
At the same time at Z we have V(s) which make S = 0 to stop process P.
Hence (B) is correct option.

Question. 17

Which of the following will ensure that the output string never contains a substring of the form
0.1” or 10”1 where n is odd?

(A)P(S) at W, V(S) at X, P(T) at Y, V(T) at Z, S and T initially 1

(B)P(S) at W, V(T) at X, P(T) at Y, V(S) at Z, S and T initially 1
(C)P(S) at W, V(S) at X, P(T) at Y, V(S) at Z, S initially 1
(D)(S) at W, V(T) at X, P(T) at Y, P(S) at Z, S and T initially 1

SOLUTION

To ensure this condition that substring of form 01n0 or 10n1, where n is odd S should be
initially 1, we will case only 1 semaphore S.

So at W P(s), at X V(s) whereas at Y P(s), at Z V(s)

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Hence (C) is correct option.

YEAR 2004

Question. 18

Consider the following statements with respect to user-level threads and kernel-supported threads
(i)Context which is faster with kernel-supported threads
(ii)For user-level threads. a system call can block the entire process
(iii)Kernel-supported threads can be scheduled independently
(iv)User-level threads are transparent to the kernel
Which of the above statements are true?
(A) (ii),(iii) and (iv) only (B) (ii) and (iii) only
(C) (i) and (iii) only (D) (i) and (ii) only

SOLUTION

(I)It is false, context switch is not faster in support of kernel threads.

(II)A system call can truly block the user level threads, since they don’t have permission to do that.
(III)True since kernel supported threads have their independent memory & resources.
(IV) False since user level threads might need support of kernel threads.
Hence (B) is correct option.

Question. 19

Consider an operating system capable of loading and executing a single sequential user process
at a time. The disk head scheduling algorithm used is First Come First Served (FCFS). If FCFS
is replaced by shortest seek Time Fist (SSTF), claimed by the vendor to given 50% better
beachmark results, what is the expected improvement in the I/O performance of user programs?

(A) 50% (B) 40%

(C) 25% (D) 0%

SOLUTION

I/O performance is not entirely dependent upon disk access, it has effect of various other
devices, so using SSTF in place of FCFS may reduce disk access time but no improvement in
the I/O is done.

Hence (D) is correct option.

Question. 20

The minimum number of page frames that must be allocated to a running process in a virtual
memory environment is determined by

(A)the instruction set architecture

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(B)page size
(C)physical memory size
(D)number of processes in memory

SOLUTION

Page frames are allocated in main memory, for virtual memory pages. This no. of page frames
depends upon the instruction set architecture.

Hence (A) is correct option.

Question. 21

Consider the following set of processes, with the arrival times and the CPU-burst times given in
milliseconds

Process Arrival Time Burst Time

P1 0 5
P2 1 3
P3 2 3
P4 4 1

What is the average turnaround time for these processes with the preemptive shortest remaining
processing time first (SRPT) algorithm?

(A) 5.50 (B) 5.75

(C) 6.00 (D) 6.25

SOLUTION

Then around time = (Submit time −finish time)

Gantt chart for the scheduler.

T.A time for P1 = 12 −0 = 12

P2 = 4 −1 = 3

P3 = 8 −2 = 6
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In order to avoid deadlock, the correct operators at L1, L2, L3 and L4 are respectively

(A) P(Sy),P(Sx);P(Sx),P(Sy) (B) P(Sx),P(Sy);P(Sy),P(Sx)

(C) P(Sx),P(Sx);P(Sy),P(Sy) (D) P(Sx),P(Sy);P(Sx),P(Sy)

SOLUTION

Here semaphores are required to obtain mutual exclusion since both access X & Y . So at L1
P(Sx) which means now Sx = wait at L2P(Sy) Sy wait, this prevents process P2 to start access X
&Y .

V(Sx) & V(Sy) in the end of P1 makes Sx & Sy signal so that at L3 & L4 P(Sx) & P(Sy) can start.

Hence (D) is correct option.

Question. 24

A Unix-style I-node has 10 direct pointers and one single, one double and one triple indirect
pointers. Disk block size is 1 Kbyte, disk block address is 32 bits, and 48-bit integers are used.
What is the maximum possible file size?

(A) 224 bytes (B) 232 bytes (C) 234 bytes (D) 248 bytes

SOLUTION

Size of 1 block = 1 kB
Block addresses size 1 pointer size = 32 bit
= 4 bytes.
So, no. of pointers in= 210B/ 22B
1 block = 256
So direct pointer will have = 10*1kB = 10kB
Double will have = 256*256*1 kB
Triple will have = 256*256*256*1 kB
= 28*28*28*210 B = 234 B
Hence (C) is correct option.
YEAR 2005

Question. 25

Suppose n processes, P1……Pn share m identical resource units, which can be reserved and
released one at a time. The maximum resource requirement of process Pi is sp where si<0.
Which one of the following is a sufficient condition for ensuring that deadlock does not occur?

(A)  i, s < m (B)  i,s,< n

n n
(C) ∑ si < (m +n) (D) ∑ si < (m * n)
i=1 i=1
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SOLUTION

For every Pi Si is maximum resource requirement where Si > 0. To allot resources to all
processes without any deadlock situation is

n
∑ si < (m +n)
i=1

i.e. sum of all maximum resource requirement should be less than m +n.

Hence (C) is correct option.

Question. 26

Consider the following code fragment:

if (fork()==0)

{a = a +5; printf("%d,%/n"a, and a);}

else {a −5; printf("%d,%d/n",a,&a);}

let u, v be the values printed by the parent process, and x,y be the values printed by the child
process. Which one of the following is TRUE?

(A) u = x+10 and v = y (B) u = x+10 and v≠y (C) u+10 = x and v = y (D) u+10 = x and v≠ y

SOLUTION

Initial value of a is let 10 and its address &a would be different for both parent & child process
so.

(A) & (B) are incorrect also parent process executes a = a −5 = 5 = u & child executes a = a +5
= 15 = x so u +10 = x

Hence (D) is correct option.

YEAR 2006

Question. 27

Consider three CPU-intensive processes, which require 10,20 and 30 time units and arrive at
times 0,2, and 6, respectively. How many context switches are needed if the operating system

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implements a shortes remaining time first scheduling algorithm? Do not count the context
switches at time zero and at the end

(A) 1 (B) 2 (C) 3 (D) 4

SOLUTION

When CPU burst are given to another process, called context switching. The Gantt chart for
shortest remaining time first is.

So there are two context & witches at T = 10 & T = 30

Hence (B) is correct option.

Question. 28

The atomic feth-and-set x,y instruction unconditionally sets the memory location x to 1 and
fetches the old value of x in y without allowing any intervening access to the memory location
x. Consider the following implementation of P and V functions on a binary semaphore S.

void p (binary_semaphore*S){
unsigned y;
unsigned*x =& (S->value);}
do {
fetch-and-set x,y;
} while(y);
}
void V (binary_semphore*S){
S_>value = 0;
}

Which one of the following is true?

(A)The implementation may not work if context switching is disabled in P

(B)Instead of using fetch-and-set, a pair of normal load/store can be used

(C)The implementation of V is wrong

(D)The code does not implement a binary semaphore

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SOLUTION

If there are more than two processes and context & switching processes is disabled in P then
this implementation doesn’t work properly and can’t synchronize the processes.

Hence (A) is correct option.

Question. 29

A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a
translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-
way set associative.

The minimum size of the TLB tag is

(A)11bits (B) 13bits (C) 15bits (D) 20bits

SOLUTION

TLB has 128 page table enteries, each page table would have. 64 bits i.e. 32 +32 virtual
addresses.

So total memory required.

27*26

But 4 way set associative.

27*26/22 = 211

So 11 bits are required.

Hence (A) is correct option.

Question. 30

A computer system supports 32-bit virtual addresses as well as 32-bit physical addresses, Since
the virtual address space is of the same size as the physical address space, the operating system
designers decide to get rid of the virtual entirely. Which one of the following is true?

(A)Efficient implementation of multi-user support is no longer possible

(B)The processor cache organization can be made more efficient now

(C)Hardware support for memory management is no longer needed

(D)CPU scheduling can be made more efficient now

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SOLUTION

Since both virtual and physical memory has 32 bit addresses, so there is no need for address
translation hardware is required.

Hence (C) is correct option.

Question. 31

Consider three processes (process id 0,1,2, respectively) with compute time bursts 2,4, and 8
time units. All processes arrive at time zero. Consider the longest remaining time first (LRTF)
scheduling algorithm. In LRTF ties are broken by giving priority to the process with the
lowest process id. The average turn around time is

(A) 13 units (B) 14 units (C) 15 units (D) 16 units

SOLUTION

Process id 0 1 2

CPU Burst 2 4 8

So we draw Gantt chart for scheduler

At t = 0 longest remaining time for P2

At t = 4 remaining times for both P1 & P2 is 4 so P1 is given priority.

At t = 8 remaining time for P0P1 & P2 is 2. P0 is given priority & cyclically done till t = 14.

Process TAT
P0 12 −0 = 12
P1 13 −0 = 13
P2 14 −0 = 14
39/3=13 units

Hence (A) is correct option.

Question. 32

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Consider three processes, all arriving at time zero, with total execution time of 10, 20 and 30
units, respectively. Each process spends the first 20% of execution time doing I/O, the next
70% of time doing computation, and the last 10% of time doing I/O again.The operating system
uses a shortest remaining compute time first scheduling algorithm and schedules a new process
either when the running process get blocked on I/O or when the running process finishes its
compute burst. Assume that all I/O operations can be overlapped as much as possible. For what
percentage of time does the CPU remain idle?

(A) 0% (B) 10.6% (C) 30.0% (D) 89.4%

SOLUTION

Process First I/O Computation Second I/O Total

2 7 1 10
2 4 14 2 20
3 6 21 3 30

Since I/0 can be done parallely.

Gantt chart

Total time taken = 51 units

CPU has to wait = 6 units

=(6/51)*100

=10.6%

Hence (B) is correct option.

Question. 33

106
Consider the following snapshot of a system running n processes. Process i is holding xi
instances of a resource R, for 1≤i≤n. Currently, all instances of R are occupied. Further, for all
i, process i has placed a request for an additional y, instances while holding the xi instances it
already has, There are exactly two processes p and q such that yp = yq = 0: Which one of the
following can serve as a necessary condition to guarantee that the system is not approaching a
deadlock?

(A) min(xp,xq) < maxk≠p,q yk (B) xp+xq ≤ maxk≠p,q yk (C) min(xp,xq) < 1 (D) min(xp,xq)>1

SOLUTION

Here option (B) is that min (xp,xq) < maxk≠ p,q yk

Means the min no. of resources allocated should be less than the maximum number of resources
required by any process other than p & q

It prevent from deadlock.

Hence (B) is correct option.

Data for Q. 34 & 35 are given below.

Barrier is a synchronization construct where a set of processes synchronizes globally i.e. each
process in the set arrives at the barrier and waits for all others to arrive and then all processes
leave the barrier. Let the number of processes in the set be three and S be a binary semaphore
with the usual P and V functions. Consider the following C implementation of a barrier with
line numbers shown on the left.

Void barrier(void) {
1 :P(S)
2 :Process_arrived++;
3 :V (S) :
4 :while (process_arrived’=3);
5 :P(S);
6 :Process_left++;
7 :if(process_left==3)
8 :process_arrived=0;
9 :process_left+0;
10 :}
11 :V(S);
}

The variable process_arrived and process_left are shared among all processes and are initialized
to zero. In a concurrent program all the three processes call the barrier function when they need
to synchronize globally.

Question. 34
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The above implementation of barrier is incorrect. Which one of the following is true?

(A)The barrier implementation is wrong due to the use of binary semaphore S

(B)The barrier implementation may lead to a deadlock if two barrier invocations are used in
immediate succession
(C)Lines 6 to 10 need not be inside a critical section
(D)The barrier implementation is correct if there are only two processes instead of three

SOLUTION

This barrier implementation is to keep track of arrival & completion of processes in system, by
incrementing no. of process arrived & left. This implementation may lead to deadlock if two
barrier function’s invocations are used is immediate sessions.

SinceV(s) in first invocation at line 3 removes 1-3 from critical section bring 5-11 in critical
section at line 7.

Hence (B) is correct option.

Question. 35

Which one of the following rectifies the problem in the implementation?

(A)lines 6 to 10 are simply replaced by process_arrived

(B)At the beginning of the barrier the first process to enter the barrier waits until
process_arrived becomes zero before proceeding to execute P(S)

(C)Context switch is disabled at the beginning of the barrier and re-enabled at the end.

(D)The variable process_left is made private instead of shared

SOLUTION

To rectify the barrier function at the beginning of the functions the first process which inters the
function waits until process arrived becomes zero before executing P(s).

This removes any deadlock situation.

Hence (B) is correct option.

YEAR 2007

Question. 36

Group-1 contains some CPU scheduling algorithms and group-2 contains some applications.

108
Match entries in Group-1 entries in Group-2

Group-1 Group-2
P. Gang Scheduling 1.Guaranteed Scheduling
Q. Rate Monotonic Scheduling 2. Real-time scheduling
R. Fair Share Scheduling 3.Thread Scheduling

(A)P-3 Q-2 R-1 (B) P-1 Q-2 R-3 (C) P-2 Q-3 R-1 (D) P-1 Q-3 R-2

SOLUTION

Rate monotonic scheduling is for real time processes, Gang scheduling is used to schedule
group of program threads and fair share scheduling is a scheduling which guarantees a fair
share of CPU burst to every competing process.

Hence (A) is correct option.

Question. 37

Consider the following statements about user level threads and kernel level threads. Which one
of the following statements is FALSE?

(A)Context switch time is longer for kernel level threads than for user level threads
(B)User level threads do not need any hardware support
(C)Related kernal level thread can be scheduled on different processors in a multiprocessor system
(D) Blocking one kernel level thread blocks all related threads

SOLUTION

Threading a method of executing small sub processes instead of single big process. This
prevents thread from blocking. So blocking of one kernel level thread doesn’t block other
related threads, they are unaffected.

So (D) is false.

Hence (D) is correct option.

Question. 38

An operating system uses Shortest Remaining Time first (SRT) process scheduling algorithm.
Consider the arrival times and execution times for the following processes

Process Execution Time Arrival Time

P1 20 0
P2 25 15
P3 10 30
P4 15 45
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What is the total waiting time for process P2?

(A) 5 (B) 15 (C) 40 (D) 55

SOLUTION

Gantt chart for the processes.

P2 came at t = 15
Scheduled first time at t = 20 wait = 5.
Wait between t = 30 & t = 40 due to short remaining time of new process P3.
Wait now = 5 +10 = 15
Then complete at t = 55
Hence (B) is correct option.

Question. 39

A virtual memory system uses first In First Out (FIFO) page replacement policy and allocates a
fixed number of frames to a process. Consider the following statements:

P:Increasing the number of page frames allocated to a process sometimes increases the page
fault rate.

Q:Some program do not exhibit locality of reference.

Which one of the following is TRUE?

(A)Both P and Q are ture, and Q is the reason for P
(B)Both P and Q are true, but Q is not the reason for P
(C)P is false, but Q is true
(D)Both P and Q are false

SOLUTION

Due to Belady’s Anomaly, increasing the number of page frames allocated to a process
sometimes increase the page fault rate so P is true.

Also some program do not exhibit locality of reference, so both are true but Q is not reason for
P.

Hence (B) is correct option.

110
Question. 40

A single processor system has three resource types X,Y, and Z, which are shared by three
processes. There are 5 units of each resource type. Consider the following scenario, where the
column alloc denotes the number of units of each resource type allocated to each process, and
the column request denotes the number of units of each resource type requested by a process in
order to complete execution. Which of these processes will finish LAST?

alloc request
XYZ XYZ
P0 121 103
P1 201 012
P2 221 120

(A)P0 (B)P1 (C)P2 (D)None of the above,

since the system is in a deadlock

SOLUTION

Initially.

Process Allow Request/need Available

XYZ XYZ XYZ
P0 121 103 012
P1 121 012
P2 221 120

Here looking at available resources, only need of P1 can be completed. So P1 will execute &
free 2 0 1 so now available XYZ = 203.

This is need for P0 so at second no. P0 will execute & free XYZ = 121 so available 3 2 4 & in
the end need of P2 is fulfilled.

Hence (C) is correct option.

Question. 41

Two processes, P1 and P2, need to access a critical section of code. Consider the following
synchronization construct used by the processes:

/* P1 */ /*P2*/
while (true) { while (true) {
wants1=true; wants2 = true;
while(wants2==true); while (wants1 == true);
/* Critical /* Critical

111
 Section Section

*/ */
wants 1 = false; wants 2 = false;
} }
/* Remainder section*/ /*Remainder section*/

Here, wants 1 and wants 2 are shared variables, Which are initialized to false. Which one of the
following statements is TRUE about the above construct?

(A)It does not ensure mutual exclusion.

(B)It does not ensure bounded waiting.
(C)It requires that processes enter the critical section in strict alternation.
(D)It does not prevent deadlocks, but ensures mutual exclusion

SOLUTION

If P1 make wants 1 = true then P2 goes in critical section & vice versa so both together are
implementing mutual exclusion but. Since both are accessing wants 1 & wants 2 concurrently 4
wants 1 is first captured by P1 so P2 will wait & P2 captures want 2 so P1 will have to wait.

So a definite deadlock.

Hence (D) is correct option.

Data for Q. 42 & 43 are given below.

A process has been allocated 3 page frames. Assume that none of the pages of the process are
available in the memory initially. The process makes the following sequence of page references
(reference string): 1,2,1,3,7,4,5,6,3,1.

Question. 42

If optimal page replacement policy is used, how many page faults occur for the above reference
string?

(A) 7 (B)8 (C) 9 (D)10

SOLUTION

Reference string 1, 2, 1, 3, 7, 4, 5, 6, 3, 1

Using optimal replacement policy, we will replace that page in memory which either will not be
used or latest used in future.

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*denotes page fault

So no. of page faults are 7.

Hence (A) is correct option.

Question. 43

Least Recently Used (LRU) page replacement policy is a practical approximation to optimal
page replacement. For the above reference string, how many more page faults occur with LRU
than with the optimal page replacement policy?

(A) 0 (B)1 (C) 2 (D)3

SOLUTION

Instead of optimal policy if we use LRU then we don’t have future knowledge but we replace
that page in memory which has been recently used in past.

Order  1, 2,1, 3, 7, 4, 5, 6, 3,1

*denotes page faults.

In this case no. of page fault = 9
In optimal strategy = 7
Difference = 9 −7 = 2
Hence (C) is correct option.

113
YEAR 2008

Question. 44

Which of the following system calls results in the sending of SYN packets?

(A) socket (B)bind (C) listen (D)connect

SOLUTION

SYN packets are used for synchronization between sender & receiver, these packets are sent by
sender during connect system call for synchronous connection.

Hence (D) is correct option.

Question. 45

The data block of a very large file in the Unix file system are allocated using
(A) Contiguous allocation
(B) Linked allocation
(C) indexed allocation
(D) an extension of indexed allocation

SOLUTION

Generally a large file system for UNIX OS use indexed allocation, but for very large systems an
extension of indexed allocation i.e. ext 2, ext 3 are used.

Hence (D) is correct option.

Question. 46

The P and V operations on counting semaphores, where s is a counting ewmaphore, are defined
as follows:

P(s);s = s −1;
If s < 0 then wait;
V(s): s = s +1;
If s <= 0 then wakeup a process waiting on s;

Assume that Pb and Vb the wait and signal operations on binary semaphores are provided. Two
binary semaphores Xb and Yb are used to implement the semaphore operations P(s) and V(s) as
follows:

P( s ): Pb( Xb );
s = s-1;
if( s <0 ) {
114
 Vb( Xb );
Pb( Yb );
}
else Vb ( Xb );
V( s ): Pb( Xb );
s = s+1;
if( s <= 0 ) Vb( Yb );
Vb( Xb );

The initial values of Xb and Yb are respectively

(A) 0 and 0 (B)0 and 1 (C) 1 and 0 (D)1 and 1

SOLUTION

Xb & Yb are binary semaphores used to implement mutual exclusion here. So when Xb is 1 Yb
should be zero so only 1 code between the two could run.

Since Pb(Xb) module implementing wait process so Xb should be 1. Pb(Yb) implementing signal
s = s +1

So Yb should be 0 initially. Hence (C) is correct option.

Question. 47

Which of the following statements about synchronous and asynchronous I/O is NOT true?

(A) An ISR is invoked on completion of I/O in synchronous I/O but not in asynchronous I/O
(B)In both synchronous and asynchronous I/O an ISR (Interrupt Serive Routine) is
invoked after completion of the I/O
(C) A process making a synchronous I/O cal waits until I/O is complete, but a process making an
asynchronous I/O call does not wait for completion of the I/O
(D) In the case of synchronous I/O, the process waiting for the completion of I/O is woken up by
the ISR that is invoked afterr the completion of I/O

SOLUTION

For the completion of I/0 an interrupt should be generated for CPU in case of both synchronous
& asynchronous I/0 and this ISR call is before them.

So CPU can switch to I/0. Hence (B) is correct option.

Question. 48

Which of the following is NOT true of deadlock prevention and deadlock avoidance schemes?
115
(A) In deadlock prevention, the request for resources is always granted if the resulting state is
safe
(B) In deadlock avoidance, the request for resources is always granted if the resulting state is
safe
(C) Deadlock avoidance is less restrictive than deadlock prevention
(D) Deadlock avoidance requires knowledge of resource requirements a priori

SOLUTION

Both deadlock prevention, & avoidance allocate resources if the resulting state is safe state so
option (A) & (B) are tree. The difference in both schemes is that in avoidance we know the
requirement a prior. But Deadlock avoidance is less restrictive than prevention is false.

Hence (C) is correct option.

Question. 49

A process executes the following code for(i = 0;i < n;i ++) fork();

The total number of child processes created is

(A) n (B)2n-1 (C) 2n (D)2n+1-1

SOLUTION

The loop is called for n times. The first process is parent process so this should not be counted
in child process. But after that every child process has its own child created so after every loop.

20,2',........2n total threads. But subtracting the parent.

Hence (B) is correct option.

Question. 50

A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size
of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual-
to-physical address translation, where the virtual address is used as follows

 bits 30-31 are used to index into the first level page table,
 bits 21-29 are used to index into second level page table
 bits 12-20 are used to index into third level page table
 bits 0-11 are used as offset within the page

The number of bits required for addressing the next level page table(or page frame) in the page
table entry of the first, second and third level page table are respectively
116
(A) 20,20 and 20 (B)24,24 and 24 (C) 24,24 and 20 (D) 25,25 and 24

SOLUTION

Total address single = 36 bit

First level no. of bits = 2*12 = 24 bits
Second level = 4*6 = 24 bits
Third level = 8*3 = 24 bits
Hence (B) is correct option.

YEAR 2009

Question. 51

Consider a system with 4 type of resources R1 (3 units), R2 (2 units), R3 (3 units), R4

(4units). A non-preemptive resource allocation policy is used. At any give instance, a request
is not entertained if it cannot be completely satisfied. Three processes P1, P2, P3 request the
resources as follows if executed independently.

Which one of the following statements is TRUE if all three processes run concurrently starting
at time t = 0 ?

(A)All processes will finish without any deadlock

(B)Only P1 and P2 will be in deadlock

(C)Only P1 and P3 will be in deadlock

(D)All three processes will be in deadlock

SOLUTION

Total resources = 3 2 3 2
117
 Process 1Process 2Process 3Available
Time 1234 1234 1234 1234
0 0200 0020 0001 3011
1 0210 0020 0001 3001
2 0210 0021 2001 1000
3 0210 0021 2001 1000
4 0210 1021 2001 0000
5 1110 1021 0001 1100
6 1110 1011 0001 1110
7 1100 1011 0101 1020
8 1100 0000 0111 2021
9 1102 0000 0000 2130
10 0000 0000 0000 3232

All process computed without deadlock

Hence (A) is correct option.

Question. 52

In which of the following page replacement policies, Belady’s anomaly may occur ?

(A) FIFO (B)Optimal (C) LRU (D)MRU

SOLUTION

Belady’s anomaly is a properly of FIFO page replacement policy in which the no. of page faults
increases even if the no. of page frames are increased in some cases.

Hence (A) is correct option.

Question. 53

The essential content(S) in each entry of a page table is/are

(A)virtual page number

(B)page frame number
(C)Both virtual page number and page frame number
(D)access right information

SOLUTION

A page table is in main memory which mop a page frame to a virtual memory page.
So essential content is page frame number
Hence (B) is correct option.

118
Question. 54

Consider a disk system with 100 cylinders. The requests to access the cylinders occur in
following sequence :

4, 34, 10, 7, 19, 73, 2, 15, 6, 20

Assuming that the head is currently at cylinder 50, what is the time taken to satisfy all requests
if it takes 1 ms to move from one cylinder to adjacent one and shortest seek time first policy is
used?

(A) 95ms (B) 119ms (C) 233ms (D) 276ms

SOLUTION

Arranging in order.

Total = 16 +14 +1 +4 +5 +3 +1 +2 +2 +71 = 119 ms

Hence (B) is correct option.

Question. 55

In the following process state transition diagram for a uniprocessor system, assume that there
are always some processes in the steady state :

Now consider the following statements :

I. If a process makes a transition D, it would result in another process making

transition A immediately
119
 II. A process P2 in blocked state can make transition E while another process P1 is in
running state
III. The OS uses non-preemptive scheduling
IV. The OS uses non-preemptive scheduling

Which of the above statement are TRUE ?

(A) I and II (B) I and III (C) II and III (D) II and IV

SOLUTION

IIs not necessary that a new process enters immediately.

IIIs true different process can be in different states one is ready and another in running state.
IIIIs also correct since if one blocked it stop running so other can run.
IV Is not correct.
Hence (C) is correct option.

Question. 56

The enter_CS( ) and leave_CS( ) functions to implement critical section of a process are
realized using test and set instruction as follows :

Void enter_cs(X)
{
while (test-and-set)(X)) :
}
Void leave_CS(X)
{
X=0;
}

In the above solution, X is a memory location associated with the CS and is initialized to 0.
Now consider the following statements

I. The above solution to CS problem is deadlock-free

II. II The solution is starvation free
III. The processes enter CS in FIFO order
IV. More than one process can enter CS at the same time

Which of the above statements are TRUE

(A) I only (B) I and II (C) II and III (D) IV only

SOLUTION

I Is true since X is initialized to zero, this cause only 1 process to enter into critical so no
deadlock.
120
II & III Are false, other process which doesn’t capture X will wait so ultimately starve.

IV Since I true so it is false.

Hence (A) is correct option.

Question. 57

A multilevel page table is preferred in comparison to a single level page table for translating
virtual address to physical address because

(A) It reduces the memory access time to read or write and memory location

(B) It helps to reduce the size of page table needed to implement the virtual address space
of a process

(C) If is required by the translation look aside buffer

(D) If helps to reduce the number of page faults in page replacement algorithms.

SOLUTION

Single level page table is not preferred since it requires the number of page table entries equal
to the number of virtual memory addresses, but a multilevel page table has smaller number of
entries so reduce the size of page table needed.

Hence (B) is correct option.

YEAR 2010

Question. 58

Consider the methods used by processes P1 and P2 for accessing their critical sections whenever
needed, as given below. The initial values of shared boolean variables S1 and S2 are randomly
assigned.

Method used by P1 Method used by P2

While(S1= = S2) While(S1!= S2)
Critical Section Critical Section
S1= S2; S2= not(S1);

While one of the following statements describes properties achieved?

(A)Mutual exclusion nut nor progress

(B)Progress but not mutual exclusion
(C)Neither mutual exclusion nor progress
121
(D)Both mutual exclusion and progress

SOLUTION

Method used by P1 & P2 enters into critical section when S1 = S2 & S1! = S2 respectively, since
both are opposite conditions so mutual exclusion is there, but if P1's while loop true then it will
always be true & in P2 if while loop true it would run infinitely so no progress.

Hence (A) is correct option.

Question. 59

A system uses FIFO policy for page replacement. It has 4 page frames with no pages loaded to
begin with. The system first accesses 100 distinct pages in some order and then accesses the
same 100 pages but now in the reverse order. How many page faults will occur ?

(A) 196 (B) 192 (C) 197 (D) 195

SOLUTION

In FIFO page replacement policy, the pages which entered first are replaced first so for first 100
accesses, 100 page faults will occur. Now in memory there are last 4 pages 97, 98, 99 & 100th
page.

So during reverse access there 4 pages would not create any page fault & other 97 page faults.

So total 100 +96 = 196 page faults.

Hence (A) is correct option.

Question. 60

Which of the following statements are true ?

I. Shortest remaining time first scheduling may cause starvation

II. Preemptive scheduling may cause starvation
III. Round robin in better than FCFS in terms of response time

(A) I only (B) I and III only (C) II and III only (D) I, II and III

SOLUTION

I. SRIF scheduling may cause starvation since the processes which require large CPU
burst periods would have to wait.
122
 II. Generally preemptive scheduling doesn’t cause starvation but in some cases, it may
cause

starvation when one process doesn’t block due to I/O so others have to wait.

III. It is quite obvious that due to preemption involvement round orbit is better than FCFS,
in

case of response time.

All are true

Hence (D) is correct option.

Question. 61

The following program consists of 3 concurrent processes and 3 binary semaphores. The
semaphores are initialized as S0 = 1, S1 = 0, S2 = 0

Process P0 Process P1 Process P2

while( true ){ wait ( S1 ); wait ( S2 );
wait ( S0 ); release ( S0 ); release ( S0 );
print ‘0’
release ( S1 );
release ( S2 );
}

How many times will process P0 print ‘0’?

(A) At least twice (B) Exactly twice (C) Exactly thrice (D) Exactly
once

SOLUTION

Let us see what will happen initially S0 = 1, S1 = 0 S2 = 0 so P1 & P2 will wait & P0 runs & make S0 = 0 wait
decrements semaphore by 1 & release increments if by 1.
So after P0's 1st run S1 = 1 & S2 = 1 ‘0’ is printed
Now P1 & P2 can run & make S1 = 0, S2 = 0 but both increments S0 = 1 again.
So P0 again starts and print '0' so this would continue again & again.
So '0' will be printed at least twice.
Hence (A) is correct option.

Question. 62

A system has n resources R0..Rn-1, and k processes P0..Pk-1.The implementation of the resource
request logic of each process Pi, is as follows:

if (i%2==0){
123
if(i<n)request Ri;
if(i+2<n) request Ri+2;
}
else {
if (i<n) request Rn-i ;
if (i+2<n) request Rn-i-2;
}

In which one of the following situations is a deadlock possible ?

(A) n=40, k=26 (B) n=21, k=12 (C) n=20 , k=10 (D) n=41, k=19

SOLUTION

Allotment of resources would be successful to all cases but in option

(B) where n = 21 & k = 12.
Let use take i = 10
So for P10 only R10 can be allotted whereas for P11 odd case (else).
R21−11 i.e R10 can only be allotted.
This is an conflict.
Hence (B) is correct option.

DATABASE MANAGEMENT SYSTEMS

1) Which of the following statements are TRUE about an SQL query? (GATE 2012)
P: An SQL query can contain a HAVING clause even if it does not a GROUP BY clause
Q: An SQL query can contain a HAVING clause only if it has a GROUP BY clause
R: All attributes used in the GROUP BY clause must appear in the SELECT clause
S: Not all attributes used in the GROUP BY clause need to apper in the SELECT clause
(A) P and R (B) P and S (C) Q and R (D) Q and S

Answer (B)
P is correct. HAVING clause can also be used with aggregate function. If we use a HAVING
clause without a GROUP BY clause, the HAVING condition applies to all rows that satisfy the
search condition. In other words, all rows that satisfy the search condition make up a single
group. S is correct. To verify S, try following queries in SQL.

CREATE TABLE temp

(
id INT,
name VARCHAR(100)
);

INSERT INTO temp VALUES (1, "abc");

INSERT INTO temp VALUES (2, "abc");
INSERT INTO temp VALUES (3, "bcd");
INSERT INTO temp VALUES (4, "cde");
124
SELECT Count(*)
FROM temp
GROUP BY name;

Output:

count(*)
--------
2
1
1

2) Given the basic ER and relational models, which of the following is INCORRECT?
(GATE 2012)
(A) An attributes of an entity can have more that one value
(B) An attribute of an entity can be composite
(C) In a row of a relational table, an attribute can have more than one value
(D) In a row of a relational table, an attribute can have exactly one value or a NULL value

Answer (C)
The term ‘entity’ belongs to ER model and the term ‘relational table’ belongs to relational
model.
A and B both are true. ER model supports both multivalued and composite attributes

(C) is false and (D) is true. In Relation model, an entry in relational table can can have exactly
one value or a NULL.

3) Suppose (A, B) and (C,D) are two relation schemas. Let r1 and r2 be the corresponding
relation instances. B is a foreign key that refers to C in r2. If data in r1 and r2 satisfy
referential integrity constraints, which of the following is ALWAYS TRUE? (GATE
2012)

Answer (A)
B is a foreign key in r1 that refers to C in r2. r1 and r2 satisfy referential integrity constraints.
So every value that exists in column B of r1 must also exist in column C of r2.

125
4) Which of the following is TRUE? (GATE
2012)
(A) Every relation in 2NF is also in BCNF
(B) A relation R is in 3NF if every non-prime attribute of R is fully functionally dependent on
every key of R
(C) Every relation in BCNF is also in 3NF
(D) No relation can be in both BCNF and 3NF

Answer (C)
BCNF is a stronger version 3NF. So every relation in BCNF will also be in 3NF.

5) Consider the following transactions with data items P and Q initialized to zero:

T1: read (P) ;

read (Q) ;
if P = 0 then Q : = Q + 1 ;
write (Q) ;
T2: read (Q) ;
read (P) ;
if Q = 0 then P : = P + 1 ;
write (P) ;

Any non-serial interleaving of T1 and T2 for concurrent execution leads to (GATE

2012)
(A) A serializable schedule
(B) A schedule that is not conflict serializable
(C) A conflict serializable schedule
(D) A schedule for which a precedence graph cannot be drawn

Answer (B)
Two or more actions are said to be in conflict if:
1) The actions belong to different transactions.
2) At least one of the actions is a write operation.
3) The actions access the same object (read or write).

The schedules S1 and S2 are said to be conflict-equivalent if the following conditions are
satisfied:
1) Both schedules S1 and S2 involve the same set of transactions (including ordering of actions
within each transaction).
2) The order of each pair of conflicting actions in S1 and S2 are the same.

A schedule is said to be conflict-serializable when the schedule is conflict-equivalent to one or

more serial schedules.

In the given scenario, there are two possible serial schedules:

1) T1 followed by T2
2) T2 followed by T1.
In both of the serial schedules, one of the transactions reads the value written by other

126
transaction as a first step. Therefore, any non-serial interleaving of T1 and T2 will not be
conflict serializable.

6) Consider the following relations A, B, C. How many tuples does the result of the
following relational algebra expression contain? Assume that the schema of A U B is the
same as that of A. (GATE 2012)

Table A
Id Name Age
----------------
12 Arun 60
15 Shreya 24
99 Rohit 11

Table B
Id Name Age
----------------
15 Shreya 24
25 Hari 40
98 Rohit 20
99 Rohit 11

Table C
Id Phone Area
-----------------
10 2200 02
99 2100 01

(A) 7
(B) 4
(C) 5
(D) 9

Answer (A)

Result of AUB will be following table

Id Name Age
----------------
12 Arun 60
15 Shreya 24
99 Rohit 11
25 Hari 40
98 Rohit 20

The result of given relational algebra expression will be

127
Id Name Age Id Phone Area
---------------------------------
12 Arun 60 10 2200 02
15 Shreya 24 10 2200 02
99 Rohit 11 10 2200 02
25 Hari 40 10 2200 02
98 Rohit 20 10 2200 02
99 Rohit 11 99 2100 01
98 Rohit 20 99 2100 01

7) Consider the above tables A, B and C. How many tuples does the result of the following
SQL query contains? (GATE 2012)

SELECT A.id
FROM A
WHERE A.age > ALL (SELECT B.age
FROM B
WHERE B. name = "arun")

(A) 4
(B) 3
(C) 0
(D) 1

Answer (B)
The meaning of “ALL” is the A.Age should be greater than all the values returned by the
subquery. There is no entry with name “arun” in table B. So the subquery will return NULL. If
a subquery returns NULL, then the condition becomes true for all rows of A So all rows of
table A are selected.

8. Consider a relational table with a single record for each registered student with the
following attributes.

1. Registration_Number:< Unique registration number for each registered student

2. UID: Unique Identity number, unique at the national level for each citizen
3. BankAccount_Number: Unique account number at the bank. A student can have
multiple accounts or joint accounts. This attributes stores the primary account number
4. Name: Name of the Student
5. Hostel_Room: Room number of the hostel

Which of the following options is INCORRECT? (GATE 2011)

(A) BankAccount_Number is a candidate key
(B) Registration_Number can be a primary key
(C) UID is a candidate key if all students are from the same country
(D) If S is a superkey such that S UID is NULL then S UID is also a superkey

128
Answer (A)
A Candidate Key value must uniquely identify the corresponding row in table.
BankAccount_Number is not a candidate key. As per the question “A student can have multiple
accounts or joint accounts. This attributes stores the primary account number”. If two students
have a joint account and if the joint account is their primary account, then
BankAccount_Number value cannot uniquely identify a row.

9) Consider a relational table r with sufficient number of records, having attributes A1,
A2,…, An and let 1 <= p <= n. Two queries Q1 and Q2 are given below.

The database can be configured to do ordered indexing on Ap or hashing on Ap. Which of

the following statements is TRUE? (GATE 2011)
(A) Ordered indexing will always outperform hashing for both queries
(B) Hashing will always outperform ordered indexing for both queries
(C) Hashing will outperform ordered indexing on Q1, but not on Q2
(D) Hashing will outperform ordered indexing on Q2, but not on Q1.

Answer (C)
If record are accessed for a particular value from table, hashing will do better. If records are
accessed in a range of values, ordered indexing will perform better. See this for more details.

10) Database table by name Loan_Records is given below.

Borrower Bank_Manager Loan_Amount

Ramesh Sunderajan 10000.00
Suresh Ramgopal 5000.00
Mahesh Sunderajan 7000.00

What is the output of the following SQL query? (GATE 2011)

SELECT Count(*)
FROM ( (SELECT Borrower, Bank_Manager
FROM Loan_Records) AS S
NATURAL JOIN (SELECT Bank_Manager,
Loan_Amount
FROM Loan_Records) AS T );

(A) 3
(B) 9
(C) 5
(D) 6

129
Answer (C)

Following will be contents of temporary table S

Borrower Bank_Manager
--------------------------
Ramesh Sunderajan
Suresh Ramgqpal
Mahesh Sunderjan

Following will be contents of temporary table T

Bank_Manager Loan_Amount
---------------------------
Sunderajan 10000.00
Ramgopal 5000.00
Sunderjan 7000.00

Following will be the result of natural join of above two tables. The key thing to note is that the
natural join happens on column name with same name which is Bank_Manager in the above
example. “Sunderjan” appears two times in Bank_Manager column, so their will be four entries
with Bank_Manager as “Sunderjan”.

Borrower Bank_Manager Load_Amount

------------------------------------
Ramesh Sunderajan 10000.00
Ramesh Sunderajan 7000.00
Suresh Ramgopal 5000.00
Mahesh Sunderajan 10000.00
Mahesh Sunderajan 7000.00

11) the table at any point in time. Using MX and MY, new records are inserted in the
table 128 times with X and Y values being MX+1, 2*MY+1 respectively. It may be noted
that each time after the insertion, values of MX and MY change. What will be the output
of the following SQL query after the steps mentioned above are carried out?
(GATE 2011)

SELECT Y FROM T WHERE X=7;

(A) 127
(B) 255
(C) 129
(D) 257

Answer (A)

X Y
-------
1 1
130
 2 3
3 7
4 15
5 31
6 63
7 127
......
......

12) A relational schema for a train reservation database is given below.

Passenger (pid, pname, age)
Reservation (pid, class, tid)

Table: Passenger
pid pname age
-----------------
0 Sachin 65
1 Rahul 66
2 Sourav 67
3 Anil 69

Table : Reservation
pid class tid
---------------
0 AC 8200
1 AC 8201
2 SC 8201
5 AC 8203
1 SC 8204
3 AC 8202

What pids are returned by the following SQL query for the above instance of the tables?
(GATE 2010)

SLECT pid
FROM Reservation ,
WHERE class ‘AC’ AND
EXISTS (SELECT *
FROM Passenger
WHERE age > 65 AND
Passenger. pid = Reservation.pid)

(A) 1, 0
(B) 1, 2
(C) 1, 3
(S) 1, 5

Answer (C)
When a subquery uses values from outer query, the subquery is called correlated subquery. The
correlated subquery is evaluated once for each row processed by the outer query.

131
The outer query selects 4 entries (with pids as 0, 1, 5, 3) from Reservation table. Out of these
selected entries, the subquery returns Non-Null values only for 1 and 3.

13) Which of the following concurrency control protocols ensure both conflict
serialzability and freedom from deadlock?
I. 2-phase locking
II. Time-stamp ordering (GATE 2010)
(A) I only
(B) II only
(C) Both I and II
(D) Neither I nor II

Answer (B)
2 Phase Locking (2PL) is a concurrency control method that guarantees serializability. The
protocol utilizes locks, applied by a transaction to data, which may block (interpreted as signals
to stop) other transactions from accessing the same data during the transaction’s life. 2PL may
be lead to deadlocks that result from the mutual blocking of two or more transactions. See the
following situation, neither T3 nor T4 can make progress.

Timestamp-based concurrency control algorithm is a non-lock concurrency control method. In

Timestamp based method, deadlock cannot occur as no transaction ever waits.

14) Consider the following schedule for transactions T1, T2 and T3:

Which one of the schedules below is the correct serialization of the above? (GATE
2010)
(A)T1 T3 T2
132
(B)T2 T1 T3
(C)T2 T3 T1
(D)T3 T1 T2

Answer (A)
T1 can complete before T2 and T3 as there is no conflict between Write(X) of T1 and the
operations in T2 and T3 which occur before Write(X) of T1 in the above diagram.
T3 should can complete before T2 as the Read(Y) of T3 doesn’t conflict with Read(Y) of T2.
Similarly, Write(X) of T3 doesn’t conflict with Read(Y) and Write(Y) operations of T2.
Another way to solve this question is to create a dependency graph and topologically sort the
dependency graph. After topologically sorting, we can see the sequence T1, T3, T2.

15) The following functional dependencies hold for relations R(A, B, C) and S(B, D, E):
B A,
A C
The relation R contains 200 tuples and the rel ation S contains 100 tuples. What is the
maximum number of tuples possible in the natural join R S (R natural join S)

(GATE 2010)
(A) 100
(B) 200
(D) 300
(D) 2000

Answer (A)
From the given set of functional dependencies, it can be observed that B is a candidate key of
R. So all 200 values of B must be unique in R. There is no functional dependency given for S.
To get the maximum number of tuples in output, there can be two possibilities for S.
1) All 100 values of B in S are same and there is an entry in R that matches with this value. In
this case, we get 100 tuples in output.
2) All 100 values of B in S are different and these values are present in R also. In this case also,
we get 100 tuples.

16) Consider two transactions T1 and T2, and four schedules S1, S2, S3, S4 of T1 and T2
as given below:
T1 = R1[X] W1[X] W1[Y]
T2 = R2[X] R2[Y] W2[Y]
S1 = R1[X] R2[X] R2[Y] W1[X] W1[Y] W2[Y]
S2 = R1[X] R2[X] R2[Y] W1[X] W2[Y] W1[Y]
S3 = R1[X] W1[X] R2[X] W1[Y] R2[Y] W2[Y]
S1 = R1[X] R2[Y]R2[X]W1[X] W1[Y] W2[Y]
Which of the above schedules are conflict-serializable? (GATE: 2009)
(A) S1 and S2
(B) S2 and S3

133
(C) S3 only
(D) S4 only

Answer (B)
There can be two possible serial schedules T1 T2 and T2 T1. The serial schedule T1 T2 has the
following sequence of operations
R1[X] W1[X] W1[Y] R2[X] R2[Y] W2[Y]
And the schedule T2 T1 has the following sequence of operations.
R2[X] R2[Y] W2[Y] R1[X] W1[X] W1[Y]
The Schedule S2 is conflict-equivalent to T2 T1 and S3 is conflict-equivalent to T1 T2.

17) Let R and S be relational schemes such that R={a,b,c} and S={c}. Now consider
the following queries on the database:

IV) SELECT R.a, R.b

FROM R,S
WHERE R.c=S.c

Which of the above queries are equivalent? (GATE: 2009)

(A) I and II
(B) I and III
(C) II and IV
(D) III and IV

Answer (A)
I and II describe the division operator in Relational Algebra and Tuple Relational Calculus
respectively. See Page 3 of this and slide numbers 9,10 of this for more details.

18) Consider the following relational schema:

Suppliers(sid:integer, sname:string, city:string, street:string)

Parts(pid:integer, pname:string, color:string)
Catalog(sid:integer, pid:integer, cost:real)

Consider the following relational query on the above database:

SELECT S.sname
FROM Suppliers S
WHERE S.sid NOT IN (SELECT C.sid
FROM Catalog C
WHERE C.pid NOT IN (SELECT P.pid

134
 FROM Parts P
WHERE P.color<> 'blue'))

Assume that relations corresponding to the above schema are not empty. Which one of the
following is the correct interpretation of the above query? (GATE: 2009)

(A) Find the names of all suppliers who have supplied a non-blue part.
(B) Find the names of all suppliers who have not supplied a non-blue part.
(C) Find the names of all suppliers who have supplied only blue parts.
(D) Find the names of all suppliers who have not supplied only blue parts.

Answer (B)
The subquery “SELECT P.pid FROM Parts P WHERE P.color<> ‘blue’” gives pids of parts
which are not blue. The bigger subquery “SELECT C.sid FROM Catalog C WHERE C.pid NOT
IN (SELECT P.pid FROM Parts P WHERE P.color<> ‘blue’)” gives sids of all those suppliers
who have supplied blue parts. The complete query gives the names of all suppliers who have
not supplied a non-blue part

19) Assume that, in the suppliers relation above, each supplier and each street within a
city has a unique name, and (sname, city) forms a candidate key. No other functional
dependencies are implied other than those implied by primary and candidate keys. Which
one of the following is TRUE about the above schema? (GATE: 2009)
(A) The schema is in BCNF
(B) The schema is in 3NF but not in BCNF
(C) The schema is in 2NF but not in 3NF
(D) The schema is not in 2NF

Answer (A)
The schema is in BCNF as all attributes depend only on a superkey (Note that primary and
candidate keys are also superkeys).

20) Let R and S be two relations with the following schema

R (P,Q,R1,R2,R3)
S (P,Q,S1,S2)
Where {P, Q} is the key for both schemas. Which of the following queries are equivalent?
(GATE: 2008)

(A) Only I and II

(B) Only I and III
(C) Only I, II and III
(D) Only I, III and IV
135
Answer (D)
In I, Ps from natural join of R and S are selected.
In III, all Ps from intersection of (P, Q) pairs present in R and S.
IV is also equivalent to III because (R – (R – S)) = R S.
II is not equivalent as it may also include Ps where Qs are not same in R and S.

21) Consider the following ER diagram. (GATE: 2008)

The minimum number of tables needed to represent M, N, P, R1, R2 is

(A) 2
(B) 3
(C) 4
(D) 5

Answer (A)
Many-to-one and one-to-many relationship sets that are total on the many-side can be
represented by adding an extra attribute to the “many” side, containing the primary key of the
“one” side. Since R1 is many to one and participation of M is total, M and R1 can be combined
to form the table {M1, M2, M3, P1}. N is a week entity set, so it can be combined with P.

22) Which of the following is a correct attribute set for one of the tables for the correct
answer to the above question? (GATE: 2008)
(A) {M1, M2, M3, P1}
(B) {M1, P1, N1, N2}
(C) {M1, P1, N1}
(D) {M1, P1}

Answer (A)

23) Consider the following relational schemes for a library database:

Book (Title, Author, Catalog_no, Publisher, Year, Price)
Collection (Title, Author, Catalog_no)

with in the following functional dependencies:

136
I. Title Author --> Catalog_no
II. Catalog_no --> Title Author Publisher Year
III. Publisher Title Year --> Price

Assume {Author, Title} is the key for both schemes. Which of the following statements is
true? (GATE: 2008)
(A) Both Book and Collection are in BCNF
(B) Both Book and Collection are in 3NF only
(C) Book is in 2NF and Collection is in 3NF
(D) Both Book and Collection are in 2NF only

Answer (C)
Table Collection is in BCNF as there is only one functional dependency “Title Author –>
Catalog_no” and {Author, Title} is key for collection. Book is not in BCNF because
Catalog_no is not a key and there is a functional dependency “Catalog_no –> Title Author
Publisher Year”. Book is not in 3NF because non-prime attributes (Publisher Year) are
transitively dependent on key [Title, Author]. Book is in 2NF because every non-prime attribute
of the table is either dependent on the key [Title, Author], or on another non prime attribute.

24) Information about a collection of students is given by the relation studinfo(studId,

name, sex). The relation enroll(studId, courseId) gives which student has enrolled for (or
taken) that course(s). Assume that every course is taken by at least one male and at least
one female student. What does the following relational algebra expression represent?

(GATE: 2007)

(A) Courses in which all the female students are enrolled.

(B) Courses in which a proper subset of female students are enrolled.
(C) Courses in which only male students are enrolled.
(D) None of the above

Answer (B)
The expression given in question does following steps in sequence.
a) Select studids of all female students and selects all courseids of all courses.
b) Then the query does a Cartesian Product of the above select two columns from different
tables.
c) Finally it subtracts enroll table from the result of above step (b). This will remove all the
(studid, courseid) pairs which are present in enroll table. If all female students have registered
in a courses, then this course will not be there in the subtracted result.
So the complete expression returns courses in which a proper subset of female students are
enrolled.

studinfo table
studid name sex
137
------------------------
1 a Male
2 c Female
3 d Female

enroll table
studid courseid
------------------
1 1
2 1
3 1
2 2
3 3
3 2

Result of step b
studid courseid
---------------------
2 1
2 2
2 3
3 1
3 2
3 3

Result of step c
studid courseid
-------------------
2 3

25) Consider the relation employee(name, sex, supervisorName) with name as the key.
supervisorName gives the name of the supervisor of the employee under consideration.
What does the following Tuple Relational Calculus query produce? (GATE: 2007)

(A) Names of employees with a male supervisor.

(B) Names of employees with no immediate male subordinates.
(C) Names of employees with no immediate female subordinates.
(D) Names of employees with a female supervisor.

Answer (C)
The query selects all those employees whose immediate subordinate is “male”. In other words,
it selects names of employees with no immediate female subordinates

26) Consider the table employee(empId, name, department, salary) and the two queries
138
Q1 ,Q2 below. Assuming that department 5 has more than one employee, and we want to
find the employees who get higher salary than anyone in the department 5, which one of
the statements is TRUE for any arbitrary employee table? (GATE: 2007)

Q1 : Select e.empId
From employee e
Where not exists
(Select * From employee s where s.department = “5” and
s.salary >=e.salary)
Q2 : Select e.empId
From employee e
Where e.salary > Any
(Select distinct salary From employee s Where s.department = “5”)

(A) Q1 is the correct query

(B) Q2 is the correct query
(C) Both Q1 and Q2 produce the same answer.
(D) Neither Q1 nor Q2 is the correct query

Answer (D)
Consider the following example table.

empid name department salary

1 a 4 90k
2 b 5 30k
3 c 5 50k
4 d 5 80k

Q1 will give empid 1

Q2 will give empid 1, 3, 4
But the correct answer is 4

27) Which one of the following statements if FALSE? (GATE: 2007)

(A) Any relation with two attributes is in BCNF
(B) A relation in which every key has only one attribute is in 2NF
(C) A prime attribute can be transitively dependent on a key in a 3 NF relation.
(D) A prime attribute can be transitively dependent on a key in a BCNF relation.

Answer (D)

28) Consider the following schedules involving two transactions. Which one of the
following statements is TRUE? (GATE: 2007)

139
(A) Both S1 and S2 are conflict serializable.
(B) S1 is conflict serializable and S2 is not conflict serializable.
(C) S1 is not conflict serializable and S2 is conflict serializable.
(D) Both S1 and S2 are not conflict serializable.

Answer (C)
S1 is not conflict serializable, but S2 is conflict serializable

Schedule S1
T1 T2
---------------------
r1(X)
r1(Y)
r2(X)
r2(Y)
w2(Y)
w1(X)
The schedule is neither conflict equivalent to T1T2, nor T2T1.

Schedule S2
T1 T2
---------------------
r1(X)
r2(X)
r2(Y)
w2(Y)
r1(Y)
w1(X)
The schedule is conflict equivalent to T2T1.

29) Consider the following log sequence of two transactions on a bank account, with initial
balance 12000, that transfer 2000 to a mortgage payment and then apply a 5% interest.

1. T1 start
2. T1 B old=12000 new=10000
3. T1 M old=0 new=2000
4. T1 commit
5. T2 start
6. T2 B old=10000 new=10500
7. T2 commit
Suppose the database system crashes just before log record 7 is written. When the system is
restarted, which one statement is true of the recovery procedure? (GATE: 2006)

(A) We must redo log record 6 to set B to 10500

(B) We must undo log record 6 to set B to 10000 and then redo log records 2 and 3
(C) We need not redo log records 2 and 3 because transaction T1 has committed
(D) We can apply redo and undo operations in arbitrary order because they are idempotent.

Answer (C)
Once a transaction is committed, no need to redo or undo operations.
140
30) Consider the relation enrolled (student, course) in which (student, course) is the
primary key, and the relation paid (student, amount) where student is the primary key.
Assume no null values and no foreign keys or integrity constraints. Given the following
four queries:

Query1: select student from enrolled where student in (select student from
paid)
Query2: select student from paid where student in (select student from
enrolled)
Query3: select E.student from enrolled E, paid P where E.student = P.student
Query4: select student from paid where exists
(select * from enrolled where enrolled.student = paid.student)

Which one of the following statements is correct? (GATE : 2006)

(A) All queries return identical row sets for any database
(B) Query2 and Query4 return identical row sets for all databases but there exist databases for
which Query1 and Query2 return different row sets.
(C) There exist databases for which Query3 returns strictly fewer rows than Query2.
(D) There exist databases for which Query4 will encounter an integrity violation at runtime.

Answer (A)
The output of Query2, Query3 and Query4 will be identical. Query1 may produce duplicate
rows. But rowset produced by all of them will be same.

Table enrolled
student course
----------------
abc c1
xyz c1
abc c2
pqr c1

Table paid
student amount
-----------------
abc 20000
xyz 10000
rst 10000

Output of Query 1
abc
abc
xyz

Output of Query 2
abc
xyz

Output of Query 3
141
 abc
xyz

Output of Query 4
abc
xyz

31) Consider the relation enrolled(student, course) in which (student, course) is the
primary key, and the relation paid(student, amount), where student is the primary key.
Assume no null values and no foreign keys or integrity constraints. Assume that amounts
6000, 7000, 8000, 9000 and 10000 were each paid by 20% of the students. Consider these
query plans (Plan 1 on left, Plan 2 on right) to “list all courses taken by students who have
paid more than x”.

A disk seek takes 4ms, disk data transfer bandwidth is 300 MB/s and checking a tuple to
see if amount is greater than x takes 10 micro-seconds. Which of the following statements
is correct? (GATE: 2006)
(A) Plan 1 and Plan 2 will not output identical row sets for all databases.
(B) A course may be listed more than once in the output of Plan 1 for some databases
(C) For x = 5000, Plan 1 executes faster than Plan 2 for all databases.
(D) For x = 9000, Plan I executes slower than Plan 2 for all databases.

Answer (C)
Assuming that large enough memory is available for all data needed. Both plans need to load
both tables courses and enrolled. So disk access time is same for both plans.
Plan 2 does lesser number of comparisons compared to plan 1.
1) Join operation will require more comparisons as the second table will have more rows in plan
2 compared to plan 1.
2) The joined table of two tables will will have more rows, so more comparisons are needed to
find amounts greater than x.

142
32) The following functional dependencies are given:

AB CD, AF D, DE F, C G , F E, G A

Which one of the following options is false? (GATE: 2006)

(A)CF+ = {ACDEFG}
(B)BG+ = {ABCDG}
(C)AF+ = {ACDEFG}
(D)AB+ = {ABCDFG}

Answer (C)
Closure of AF or AF+ = {ADEF}, closure of AF doesn’t contain C and G.
Option (D) also looks correct. AB+ = {ABCDG}, closure of AB doesn’t contain F.

33) Which one of the following statements about normal forms is FALSE? (GATE 2005)
(a) BCNF is stricter than 3NF
(b) Lossless, dependency-preserving decomposition into 3NF is always possible
(c) Lossless, dependency-preserving decomposition into BCNF is always possible
(d) Any relation with two attributes is in BCNF

Answer (c)
It is not always possible to decompose a table in BCNF and preserve dependencies. For
example, a set of functional dependencies {AB –> C, C –> B} cannot be decomposed in BCNF.

34) The following table has two attributes A and C where A is the primary key and C is
the foreign key referencing A with on-delete cascade.

A C
-----
2 4
3 4
4 3
5 2
7 2
9 5
6 4

The set of all tuples that must be additionally deleted to preserve referential integrity
when the tuple (2,4) is deleted is: (GATE
2005)
(a) (3,4) and (6,4)
(b) (5,2) and (7,2)
(c) (5,2), (7,2) and (9,5)
(d) (3,4), (4,3) and (6,4)

Answer (C)
When (2,4) is deleted. Since C is a foreign key referring A with delete on cascade, all entries
143
with value 2 in C must be deleted. So (5, 2) and (7, 2) are deleted. As a result of this 5 and 7 are
deleted from A which causes (9, 5) to be deleted.

35) The relation book (title, price) contains the titles and prices of different books.
Assuming that no two books have the same price, what does the following SQL query list?
(GATE 2005)

select title
from book as B
where (select count(*)
from book as T
where T.price > B.price) < 5

(a) Titles of the four most expensive books

(b) Title of the fifth most inexpensive book
(c) Title of the fifth most expensive book
(d) Titles of the five most expensive books

Answer (d)
When a subquery uses values from outer query, the subquery is called correlated subquery. The
correlated subquery is evaluated once for each row processed by the outer query.
The outer query selects all titles from book table. For every selected book, the subquery returns
count of those books which are more expensive than the selected book. The where clause of
outer query will be true for 5 most expensive book. For example count (*) will be 0 for the most
expensive book and count(*) will be 1 for second most expensive book.

36) Let r be a relation instance with schema R = (A, B, C, D). We define r1 = ‘select A,B,C
from r’ and r2 = ‘select A, D from r’. Let s = r1 * r2 where * denotes natural join. Given
that the decomposition of r into r1 and r2 is lossy, which one of the following is TRUE?
(GATE 2005)
(a) s is subset of r
(b) r U s = r
(c) r is a subset of s
(d) r * s = s

Answer (c)
Consider the following example with lossy decomposition of r into r1 and r2. We can see that r
is a subset of s.

Table r
A B C D
---------------------------
1 10 100 1000
1 20 200 1000
1 20 200 1001

Table r1

144
 A B C
------------------
1 10 100
1 20 200

Table r2
A D
-----------
1 1000
1 1001

Table s (natural join of r1 and r2)

A B C D
---------------------------
1 10 100 1000
1 20 200 1000
1 20 100 1001
1 20 200 1001

37) Let E1 and E2 be two entities in an E/R diagram with simple single-valued attributes.
R1 and R2 are two relationships between E1 and E2, where R1 is one-to-many and R2 is
many-to-many. R1 and R2 do not have any attributes of their own. What is the minimum
number of tables required to represent this situation in the relational model?
(GATE 2005)
(a) 2
(b) 3
(c) 4
(d) 5

Answer (c)
The situation given can be expressed with following sample data.

E1
a
b
c

E2
x
y
z

R1
E1 E2
a x
a y
b z

R2
E1 E2
145
a x
a y
b y

38) Consider a relation scheme R = (A, B, C, D, E, H) on which the following functional

dependencies hold: {A–>B, BC–> D, E–>C, D–>A}. What are the candidate keys of R?

(GATE 2005)
(a) AE, BE
(b) AE, BE, DE
(c) AEH, BEH, BCH
(d) AEH, BEH, DEH

Answer (d)
A set of attributes S is candidate key of relation R if the closure of S is all attributes of R and
there is no subset of S whose closure is all attributes of R.
Closure of AEH, i.e. AEH+ = {ABCDEH}
Closure of BEH, i.e. BEH+ = {ABCDEH}
Closure of DEH, i.e. DEH+ = {ABCDEH}

39) Let R1 (A, B, C) and R2 (D, E) be two relation schema, where the primary
keys are shown underlined, and let C be a foreign key in R1 referring to R2.
Suppose there is no violation of the above referential integrity constraint in the
corresponding relation instances r1 and r2 . Which one of the following relational
algebra expressions would necessarily produce an empty relation ?
(GATE:2004)
1) ΠD (r2 ) - ΠC (r1 )
2) ΠC (r1 ) - ΠD (r2 )
3) ΠD (r1 C 1 D r2 )
4) ΠC (r1 C = Dr2)

Answer (2)
Explanation:
C is an attribute in R1 but D is a key in K 2 . So consider ΠC (r1)
− ΠD (r2) So the result of this query would be all those tuples
which are in ΠC (r1) but not in ΠD (r2).Since D is a key so it has
all the possible values of C . So difference would always be
146
empty.Hence( 2 ) is correct.

40) Consider the following relation schema pertaining to a students database:

Student (rollno, name, address)
Enroll (rollno, courseno, coursename)
where the primary keys are shown underlined. The number of tuples in the
Student and Enroll tables are 120 and 8 respectively. What are the maximum and
minimum number of tuples that can be present in (Student * Enroll), where '*'
denotes natural join ?
(GATE: 2004)

1) 8, 8
2) 120, 8
3) 960, 8
4) 960, 120

Answer (1)
Explanation:
The boundary cases are when either all the tuples of Enroll
table belong to one roll no. , so there can be at most 8 roll
no & courses no. combinations or the other case is when all
the tuples belong to different roll no. this also has 8 tuples.
So (8,8) = (max, min) Hence (A) is correct option

41) Which of the following scenarios may lead to an irrecoverable error in a database system
?
(GATE: 2003)

1) A transaction writes a data item after it is read by an uncommitted transaction

2) A transaction reads a data item after it is read by an uncommitted transaction
3) A transaction reads a data item after it is written by a committed transaction
4) A transaction reads a data item after it is written by an uncommitted transaction

Answer (4)

147
42) The following SQL
query select distinct al,
a2,........., an
from r1 , r2,........, rm
where P
For an arbitrary predicate P, this query is equivalent to which of the following
relational algebra expressions
GATE 2003

1.

2.

3.
4.

Answer (1)

43) Relation R with an associated set of functional dependencies, F, is

decomposed into BCNF. The redundancy (arising out of functional
dependencies) in the resulting set of relations is (GATE: 2002)

(a) Zero
(b) More than zero but less than that of an equivalent 3NF decomposition
(c) Proportional to the size of F+
(d) Indetermine

Ans: solution (b)

Explanation:
Redundancy in BCNF is low when compared to 3NF.

44) With regard to the expressive power of the formal relational query
languages, which of the following statements is true? (GATE: 2002)

(a) Relational algebra is more powerful than relational calculus

(b) Relational algebra has the same power as relational calculus.
148
(c) Relational algebra has the same power as safe relational calculus.

(d) None of the above

SOLUTION
Expressive power is the capacity of formal query languages to express various query
statements, so relational algebra is as powerful as relational calculus only if calculus
is safe relational calculus.Hence (C) is correct option.

45) Consider a relation geq which represents “greater than or equal to”,
that is, (x,y)∈ geq only if y≥x.
create table geq
( Ib integer not null ub integer not null primary key 1b foreign key (ub)
references geq on delete cascade)

Which of the following is possible if a tuple (x,y) is deleted?

(GATE:2001)
(a) A tuple (z,w) with z > y is deleted
(b) A tuple (z,w) with z > x is deleted
(c) A tuple (z,w) with w < x is deleted
(d) The deletion of (x,y) is prohibited
SOLUTION
Tuple (x, y) is
deleted. Here y
$x
lb is primary key
ub is foreign key
Since y refer to same key z . & in table A x a primary key is deleted so all enteries
from table B will also be deleted. And also all enteries referencing it in y will also be
deleted.Hence (C) is correct option.

46) Suppose the adjacency relation of vertices in a graph is represented in a table

Adj (X, Y).Which of the following queries cannot be expressed by a relational
algebra expression of constant length ? (A) List all vertices adjacent to a given vertex.
(B) List all vertices which have self loops
(C) List all vertices which belong to cycles of less than three vertices
(D) List all vertices reachable from a given vertex
149
 SOLUTION

The database contains the adjacency list of the graph. So

relation algebra with face problems when while calculating the
length of cycle self loops come, then the query would execute
in one tuple only. Hence (C) is correct option.

47) Given the relations

employee (name, salary, deptno)
department (deptno, deptname, address)
Which of the following queries cannot be expressed using the basic
relational algebra operations (σ,π,×, ,∪ ,∩,−)? (GATE:2000)

(a) Department address of every employee

(b) Employees whose name is the same as their department name
(c) The sum of all employees' salaries
(d) All employees of a given department
Answer: (c)

48) Given relations r(w,x) and s(y,z), the result of

select distinct w,x
from r, s
is guaranteed to be same as r, provided (GATE:2000)

(a) r has no duplicates and s is non-empty

(b) r and s have no duplicates
(c) s has no duplicates and r is non-empty
(d) r and s have the same number of tuples
Answer: (A)

49) In SQL, relations can c o n t a i n null values, and c o m p a r i s o n s with null

v a l u e s are treated as unknown. Suppose all c o m p a r i s o n s with a null
value are treated as false. Which of the following pairs is not equivalent?
(GATE:2000)

(a) x = 5 not (not (x = 5)

(b) x = 5 x > 4 and x < 6, where x is an integer
(c) x ≠ 5 not (x = 5)
(d) None of the above

150
Answer: (B)

50) Consider the join of a relation R with a relation S. If R has m tuples and
S has n tuples then the maximum and minimum sizes of the join respectively
are (GATE:1999)
(a) m + n and 0
(b) mn and 0
(c) m + n and |m – n|
(d) mn and m + n

151
52) Consider the schema R = (S T U V) and the dependencies S € T, T € U. U € V and
V € S. Let R = (R1 and R2) be a decomposition such that R1 ∩ R2 = ∅ . The
decomposition is (GATE:1999)
(a) not in 2NF (b) in 2NF but not 3NF (c) in 3NF
but not in 2NF (d) in both 2NF and 3NF

53) The minimum number of record movements required to merge five files A (with
10 records), B (with 20 records), C (with 15 records), D (with 5 records) and E
(with 25 records) is: (GATE:1999)
(a) 165 (b) 90 (c) 75 (d) 65

54) Which of the following is/are correct? (GATE:1999)

(a) An SQL query automatically eliminates duplicates

(b) An SQL query will not work if there are no indexes on the relations (c) SQL
permits attribute names to be repeated in the same relation

(d) None of the above

Answer: (d)

55) Consider the set of relations

EMP (Employee-no. Dept-no, Employee-name, Salary)

DEPT (Dept-no. Dept-name, Location)

Write an SQL query to:
(a) Find all employee names who work in departments located at ‘Calcutta’ and
whose salary is greater than Rs.50,000.
(b) Calculate, for each department number, the number of employees with a
salary greater than Rs.1,00,000. (GATE:1999)

56) Which normal form is considered adequate for normal relational database Design?
(GATE:1998)
(a) 2 NF (b) 5 NF (c) 4 NF (d) 3 NF

Ans: solution (d)

Explanation:

152
A relational database table is often described as "normalized" if it is in the Third Normal
Form because most of the 3NF tables are free of insertion, update, and deletion anomalies.

57) There are five records in a database.

Name Age Occupatio Categor

Rama 27 n CO y A

Abdul 22 N A
Jeniffe 28 EN B
r 32 G D
Maya 24 DO C
There is an index file
Devassociated with thisC and it contains the values 1,3,2,5 and 4.Which
one of the fields is the index built from? (GATE:1998)
SER
(a) Age (b) Name MUS (c) Occupation (d) Category
Answer: (C)
58) Suppose we have a database consisting of the following three relations.

FREQUENTS (student, parlor) giving the parlors each student visits.

SERVES (parlor, ice-cream) indicating what kind of ice-creams each parlor serves.
LIKES (student, ice-cream) indicating what ice-creams each student likes. (Assume that
each student likes at least one ice-cream and frequents at least one parlor)

Express the following in SQL:

Print the students that frequent at least one parlor that serves some ice- cream
that they like. (GATE:1998)

59) AB+ -tree index is to be built on the Name attribute of the relation STUDENT . Assume
that all student names are of length 8 bytes, disk blocks are of size 512 bytes, and index
pointers are of size 4 bytes. Given this scenario, what would be the best choice of the degree
(i.e. the number of pointers per node) of the B+ -tree ?
(A) 16 (B) 42 (C) 43 (D) 44

SOLUTION
Size of 1 record of index = 8 + 4 = 12 bytes. Let no. of pointers required = P
No. of index values per block = P – 1
So (P − 1) 8 + 4P= 512
12P= 520

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 P , 44
60) Let r and s be two relations over the relation schemes R and S respectively, and let A
be an attribute in R . Then the relational algebra expression σA = a ]r A s g is always equal to :
(A) σA = a ]r g (B) r
(C) σA = a ]r A s g (D) None of the above

SOLUTION

Given query performs natural join between r & s , & then project
attribute A where A = a . This same result is produced by the query σA = a (r) A s . This
query selects attribute A = a from r & then performs join operation results are
same. Hence (C) is correct option.

INFORMATIONS SYSTEMS SOFTWARE ENGINEERING

1.The coupling between different modules of a software is categorized as

follows:
I. Content coupling II. Common coupling III. Control coupling IV. Stamp coupling
V. Data coupling
Coupling between modules can be ranked in the order of strongest(least desirable) to
weakest (most desirable) as follows:
1) I-II-III-IV-V
2) V-IV-III-II-I
3) I-III-V-II-IV
4) IV-II-V-III-I
Solution:1

2.

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Solution: B gate-2010

3.

Solution: A gate-2010

4.

Solution: D gate-2010

5. In the system concepts, the term integration ?

a. implies structure and order

155
 b. refers to the manner in which each component functions with other components of the
system
c. means that parts of computer system depends on one another
d. refers to the holism of systems

Solution: D gate-2009

6.What is software?
a. Set of computer programs, procedures and possibly associated document concerned with the
operation of data processing.
b. A set of compiler instructions.
c. A mathematical formulae
d. All of the above
e. None of the above
Solution:A gate-2009
7. Which is the last step in classic life cycle paradigm?
a. System engineering
b. Analysis
c. Design
d. Coding
e. Maintenance.

Solution:E gate-2010

8. Which of the following is closer to machine Code

a. Assembly language
b. Machine language
c. High level language
d. All of the above
e. None of the above
Solution:A gate-2010
9. The following are properties of Modularity except

156
a. It implement a single independent function
b. It performs a single logical task.
c. It has a single entry and exit point.
d. It is entirely constructed of modules.
e. None of the above.

Solution:E gate-2011

10. The following are characteristics of software expects

a. It is developed or engineered.
b. Software does not wear out
c. Software are custom made
d. Software have don’t have spare parts instead it has backup
e. Software consists of physical devices.

Solution:E gate-2011

11. Software genetic development process contains three genetic phrases namely
a. Definition, development, maintenance.
b. Coding, design, Software engineering
c. Software engineering, Definition, Coding
d. Design, Coding, Development
e. Development, Definition, Testing
Solution:A gate-2011

12. Which of the following translators convert high-level language on statement-by-statement

basis?
a. Compiler
b. Machine level language converter
c. Interpreter.
d. Assembler
e. None of the above

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Solution:C gate-2012
13. Which of the following is not an example of Prototype in engineering paradigm?
a. Paper prototype.
b. Existing prototype.
c. Working prototype.
d. Software prototype.
e. Engineering prototype.
Solution:A gate-2012

14. Which of the following Construct in formal model in software engineering execute each
statement in succession.
a. Selection Construct.
b. Sequence Construct. (Correct)
c. Iteration Construct.
d. Business Construct.
e. Statement Construct.
Solution:B gate-2012

15.What is software engineering?

a. Set of computer programs, procedures and possibly associated document concerned with the
operation of data processing.
b. Software engineering is Design, Coding, Development
c. Software engineering implement a single independent function
d. Software engineering is the establishment and use of sound engineering practice in order to
produce economical and reliable software that will perform efficiently on real machine (Correct)
e.Software engineering is a step that encompasses the method, tools, procedure used in software

Solution:D gate-2012

16. The most important feature of spiral model is

(A) requirement analysis. (B) risk management.
(C) quality management. (D) configuration management.

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Ans: B

17. The worst type of coupling is

(A) Data coupling. (B) control coupling.
(C) stamp coupling. (D) content coupling.

Ans: D

18. IEEE 830-1993 is a IEEE recommended standard for

(A) Software requirement specification.
(B) Software design.
(C)Testing.
(D) Both (A) and (B)

Ans: A

19. One of the fault base testing techniques is

(A) unit testing. (B) beta testing.
(C) Stress testing. (D) mutation testing.

Ans: D

20. Changes made to an information system to add the desired but not necessarily the
required features is called
(A) Preventative maintenance.
(B) Adaptive maintenance.
(C) Corrective maintenance.
(D) Perfective maintenance.

Ans: D

21. All the modules of the system are integrated and tested as complete system in the
case of
(A) Bottom up testing (B) Top-down testing
(C) Sandwich testing (D) Big-Bang testing

Ans: D
22. SRS is also known as specification of

Ans: D
(A) White box testing (B) Stress testing
(C) Integrated testing (D) Black box testing

23. The model in which the requirements are implemented by category is

(A) Evolutionary Development Model
(B) Waterfall Model
159
(C) Prototyping
(D) Iterative Enhancement Model

Ans: A

24. SRD stands for

(A) Software requirements definition
(B) Structured requirements definition
(C) Software requirements diagram
(D) Structured requirements diagram

Ans: B

25. Usingpublic key cryptography, X adds a digital signature σ to message M,

encrypts <M, σ>, and sends it to Y, where it is decrypted. Which one of the
following sequences of keys is used for the operations?
(A) Encryption: X’s private key followed by Y’s private key; Decryption: X’s public
key followed by Y’s public key
(B) Encryption: X’s private key followed by Y’s public key; Decryption: X’s public
key followed by Y’s private key
(C) Encryption: X’s public key followed by Y’s private key; Decryption: Y’s public
key followed by X’s private key
(D) Encryption: X’s private key followed by Y’s public key; Decryption: Y’s private
key followed by X’s public key

Ans:D 2013

COMPUTER NETWORKS
1. The transport layer protocols used for real time multimedia, file transfer, DNS and email,
respectively are GATE 2013

(A) TCP, UDP, UDP and TCP

(B) UDP, TCP, TCP and UDP
(C) UDP, TCP, UDP and TCP
(D) TCP, UDP, TCP and UDP
ANS: C
SOL: Multimedia can be unreliable but has to be fast so UDP, File transfer has to be secure &
reliable so uses TCP, DNS can be both TCP and UDP, E mail uses TCP for reliability.

2. Using public key cryptography, X adds a digital signature σ to message M, encrypts <M, σ>, and
sends it to Y, where it is decrypted. Which one of the following sequences of keys is used for the
operations? GATE 2013
160
 (A) Encryption: X’s private key followed by Y’s private key; Decryption: X’s public key followed
by Y’s public key
(B) Encryption: X’s private key followed by Y’s public key; Decryption: X’s public key followed by
Y’s private key
(C) Encryption: X’s public key followed by Y’s private key; Decryption: Y’s public key followed by
X’s private key
(D) Encryption: X’s private key followed by Y’s public key; Decryption: Y’s private key followed
by X’s public key
ANS: D

3. Assume that source S and destination D are connected through two intermediate routers labeled R.
Determine how many times each packet has to visit the network layer and the data link layer during
a transmission from S to D. GATE 2013

(A) Network layer – 4 times and Data link layer – 4 times

(B) Network layer – 4 times and Data link layer – 3 times
(C) Network layer – 4 times and Data link layer – 6 times
(D) Network layer – 2 times and Data link layer – 6 times
ANS: C
SOL: Therefore, Network layer – 4 times
Data link layer – 6 times

4. Determine the maximum length of the cable (in km) for transmitting data at a rate of 500 Mbps in an
Ethernet LAN with frames of size 10,000 bits. Assume the signal speed in the cable to be 2,00,000
km/s. GATE 2013

(A) 1 (B) 2 (C) 2.5 (D) 5

ANS: B
SOL: Propagation time = Transmission time + Collision signal time

𝐹𝑎𝑟𝑚𝑒 𝑠𝑖𝑧𝑒 𝐿𝑒𝑛𝑔𝑡ℎ 𝐿𝑒𝑛𝑔𝑡ℎ

= +
𝑃𝑟𝑜𝑝𝑎𝑔𝑎𝑡𝑖𝑜𝑛 𝑡𝑖𝑚𝑒 𝑆𝑖𝑔𝑛𝑎𝑙 𝑠𝑝𝑒𝑒𝑑 𝑆𝑖𝑔𝑛𝑎𝑙 𝑠𝑝𝑒𝑒𝑑

10000 𝑏𝑖𝑡 2 ∗ 𝑙𝑒𝑛𝑔𝑡ℎ

=
500 ∗ 106 𝑏𝑖𝑡𝑠/ 𝑠𝑒𝑐 2 ∗ 105 𝑘𝑚/𝑠𝑒𝑐
161
 Length = 2 km

5. In an IPv4 datagram, the M bit is 0, the value of HLEN is 10, the value of total length is 400 and the
fragment offset value is 300. The position of the datagram, the sequence numbers of the first and the
last bytes of the payload, respectively are GATE 2013

(A) Last fragment, 2400 and 2789

(B) First fragment, 2400 and 2759
(C) Last fragment, 2400 and 2759
(D) Middle fragment, 300 and 689
ANS: C
SOL: Since M bit is 0, so there is no fragment after this fragment. Hence this fragment is the last
fragment.
Now, HLEN defines the length of header in datagram. Since Hlen is 10 so, size of header is 10 *
4 = 40 B
Length of data = Total length – Header length
= 400 – 40
= 360 B
Now, fragment offset of data in original datagram is measured in units of 8 B. so to find first Byte of
this fragment, First byte/8 = fragment offset
First byte = 300 * 8 = 2400 B and since length of data is 360 B.
So, last byte on this datagram will be 2759

6. In the IPv4 addressing format, the number of networks allowed under Class C addresses is
GATE 2012
(A) 214 (B) 27 (C) 221 (D) 224
ANS: C
SOL: For class C address, size of network field is 24 bits. But first 3 bits are fixed as 110; hence
total number of networks possible is 221.

7. Which of the following transport layer protocols is used to support electronic mail?
GATE 2012
(A) SMTP (B) IP (C) TCP (D) UDP
ANS:C
SOL: E-mail uses SMTP in application layer to transfer mail. And SMTP uses TCP to transfer data
in transport layer.
8. The protocol data unit (PDU) for the application layer in the Internet stack is
GATE 2012
(A) Segment (B) Datagram (C) Message (D) Frame
ANS: C
SOL: Protocol Data Unit (PDU)
Application layer – Message
Transport layer – Segment
Network layer – Datagram
Data Link layer – Frame
Ans = Message
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9. Consider an instance of TCP’s Additive Increase Multiplicative Decrease (AIMD) algorithm where
the window size at the start of the slow start phase is 2 MSS and the threshold at the start of the first
transmission is 8 MSS. Assume that a timeout occurs during the fifth transmission. Find the
congestion window size at the end of the tenth transmission.
GATE 2012
(A) 8 MSS (B) 14 MSS (C) 7 MSS (D) 12 MSS
ANS: C
SOL: Given threshold = 8
Time = 1, during first transmission, window size = 2 (slow start phase)
Time = 2, congestion window size = 4 (double the no. of acknowledgments)
Time = 3, congestion window size is = 8
Time = 4, congestion window size = 9, after threshold (increase by one addictive increase)
Time = 5, transmits 10 MSS, but time out occurs congestion windw size = 10
Hence threshold = (congestion window size)/2=10/2 = 5
Time = 6, transmits 2
Time = 7, transmits 4
Time = 8, transmits 5(threshold is 5)
Time = 9, transmits 6
Time = 10, transmits 7
During 10th transmission, it transmits 7 segments hence at the end of the 10th transmission
the size of congestion window is 7 MSS.

10. Consider a source computer (S) transmitting a file of size 106 bits to a destination
computer (D) over a network of two routers (R1 and R2) and three links (L1, L2, and L3).
L1 connects S to R1; L2 connects R1 to R2; and L3 connects R2 to D. Let each link be
of length 100km. Assume signals travel over each line at a speed of 108 meters per
second. Assume that the link bandwidth on each link is 1Mbps. Let the file be broken down
i n t o 1000 p a c k e t s each of size 1000 bits. Find the total sum o f transmission and
p r o p a g a t i o n delays i n transmitting the file from S to D?
GATE 2012
(A) 1005ms (B) 1010ms (C) 3000ms (D) 3003ms
ANS: A
SOL: L1 L2 L3

R2 D
S R1

Transmission delay for 1st packet from each of S, R1 and R2 will take 1 ms
Propagation delay on each link l1,l2 and l3 for one packet is 1ms
Therefore the sum of transmission delay and propagation delay on each link for one packet is
2ms.
The first packet reaches the destination at 6th ms
The second packet reaches the destination at 7th ms
So, inductively we can say that 1000th packet reaches the destination at 1005th ms.

163
11. Consider the directed graph shown in the figure below. There are multiple shortest paths between
vertices S and T. Which one will be reported by Dijkstra’s shortest path algorithm? Assume that, in
any iteration, the shortest path to a vertex v is updated only when a strictly shortest path to v is
discovered.

GATE 2012

(A) SDT (B) SBDT (C) SACDT (D) SACET

ANS: D
SOL: Let d[v] represent the shortest path distance computed from ‘S’ Initially d[S] = 0, d[A] = ∞,
d[B] = ∞, - - - - -, d[T] = ∞
and let P[v] represent the predecessor of v in the shortest path from ‘S’ to ‘v’ and let P[v] = 1 denote
that currently predecessor of ‘v’ has not been computed
→ Let Q be the set of vertices for which shortest path distance has not been computed

→ Let W be the set of vertices for which shortest path distance has not been computed

→ So initially, Q = {S, A, B, C, D, E, F, G, T}, W = ϕ

We will use the following procedure

Repeat until Q is empty{
1. u = choose a vertex from Q with minimum d[u] value
2. Q = Q – u
3. update all the adjacent vertices of u
4. W = W U{u}
} d[S] = 0, d[A] = ∞, d[B] = ∞, . . . . , d[T] = ∞
Iteration 1: Step 1: u = S
Step 2: Q = {A, B, C, D, E, F, G, T}
Step 3: final values after adjustment
d[S] = 0, d[A] = 4, d[B] = 3, d[C] = ∞, d[D] = 7, d[E] = ∞ - - -, d[T] = ∞
P[A] = S, P[B] = S, P[C] = 1, P[D] = S, P[E] = 1 - - - , P[T] = 1
Step 4: W = {S}
Iteration 2: Step 1: u = S
Step 2: Q = {A, C, D, E, F, G, T}
Step 3: final values after adjustment
d[S] = 0, d[A] = 4, d[B] = 3, d[C] = ∞, d[D] = 7, d[E] = ∞ - - -, d[T] = ∞
P[A] = S, P[B] = S, P[C] = 1, P[D] = S, P[E] = 1 - - - , P[T] = 1
164
 Step 4: W = {S, B}
Iteration 3: Step 1: u = A
Step 2: Q = {C, D, E, F, G, T}
Step 3: final values after adjustment
d[S] = 0, d[A] = 4, d[B] = 3, d[C] = 5, d[D] = 7, d[E] = ∞ - - -, d[T] = ∞
P[A] = S, P[B] = S, P[C] = A, P[D] = S, P[E] = 1 - - - , P[T] = 1
Step 4: W = {S, B, A}
Iteration 4: Step 1: u = C
Step 2: Q = {D, E, F, G, T}
Step 3: final values after adjustment
d[S] = 0, d[A] = 4, d[B] = 3, d[C] = 5, d[D] = 7, d[E] = 6, - - -, d[T] = ∞
P[A] = S, P[B] = S, P[C] = A, P[D] = S, P[E] = C, - - - , P[T] = 1
Step 4: W = {S, B, A, C}
Iteration 5: Step 1: u = E
Step 2: Q = {D, F, G, T}
Step 3: final values after adjustment
d[S] = 0, d[A] = 4, d[B] = 3, d[C] = 5, d[D] = 7, d[E] = 6, d[F] = ∞, d[G] = 8,
d[T] = 10 P[A] = S, P[B] = S, P[C] = A, P[D] = S, P[E] = C, P[F] = 1,
P[G] = E, P[T] = E
Step 4: W = {S, B, A, C, E}
After iteration 5, we can observe that P[T] = E, P[E] = C, P[C] = A, P[A] = S, So the shortest
path from S to T is SACET

12. An Internet Service Provider (ISP) has the following chunk of CIDR-based IP addresses available
with it: 245.248.128.0/20. The ISP wants to give half of this chunk of addresses to Organization. A,
and a quarter to Organization B, while retaining the remaining with itself. Which of the following is
a valid allocation of addresses to A and B? GATE 2012

(A) 245.248.136.0/21 and 245.248.128.0/22

(B) 245.248.128.0/21 and 245.248.128.0/22

(C) 245.248.132.0/22 and 245.248.132.0/21

(D) 245.248.136.0/24 and 245.248.132.0/21

ANS: A
SOL:

th
Since half of 4096 host addresses must be given to organization A, we can set 12 bit to 1 and
include that bit into network part of organization A, so the valid allocation of addresses to A is
245.248.136.0/21

165
 th th
Now for organization B, 12 bit is set to ‘0’ but since we need only half of 2048 addresses, 13
bit can be set to ‘0’ and include that bit into network part of organization B so the valid
allocation of addresses to B is 245.248.128.0/22

13. Consider different activities related to email.

m1: Send an email from a mail client to a mail server
m2: Download an email from mailbox server to a mail client
m3: Checking email in a web browser
Which is the application level protocol used in each activity? GATE 2011

(A) m1: HTTP m2: SMTP m3: POP (B) m1: SMTP m2: FTP m3: HTTP

(C) m1: SMTP m2: POP m3: HTTP (D) m1: POP m2: SMTP m3: IMAP
ANS: C
SOL: Mail client uses SMTP (Simple Mail Transfer Protocol) to send mail. (The client need not be
web based. So, HTTP may not be involved here). POP (Post Office Protocol) is used to retrieve
mail from mail server. HTTP (Hypertext transfer protocol) is used to transfer a HTML page
containing the mail message that can be viewed on a web browser.

14. A layer-4 firewall (a device that can look at all protocol headers up to the transport layer) CANNOT
GATE 2011

(A) Block entire HTTP traffic during 9:00PM and 5:00AM

(B) Block all ICMP traffic

(C) Stop incoming traffic from a specific IP address but allow outgoing traffic to the same IP address

(D) Block TCP traffic from a specific user on a multi-user system during 9:00PM and 5:00Am
ANS: A

Statement for Linked Questions 15 and 16

Consider a network with five nodes, N1 to N5, as shown below.

166
 The network uses a Distance Vector Routing protocol. Once the routes have stabilized, the distance
vectors at different nodes are as following.
N1: (0, 1, 7, 8, 4)
N2: (1, 0, 6, 7, 3)
N3: (7, 6, 0, 2, 6)
N4: (8, 7, 2, 0, 4)
N5: (4, 3, 6, 4, 0)
Each distance vector is the distance of the best known path at the instance to nodes, N1 to N5, where
the distance to itself is 0. Also, all links are symmetric and the cost is identical in both directions. In
each round, all nodes exchange their distance vectors with their respective neighbors. Then all nodes
update their distance vectors. In between two rounds, any change in cost of a link will cause the two
incident nodes to change only that entry in their distance vectors.

15. The cost of link N2-N3 reduces to 2(in both directions). After the next round of updates, what will
be the new distance vector at node, N3? GATE 2011

(A) (3, 2, 0, 2, 5) (B) (3, 2, 0, 2, 6) (C) (7, 2, 0, 2, 5) (D) (7, 2, 0, 2, 6)

ANS: A

16. After the update in the previous question, the link N1-N2 goes down. N2 will reflect this change
immediately in its distance vector as cost, ∞. After the NEXT ROUND of update, what will be the
cost to N1 in the distance vector of N3? GATE 2011

(A) 3 (B) 9 (C) 10 (D) ∞

ANS: C

17. One of the header fields in an IP datagram is the Time to Live (TTL) field. Which of the following
statements best explains the need for this field? GATE 2010

(A) It can be used to prioritize packets

(B) It can be used to reduce delays
(C) It can be used to optimize throughput
(D) It can be used to prevent packet looping
ANS: D
SOL: Whenever Time to live field reaches ‘0’ we discard the packet, so that we can prevent it from
looping.

18. Which one of the following is not a client server application? GATE 2010

(A) Internet chat (B) Web browsing (C) E-mail (D) Ping
ANS: D

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Statement for Linked Answer Questions: 19 & 20
Consider a network with 6 routers R1 to R6 connected with links having weights as shown in the
following diagram

19. All the routers use the distance vector based routing algorithm to update their routing tables. Each
router starts with its routing table initialized to contain an entry for each neighbor with the weight of
the respective connecting link. After all the routing tables stabilize, how many links in the network
will never be used for carrying any data? GATE 2010

(A) 4 (B) 3 (C) 2 (D) 1

ANS: D
SOL: In Distance vector, the Router will update its routing tables by exchanging the information
from all its neighbors. After all the routing tables stabilize the routing Table for ‘R1’ will not
have any entry to Router R6., so that link will not be used. So one link.

20. Suppose the weights of all unused links in the previous question are changed to 2 and the distance
vector algorithm is used again until all routing tables stabilize. How many links will now remain
unused? GATE 2010

(A) 0 (B) 1 (C) 2 (D) 3

ANS: A

21. Which of the following statement(s) is / are correct regarding Bellman-Ford shortest path algorithm?
P. Always finds a negative weighted cycle, if one exists.
Q. Finds whether any negative weighted cycle is reachable from the source.
GATE 2009

(A) P only (B) Q only (C) both P and Q (D) Neither P nor Q
ANS: B
SOL: The algorithm identifies a negative weight cycle iff it is reachable from Source.

168
22. Consider the following graph:

Which one of the following is NOT the sequence of edges added to the minimum spanning tree
using Kruskal’s algorithm?
GATE 2009

(A) (b,e) (e,f) (a,c) (b,c) (f,g) (c,d) (B) (b,e) (e,f) (a,c) (f,g) (b,c) (c,d)
(C) (b,e) (a,c) (e,f) (b,c) (f,g) (c,d) (D) (b,e) (e,f) (b,c) (a,c) (f,g) (c,d)
ANS: D
SOL: Weight of edge (a,c) is less than (b,c) . So it cannot come after (b,c)

23. In the RSA public key cryptosystem, the private and public keys are (e, n) and (d, n) respectively,
where n=p*q and p and q are large primes. Besides, n is public and p and q are private. Let M be an
integer such that 0<M<n and Φ (n) = (p − 1) (q − 1). Now consider the following equations.
I. M' = Me mod n
M = (M')d mod n

II. ed ≡ 1 mod n

III. ed ≡ 1 mod Φ(n)

IV. M' = Me mod Φ(n)

M = (M')d mod Φ(n)
Which of the above equations correctly represent RSA cryptosystem?
GATE 2009
(A) I and II (B) I and III (C) II and IV (D) III and IV
ANS: B

Statement for Linked Answer Questions: 24 & 25

Frames of 1000 bits are sent over a 106 bps duplex link between two hosts. The propagation time
is 25ms. Frames are to be transmitted into this link to maximally pack them in transit (within the
link).

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24. What is the minimum number of bits (i) that will be required to represent the sequence numbers
distinctly? Assume that no time gap needs to be given between transmission of two frames.
GATE 2009
(A) i=2 (B) i=3 (C) i=4 (D) i=5
ANS: D

SOL: The transmission time for a frame is 1000/1Mbps = 1 ms .As the propagation time is 25 ms,
the sender can transmit 25 packets before the first packet reaches the destination. Therefore the
number of bits required to represent 25 packets is 5.

25. Suppose that the sliding window protocol is used with the sender window size of 2i, where i is the
number of bits identified in the earlier part and acknowledgements are always piggy backed. After
sending 2i frames, what is the minimum time the sender will have to wait before starting
transmission of the next frame? (Identify the closest choice ignoring the frame processing time.)
GATE 2009
(A) 16ms (B) 18ms (C) 20ms (D) 22ms
ANS: B
SOL: Sliding window size is 32 as i=5. The sender can expect an Ack after one RTT. Here Round
trip time is 50ms. Therefore the sender has to wait at least 50-32= 18ms before transmission of the
next frame.

26. What is the maximum size of data that the application layer can pass on to the TCP layer below?
GATE 2008

(A) Any size (B) 216 bytes-size of TCP header

(C) 216 bytes (D) 1500 bytes
ANS: A
SOL: Application layer can pass any length data. TCP layer will divide that data into frames.

27. Which of the following system calls results in the sending of SYN packets?
GATE 2008
(A) socket (B) bind (C) listen (D) connect
ANS: D
SOL: In the process of establishing a connection between two endpoints, the user process on active
end point invokes the connect() system call. The active end point then sends a SYN packet. The
passive end point invokes an accept() system call and sends ACK to the other system then the
connection is established.

28. Dijkstra’s single source shortest path algorithm when run from vertex ‘a’ in the following graph,
computes the correct shortest path distance to

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 (A) only vertex a (B) only vertices a, e, f, g, h
(C) only vertices a, b, c, d (D) all the vertices
ANS: D

SOL: Even though the graph has negative weights, it correctly computes the shortest path to all the
vertices. There will not be any problem with the Dijkstra's algorithm operating on negative edge
weights as long as the shortest path distance computed for the currently removed vertex is the actual
shortest path distance.

29. In the slow start phase of the TCP congestion control algorithm, the size of the congestion window
GATE 2008

(A) Does not increase (B) increases linearly

(C) Increases quadratically (D) increases exponentially
ANS: B

30. If a class B network on the Internet has a subnet mask of 255.255.248.0, what is the maximum
number of hosts per subnet? GATE 2008

(A) 1022 (B) 1023 (C) 2046 (D) 2047

ANS: C

SOL: Number of bits for subnet mask = 21

Number of bits for host = 11

Number of hosts = 211-2 = 2046

31. A computer on a 10Mbps network is regulated by a token bucket. The token bucket is filled at a rate
of 2Mbps. It is initially filled to capacity with 16Megabits. What is the maximum duration for which
the computer can transmit at the full 10Mbps? GATE 2008

(A) 1.6 seconds (B) 2 seconds (C) 5 seconds (D) 8 seconds

ANS: B
SOL: If the capacity of the token bucket is C bytes, Token arrival rate is R bytes/sec, and the
Maximum possible transmission rate is M bytes/sec then the time(S) in seconds it is possible to
transmit is S = C/(M-R) seconds , so 16/(10-2) = 2 seconds.

32. In Ethernet when Manchester encoding is used, the bit rate is: GATE 2007

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 (A) Half the baud rate. (B) Twice the baud rate.
(C) Same as the baud rate. (D) None of the above
ANS: A
SOL: In Ethernet when Manchester encoding is used, the bit rate is half of the baud rate.

33. Which one of the following uses UDP as the transport protocol? GATE 2007

(A) HTTP (B) Telnet (C) DNS (D) SMTP

ANS: C
SOL: DNS queries are normally short and they need fast responses. Therefore UDP is a better
option as a transport protocol for DNS.

34. There are n stations in a slotted LAN. Each station attempts to transmit with a probability p in each
time slot. What is the probability that ONLY one station transmits in a given time slot?
GATE 2007

(A) np(1-p)n-1 (B) (1-p)n-1 (C) p(1-p)n-1 (D) 1-(1-p)n-1

ANS: A
SOL: The probability that only one station transmits in a given slot is, probability that station 1
transmits, stations 2 to n are not tranmitting + station 2 is transmitting and
station 1, stations 3 to n are not transmitting + ...............

which is, p(1-p)(1-P)....... + (1-p)p(1-p)(1-p) ........ + (1-p)(1-p)p(1-p) ......... + ....... ntimes

= p(1-p)(n-1) + p(1-p)(n-1) + p(1-p)(n-1) + p(1-p)(n-1) + p(1-p)(n-1) + ...... n times
= np(1-p)(n-1)

35. In a token ring network the transmission speed is 7 10 bps and the propagation speed is 200
metres/Rs. The 1-bit delay in this network is equivalent to: GATE 2007

(A) 500 metres of cable. (B) 200 metres of cable.

(C) 20 metres of cable. (D) 50 metres of cable.
ANS: C
SOL: The time taken to transmit 1 bit is 0.1micro second. Propagation speed is
200meters/microsecond.Therefore 1 bit delay implies 20 metres.

36. The address of a class B host is to be split into subnets with a 6-bit subnet number. What is the
maximum number of subnets and the maximum number of hosts in each subnet?
(A) 62 subnets and 262142 hosts. (B) 64 subnets and 262142 hosts.
(C) 62 subnets and 1022 hosts. (D) 64 subnets and 1024 hosts.
ANS: C
SOL: Maximum number of subnets is 26-2 =62. Maximum number of hosts is 210-2 = 1022.
Actually at present , subnets with addresses all 0's and all 1's can also be used.

37. The message 11001001 is to be transmitted using the CRC polynomial 3 x + 1 to protect it from
errors. The message that should be transmitted is: GATE 2007

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 (A) 11001001000 (B) 11001001011
(C) 11001010 (D) 110010010011
ANS: B
SOL: The divisor is 1001. After dividing the given data 11001001 by 1001, the remainder is 011
which is the CRC. Therefore the transmitted data is, data+CRC
which is 11001001011.

38. The distance between two stations M and N is L kilometers. All frames are K bits long. The
propagation delay per kilometer is t seconds. Let R bits/second be the channel capacity. Assuming
that processing delay is negligible, the minimum number of bits for the sequence number field in a
frame for maximum utilization, when the sliding window protocol is used, is:

2𝐿𝑡𝑅+2𝐾 2𝐿𝑡𝑅
(A) ⌈log 2 ⌉ (B) ⌈log 2 ⌉
𝐾 𝐾
2𝐿𝑡𝑅+𝐾 2𝐿𝑡𝑅+𝐾
(C) ⌈log 2 ⌉ (D) ⌈log 2 ⌉
𝐾 2𝐾
ANS: A

SOL: The distance between the stations is L kilometers.

Propagation delay per kilometer is t seconds. Therefore the total propagation delay is Lt seconds.

The round trip time is 2*propagation delay = 2Lt seconds.

Maximum utilization can be achieved by transmitting data for the whole round trip time. The
size of data that can be transmitted for Round trip time is Time * bandwidth = 2LtR.

other than round trip time a packet is transmitted, and an ack. is also transmitted when the packet
is received. The size in bits is 2k.

Therefore total size in bits is 2LtR + 2k. Number of packets is (2LtR+2k)/k. Number of bits
required to represent these packets is log(Number of packets).

39. Match the following:

(P) SMTP (1) Application layer
(Q) BGP (2) Transport layer
(R) TCP (3) Data link layer
(S) PPP (4) Network layer
(5) Physical layer GATE 2007

(A) P - 2 Q - 1 R - 3 S – 5 (B) P - 1 Q - 4 R - 2 S - 3
(C) P - 1 Q - 4 R - 2 S – 5 (D) P - 2 Q - 4 R - 1 S – 3
ANS: B
SOL: SMTP is an application layer protocol. TCP is the transport layer protocol. BGP is
network layer protocol and PPP is the data link layer protocol.

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40. For which one of the following reasons does Internet Protocol (IP) use the time-to- live (TTL) field
in the IP datagram header? GATE 2006

(A) Ensure packets reach destination within that time

(B) Discard packets that reach later than that time
(C) Prevent packets from looping indefinitely
(D) Limit the time for which a packet gets queued in intermediate routers.
ANS: C
SOL: Time to live indicates the time or maximum number of hops the packet is allowed to make
before it is discarded. Normally it is set to twice the maximum length path from source to
destination.

41. Station A uses 32 byte packets to transmit messages to Station B using a sliding window protocol.
The round trip delay between A and B is 80 milliseconds and the bottleneck bandwidth on the path
between A and B is 128 kbps. What is the optimal window size that A should use?
GATE 2006

(A) 20 (B) 40 (C) 160 (D) 320

ANS: B
SOL: The packet size is 32 bytes = 32*8 bits.

Round trip time is 80ms. Bandwidth is 128kbps. Therefore in 1 RTT, the source a transmit
128kbps * 80ms bits of data.

The data possible to be transmitted divided by the packet size gives the window size, which
is (128k * 80 ms)/(32*8) = 40.

42. Two computers C1 and C2 are configured as follows. C1 has IP address 203.197.2.53 and net mask
255.255.128.0. C2 has IP address 203.197.75.201 and net mask 255.255.192.0. which one of the
following statements is true? GATE 2006

(A) C1 and C2 both assume they are on the same network

(B) C2 assumes C1 is on same network, but C1 assumes C2 is on a different network
(C) C1 assumes C2 is on same network, but C2 assumes C1 is on a different network
(D) C1 and C2 both assume they are on different networks.
ANS: C
SOL: IP address of C1 is 203.197.2.53 and Subnet mask is 255.255.128.0 ending gives the network
id which is 203.197.0.0.

When C1 sees the ipaddress 203.197.75.201, to find the network id it will and with its subnet
mask, which gives 203.197.0.0.

So C1 assumes that C2 is on the same network with C1.

Similarly, IP address of C2 is 203.197.75.201, subnet mask is 255.255.192.0 ending gives the

network id which is 203.197.64.0.

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 When this computer looks at IP address of C1, to find the network id, it will and with its network
mask giving 203.197.0.0.

Therefore C1 assumes that C2 is on the same network with C2, but C2 assumes C1 is on a
different network.

43. Station A needs to send a message consisting of 9 packets to Station B using a sliding window
(window size 3) and go-back-n error control strategy. All packets are ready and immediately
available for transmission. If every 5th packet that A transmits gets lost (but no acks from B ever get
lost), then what is the number of packets that A will transmit for sending the message to B?
GATE 2006

(A) 12 (B) 14 (C) 16 (D) 18

ANS: C

SOL:

Assume that correctly transmitted packet is acknowledged at the same time. When a packet is
lost, the receiver waits for certain duration but the sender can send up to its window size. The
total number of packets sent is 16.

44. Packets of the same session may be routed through different paths in:
(a) TCP, but not UDP (b) TCP and UDP
(c) UDP, but not TCP (d) Neither TCP nor UDP
ANS: B
SOL: Packet is the Network layer Protocol Data Unit (PDU). TCP and UDP are Transport layer
protocols. Packets of same session may be routed through different routes. Most networks don’t use

175
 static routing, but use some form of adaptive routing where the paths used to route two packets for
same session may be different due to congestion on some link, or some other reason.

45. The address resolution protocol (ARP) is used for: GATE 2005

(a) Finding the IP address from the DNS

(b) Finding the IP address of the default gateway
(c) Finding the IP address that corresponds to a MAC address
(d) Finding the MAC address that corresponds to an IP address
ANS: D

46. The maximum window size for data transmission using the selective reject protocol with n-bit frame
sequence numbers is: GATE 2005

(a) 2n (b) 2n - 1 (c) 2n - 1 (d) 2n-2

ANS: B

47. In a network of LANs connected by bridges, packets are sent from one LAN to another through
intermediate bridges. Since more than one path may exist between two LANs, packets may have to
be routed through multiple bridges. Why is the spanning tree algorithm used for bridge-routing?
GATE 2005

(a) For shortest path routing between LANs

(b) For avoiding loops in the routing paths
(c) For fault tolerance
(d) For minimizing collisions
ANS: B

48. An organization has a class B network and wishes to form subnets for 64 departments. The subnet
mask would be: GATE 2005

(a) 255.255.0.0 (b) 255.255.64.0

(c) 255.255.128.0 (d) 255.255.252.0
ANS: D
SOL: The size of network ID is 16 bit in class B networks. So bits after 16th bit must be used to
create 64 departments. Total 6 bits are needed to identify 64 different departments. Therefore, subnet
mask will be 255.255.252.0.

49. Suppose the round trip propagation delay for a 10 Mbps Ethernet having 48-bit jamming signal is
46.4 ms. The minimum frame size is: GATE 2005

(a) 94 (b) 416 (c) 464 (d) 512

ANS: C
SOL: Transmission Speed = 10Mbps.
Round trip propagation delay = 46.4 ms
The minimum frame size = (Round Trip Propagation Delay) * (Transmission Speed)
176
 = 10*(10^6)*46.4*(10^-3) = 464 * 10^3 = 464 Kbit.

The concept behind the above formula is collision detection. Consider a situation where a
node A wants to send a frame to another node B. When Node A begins transmitting, the signal
must propagate the network length. In the worst-case collision scenario, Node B begins to
transmit just before the signal for Node A’s frame reaches it. The collision signal of Node A and
Node B’s frame must travel back to Node A for Node A to detect that a collision has occurred.

The time it takes for a signal to propagate from one end of the network to the other is
known as the propagation delay. In this worst-case collision scenario, the time that it takes for
Node A to detect that its frame has been collided with is twice the propagation delay. Node A’s
frame must travel all the way to Node B, and then the collision signal must travel all the way
from Node B back to Node A. This time is known as the slot time. An Ethernet node must be
transmitting a frame for the slot time for a collision with that frame to be detected. This is the
reason for the minimum Ethernet frame size.

50. Choose the best matching between Group 1 and Group 2

Group –1 Group – 2

P. Data link layer 1. Ensures reliable transport of data over a physical

Point-to-point link

Q. Network layer 2. Encodes/decodes data for physical transmission

R. Transport layer 3.Allows end-to-end communication between two

processes
4. Routes data from one network node to the next
(a) P – 1, Q – 4, R - 3 (b) P – 2, Q – 4, R - 1
(c) P – 2, Q – 3, R - 1 (d) P – 1, Q – 3, R – 2
ANS: A
SOL: Transport layer is responsible for end to end communication, creation of
sockets.Network layer routes the data from one node to other, till it reach to destination.
Datalink layer ensures reliable data transfer by error correction, duplication check ordered
delivery etc.

51. Which of the following is NOT true with respect to a transparent bridge and a router?
(a) Both bridge and router selectively forward data packets
(b) A bridge uses IP addresses while a router uses MAC addresses
(c) A bridge builds up its routing table by inspecting incoming packets
(d) A router can connect between a LAN and a WAN
ANS: B

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 SOL: Bridge is the device which work at data link layer whereas router works at network
layer. Both selectively forward packets, build routing table & connect between LAN & WAN
but since bridge works at data link it uses MAC addresses to route whereas router uses IP
addresses.

52. The routing table of a router is shown below:

On which interface will the router forward packets addressed to destinations 128.75.43.16 and
192.12.17.10 respectively?

(a) Eth1 and Eth2 (b) Eth0 and Eth2

(c) Eth0 and Eth3 (d) Eth1 and Eth3

ANS: C

SOL: Given IP Address

128.75.43.16. (1)
Eth 0 128.75.43.0. (2)
Mask 255.255.255.0.
Equation (1) & (2) both are of same network.
192.12.17.10. (1)
Eth3 192.12.17.5 (2)
Mask 255.255.255.255
Equation (1) & (2) both are of same network.

53. Which of the following assertions is FALSE about the Internet Protocol (IP)? GATE 2003

(A) It is possible for a computer to have multiple IP addresses

(B) IP packets from the same source to the same destination can take different routes in the network
(C) IP ensures that a packet is discarded if it is unable to reach its destination within a given number
of hops
(D) The packet source cannot set the route of an outgoing packets; the route is determined only by
the routing tables in the routers on the way
ANS: A
SOL: Internet protocol ensures that a packet is forwarded if it is nable to reach its
178
 destination within a given no. of hops. One computer can have multiple IP addresses also
packets having same source & destination can take different routes.
Source doesn’t decide where to route the packet, but it is decided by the routing tables at
intermediate routers.

54. Which of the following functionalities must be implemented by a transport protocol over and above
the network protocol?GATE 2003

(A) Recovery from packet losses (B) Detection of duplicate packets

(C) Packet delivery in the correct order (D) End to end connectivity
ANS: D
SOL: Transport protocols are mainly for providing end to end connections by making
sockets. Recovery from packet loss & delivery in correct order, duplication is checked by
Data link layer.

WEB TECHNOLOGIES
1. DMSP stands for
A. Distributed Mail System Protocol B. Distributed Message System Pool
C. Distributed Message System Protocol D. Distributed Mai l System Pool

Answer: Option A

Explanation:

DMSP stands for a “ Distributed Mai l system Protocol .

2. The term byte stuffing refers to:

A. Data stuffing used with character oriented B. Data stuffing used with bit oriented
hardware. hardware.
C. data stuffing used with both (A) and(B) D. Data stuffing used with byte oriented
hardware.

Answer & Explanation

Answer: Option A

Explanation:

179
The term byte stuffing refers to data stuffing used with character -oriented hardware

3. In 32bit IP Addressing scheme all 1's represent

A. this computer. B. directed broadcast.
C. limited broadcast. D. loop back.
Answer & Explanation

Answer: Option C

Explanation:

In 32 bit IP Addressing scheme all 1s represent limited broadcast.

4. Which Layer is not present in TCP/ IP model?

A. Application Layer B. Internet Layer
C. Transport Layer D. Presentation Layer
Answer & Explanation

Answer: Option D

Explanation:

Presentation layer is not present in TCP/ IP Model.

5. All exceptions in Java are subclasses of built in class called

A. Exception B. Error.
C. Throwable. D. Raise.
Answer & Explanation

Answer: Option C

Explanation:

All exception in Java are subclasses of built in class called Throwable.

6. Unlike Ipv4, Ipv6 does not include the following field in the base header
A. Next Header field. B. Field for Fragmentation information
C. Flow Label. D. Kind field.
Answer & Explanation

180
Answer: Option B

Explanation:

Unlike Ipv4, Ipv6 does not include the Field for Fragmentation information in the base header.

7. Let most segment of a name inn DNS represents

A. Individual Network. B. Individual computer.
C. Domain name D. Network t ype.
Answer & Explanation

Answer: Option B

Explanation:

Left Most segment of a name in DNS represents- Individual computer

8. A header in CGI script can specify

A. format of the document. B. new location of the document.
C. (A) and (B) both D. start of the document.
Answer & Explanation

Answer: Option A

Explanation:

A header in CGI script can specify - Format of the document & New location of the document.

9. Address 192.5.48.3 belongs to

A. class A. B. class B.
C. class C. D. class D.
Answer & Explanation

Answer: Option C

Explanation:

Address 192.5.48.3 belongs to class C.

10. FDDI (Fiber Distributed Data Interconnect) is an example of

A. token ring. B. token bus
C. star topology D. multipoint network.
181
Answer & Explanation

Answer: Option A

Explanation:

FDDI is an example of token ring.

11. CIDR stands for

A. Classified Internet Domain Routing B. Classless Inter Domain Routing
C. Classless Internet Domain Routing D. Classified Inter Domain Routing
Answer & Explanation

Answer: Option B

Explanation:

The total number of class of IP addresses are 5.

12. A Network uses a star topology if

A. Computers are arranged in a closed loop. B. All computers attach to a central point.
C. All computers attach to a single long cable. D. Computers attach to multiple
hierarchical cables.
Answer & Explanation

Answer: Option B

Explanation:

A Network uses a star topology if all computers attach to a central point.

13. In IP addressing scheme, class used for multicasting is:

A. Class A B. Class B
C. Class C D. Class D
Answer & Explanation

Answer: Option D

Explanation:

In IP addressing scheme, class used for multicasting is class D.

14. The total number of class of IP address are

A. 3. B. 4.
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 C. 5. D. 9.
Answer & Explanation

Answer: Option C

Explanation:

15. In TCP protocol header 'checksum' is of___________

A. 8 bits B. 16 bits
C. 32 bits D. 64 bis
Answer & Explanation

Answer: Option B

Explanation:

In TCP protocol header checksum is of 16 bits.

16. Error detecting method that can detect more errors without increasing additional information in
each packet is
A. checksum B. even parity mechanism
C. CRC D. odd parity mechanism.
Answer & Explanation

Answer: Option C

Explanation:

Error detecting method that can detect more errors without increasing additional information in each
packet is CRC.

17. Parent class of all Java classes is

A. java.lang.system B. java.lang.object
C. java.lang.class D. java.lang.reflect.object
Answer & Explanation

Answer: Option B

Explanation:

Parent class of all Java classes is java.lang.object.

18. Hardware that calculates CRC(Cyclic Redundancy Check) uses:

A. Shift register B. Xor unit
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 C. Both (A)and (B) D. Instruction register
Answer & Explanation

Answer: Option B

Explanation:

Hardware that calculates CRC uses shift register and Xor unit.

19. Except ions of type error inn JAVA are handled by

A. User program B. Java run time environment
C. Operating system kerne D. Interrupt
Answer & Explanation

Answer: Option B

Explanation:

Exceptions of type error in JAVA are handled by JAVA run time environment.

20. MTU is specified by

A. IP Datagram size B. Hardware technology
C. TCP Segment size D. None of the above.
Answer & Explanation

Answer: Option B

Explanation:

MTU is specified by hardware technology.

21. Consider the HTML t able definition given below: (GATE 2009)

< table border=1>

<tr>
<td rowspan=2> ab </td>
<td colspan=2> cd </td>
</tr>
<tr>
<td> ef </td>
<td rowspan=2> gh </td>
</tr>
<tr> <td colspan=2> ik </td>
</tr>
</table>
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 The number of rows in each column and the number of columns in each row are:
A. (2,2,3) and (2,3,2) B. (2,2,3) and (2,2,3)
C. (2,3,2) and (2,3,2) D. (2,3,2) and (2,2,3)
Answer & Explanation

Answer: Option C

Explanation:

Here two td command used in the first tr command and three td command used in second tr command,
So required rows in each column is <2,3,2>

22. HTML (HyperText Markup Language) has language elements which permit certain actions other
than describing the structure of the web document. Which one of the following actions is NOT
supported by pure HTML (without any server or client side scripting) pages?(GATE 2011)
A. Embed web objects from different B. Refresh the page automatically after a
sites into the same page specified interval
C. Automatically redirect to another D. Display the client time as
page upon download part of the page
Answer & Explanation

Answer: Option D

Explanation:

As per Theory.

COMPUTER ORGANIZATION

YEAR 2001

Question. 1
More than one word are put in one cache block to
(E) Exploit the temporal locality of reference in a program
(F) Exploit the spatial locality of reference in a program
(G) Reduce the miss penalty
(H) None of the above

185
SOLUTION

Cache is the small memory which has a very less access time. So it is used for temporal locality of
reference whereas virtual memory is for spatial locality of reference.
Hence (A) is correct option.

Question. 2
A low memory can be connected to 8085 by using
(A) INTER (B) RESET IN
(C) HOLD (D) READY

SOLUTION
memory can be connected to 8085 by using READY signal. If READY is set then communication is
possible.Hence (D) is correct option.

Question. 3
Suppose a processor does not have any stack pointer register. Which of the following statements is true ?
(A) It cannot have subroutine call instruction
(B) It can have subroutine call instruction, but no nested subroutine calls.
(C) Nested subroutine calls are possible, but interrupts are not.
(D) All sequences of subroutine calls and also interrupts are possible

SOLUTION

Stack pointer register holds the address of top of stack, which is the location of memory at which the
CPU should resume its execution after servicing some interrupt or subroutine call.
So if SP register not available then no subroutine call instructions are possible.
Hence (A) is correct option.

Question. 4
A processor needs software interrupt to
(E) Test the interrupt system of the processor.
(F) Implement co-routines.
(G) Obtain system services which need execution of privileged instructions.
(H) Return from subroutine.

SOLUTION
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A CPU needs software interrupt to obtain system services which need execution of privileged
instructions.
Hence (C) is correct opton.

Question. 5
A CPU has two modes-privileged and non-privileged. In order to change the mode from privileged to
non-privileged.
(A) A hardware interrupt is needed.

(E) A software interrupt is needed.

(F) A privileged instruction (which does not generate an interrupt) is needed.
(G) A non-privileged instruction (Which does not generate an interrupt) is needed.

SOLUTION

A software interrupt is initiated by some program module which need some CPU services, at that time
the two modes can be interchanged. Hence (B) is correct option.

Question. 6
The process of assigning load addresses to the various parts of the program and adjusting the code and
date in the program to reflect the assigned addresses is called
(A) Assembly (B) Parsing
(C) Relocation (D) Symbol resolution

SOLUTION

Load addresses are assigned to various parts of the program, the program can be loaded at any location
in memory. This location is added to all addresses in the code, to get correct references.
This makes a code re-locatable. Hence (C) is correct option.

Question. 7
Which of the following requires a device driver ?
(A) Register (B) Cache
(C) Main memory (D) Disk

SOLUTION

Device driver is the program which co-ordinates with CPU to regulate the devices. Register, cache &
187
main memory are directly connected to CPU.
So only Disk from given options require device drivers. Hence (D) is correct option.
Question. 8
Which is the most appropriate match for the items in the first column with the items in the second
column
(X.) Indirect Addressing (I.) Array implementation
(Y.) Indexed Addressing (II.) Writing re-locatable code
(Z.) Base Register Addressing (III.) Passing array as parameter

(A) (X, III) (Y, I) (Z, II) (B) (X, II) (Y, III) (Z, I)
(C) (X, III) (Y, II) (Z, I) (D) (X, I) (Y, III) (Z, II)

SOLUTION

Indexed addressing is used for array implementation where each element has indexes. Base register is
used to re-locatable code, where starts from base address & then all local addresses as added to base
address.
Indirect addressing is done when array is passed as parameter only name is passed.
Hence (A) is correct option.

Question. 9
Consider the following data path of a simple non-pilelined CPU. The registers A, B, A1, A2, MDR the
bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8 X (2:1) and the
DEMUX is of size 8 X (1:2). Each memory operation takes 2 CPU clock cycles and uses MAR
(Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.

The CPU instruction “push r”, where = A or B, has the specification

M [ SP] !r

SP ! SP − 1
188
How many CPU clock cycles are needed to execute the “push r” instruction ?
(A) 2 (B) 3
(C) 4 (D) 5

SOLUTION

Push ‘r’
Consist of following operations
M [ SP] !r
SP ! SP − 1
‘r’ is stored at memory at address stack pointer currently is, this take 2 clock cycles.
SP is then decremented to point to next top of stack. So total cycles = 3
Hence (B) is correct option.

Question. 10
Which of the following does not interrupt a running process ?
(A) A device (B) Timer
(C) Scheduler process (D) Power failure

SOLUTION

A device can request interrupt service. A timer when finishes or power failure causes a running process
to stop. But a scheduler process doesn’t do this.
Hence (C) is correct option.

YEAR 2002

Question. 11
A device employing INTR line for device interrupt puts the CALL instruction on the data bus while
(A) INTA is active (B) HOLD is active
(C) READY is active (D) None of the above

LUTION

INTR is a signal which if enabled then microprocessor has interrupt enabled it receives high INR signal
& activates INTA signal, so another request can’t be accepted till CPU is busy in servicing interrupt.
Hence (A) is correct option.

189
Question. 12
In 8085 which of the following modifies the program counter ?
(E) Only PCHL instruction
(F) Only ADD instructions
(G) Only JMP and CALL instructions
(H) All instructions

SOLUTION

Program counter is the register which has the next location of the program to be executed next. JMP &
CALL changes the value of PC. PCHL instruction copies content of registers H & L to PC.
ADD instruction after completion increments program counter. So program counter is modified in all
cases.
Hence (D) is correct option.

Question. 13
In serial data transmission, every byte of data is padded with a ‘0’ in the beginning and one or two ‘1’s
at the end of byte because
(E) Receiver is to be synchronized for byte reception
(F) Receiver recovers lost ‘0’s and ‘1’ from these padded bits
(G) Padded bits are useful in parity computation.
(H) None of the above

SOLUTION

In serial data transmission the sender & receiver needs to be synchronized with each other. Receiver
should know when 1 byte of data has been sent. 0 & 1’s which are padded tell the receiver to
synchronize.
Hence (A) is correct option.

uestion. 14
Which of the following is not a form of memory ?
(A) Instruction cache (B) Instruction register
(C) Instruction opcode (D) Translation-a-side buffer

SOLUTION

190
Instruction register stores instruction, look-a-side buffer & instruction cache are also memory.
But instruction opcodes are the opcodes related to an instruction which are not part of memory
hierarchy.
Hence (C) is correct option.

Question. 15
In the C language
(3) At most one activation record exists between the current activation record and the activation record
for the main.
(4) The number of activation records between the current activation record and the activation record for
the main depends on the actual function calling sequence.
(5) The visibility of global variables depends on the actual function calling sequence.
(6) Recursion requires the activation record for the recursive function to be saved on a different stack
before the recursive fraction can be called.

SOLUTION

Activation record is the contiguous memory locations where the data needed by the program is kept so
at most one activation record exist between current activation record & the record for the main.
Hence (A) is correct option.

Question. 16
In the absolute the addressing mode
(E) The operand is inside the instruction
(F) The address of the operand is inside the instruction
(G) The register containing the address of the operand is specified

nside the instruction

(D) The location of the operand is implicit

SOLUTION

In absolute addressing mode, no need of giving operand, the operand are implicit, instruction itself has
knowledge of operands.
Hence (D) is correct option.

Question. 17
The performance of a pipelined processor suffers if

191
(E) The pipelined stages have different delays
(F) Consecutive instructions are dependent on each other
(G) The pipeline stages share hardware resources
(H) All the above

SOLUTION

Pipelining is a method to execute a program breaking it in several independent sequence of stages.

In that case pipeline stages can’t have different delays, no dependency among consecutive instructions
& sharing of hardware resources shouldn’t be there. So option (D) is true
Hence (D) is correct option.

Question. 18
Horizontal microprogramming
t Does not require use of signal decoders
t Results in larger sized microinstructions than vertical microprogramming
t Uses one bit for each control signal
t All of the above

SOLUTION

192
In horizontal microprogramming the instruction size is not large, & no
decoding is required. But 1 bit is used for all control signals. Hence (C) is
correct option.

YEAR 2003

Question. 19
For a pipelined CPU with a single ALU, consider the following situations
1. The j + 1 − st instruction uses the result of j − th instruction as an
operand
2. The execution of a conditional jump instruction
3. The j − th and j + 1 − st instructions require the ALU at the same time
Which of the above can cause a hazard?
(A) 1 and 2 only (B) 2 and 3 only
(C) 3 only (D) All the three

SOLUTION

Case 1 is here of data dependency, this can’t be safe with single ALU so
read after write.
Case 2 Conditional jumps are always hazardous they create conditional
dependency in pipeline
Case 3 This is write after read problem or concurrency dependency so
hazardous
All the three are hazardous.
Hence (D) is correct option.

Question. 20
Consider an array multiplier for multiplying two n bit numbers. If each
gate in the circuit has a unit delay, the total delay of the multiplier is
(A) Θ(1) (B) Θ(log n)
(C) Θ(n) (D) Θ(n2)

SOLUTION
The no. of gates used in n bit array multiplier (n X n) is 2n − 1. So. if
every single gate takes unit delay, then total delay 0(2n − 1) = 0(n) It is of
linear order
Hence (C) is correct option.

193
Question. 21
Consider the ALU shown below

If the operands are in 2’s complement representation, which of the following operations can be
performed by suitably setting the control lines K and C0 only (+ and - denote addition and subtraction
respectively)?
(A) A + B, and A − B,but notA + 1
(B) A + B,and A + 1,but notA − B
(C) A + B,but not A − B,orA + 1
(D) A + B,and A − B,andA + 1

SOLUTION

This is the ckt to add two numbers in 2’s complement form. K & C0 are set to 1. So A + B & A − B using
bit adders can be done. Also since C0 = 1 & in case B 0, B1........ all are 0 then it gives A + 1.
Hence (D) is correct option.

Data for Q. 22 & 23 are given below.

Consider the following assembly language program for a hypothetical processor. A,B and C are 8 bit
registers. The meanings of various instructions are shown as comments.
MO
V B, # 0 ; B!0
MO
V C, # 8 ; C!8
Z: CMP C, # 0 ; compare C with 0
JZX ; jump to X if zero flag is set
SUB C, # 1 ; C!C−1

194
 RRC A, # 1 ; right rotate A through carry
; by one bit. Thus: if the
; initial values of A and the
; carry flag are a7 ....... a0 and c0
; respectively, their values
; after the execution of this
; instruction will be c0 a7 .....a1
; and a0 respectively.
JCY ;jump to Y if carry flag is set
JMP Z ; jump to Z
Y: ADD B, # 1 ; B!B+1
JMP Z ; jump to Z
X:

Question. 22
If the initial value of register A is A0, the value of register B after the
program execution will be
(A) the number of 0 bits in A0
(B) the number of 1 bits in A
(C) A0
(D) 8

SOLUTION

Here value of B incremented by 1 only if carry flag is 1, carry is filled

using right rotation, so B will store the no. of is in A0.
Hence (B) is correct option.

Question. 23
Which of the following instructions when inserted at location X will
ensure that the value of register A after program execution is the same as
its initial value?
(A) RRC A,# 1
(B) NOP ; no operation
(C) LRC A, # 1 ; left rotate A through carry flag by one bit
(D) ADD A, # 1
195
SOLUTION

In the end of program execution to check whether both initial and final value of register A is A0, we need
to right rotate register A through carry by one bit.
Hence (A) is correct option.

YEAR 2004

Question. 24
Which of the following addressing modes are suitable for program relocation at run time?
1. Absolute addressing
2. Based addressing
3. Relative addressing
4. Indirect addressing
(A) 1 and 4 (B) 1 and 2
(C) 2 and 3 (D) 1,2 and 4

SOLUTION

Program relocation at run time transfers complete block to some memory locations. This require as base
address and block should be relatively addressed through this base address.
This require both based addressing and relative addressing mode. Hence (C) is correct option.

Question. 25
Consider a multiplexer with X and Y as data inputs and Z as control input.Z = 0 selects input X , and Z =1
selects input Y . What are the
connection required to realize the 2-variable Boolean function
f = T + R, without using any additional hardware?
(A) R to X, 1 to Y, T to Z (B) T to X, R to Y, T to Z
(C) T to X, R to Y, 0 to Z (D) R to X, 0 to Y, T to Z

196
SOLUTIO
N

We require f = T + R
We have MUX equation
f = Z' x + zy
Now if we make following ckt

Truth table So X = R Y = 1 Z = T

R T F Z
f =T'R+T
0 0 0 0
= (T + T ')(T + R)
0 1 1 1
f =T+R
1 0 1 0
1 1 1 1

Hence (A) is correct option.

Data for Q. 26 & 27 are given below.

Consider the following program segment for a hypothetical CPU having

197
three user registers R1,R2 and R3.

198
 Instruction Operation Instruction Size
(in words)
MOV R1,5000 ;R1←Memory[5000] 2
MOV R2,R3 ;R2←R2+R3 1
ADD R2,R3 ;R2←R2+R3 1
MOV 6000,R2 ;Memory[6000]←R2 2
HALT ;Machine halts 1

Question. 26
Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting
from memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after
executing the HALT instruction, the return address (in decimal) saved in the stack will be
(A) 1007 (B) 1020
(C) 1024 (D) 1028

SOLUTION

Byte addressable so 1 word require 4 bytes.

Instruction no. Size Address range
1 2 1000-1007
2 1 1008-1011
3 1 1012-1015
4 2 1016-1023
5 1 1024-1027
Next location 1028.
CPU has executed the HALT instruction so next time the CPU will resume at next location i.e. 1028
which would be at the top of stack.

Hence (D) is correct option.

Question. 27
Let the clock cycles required for various operations be as follows:
Register to/from memory transfer: 3 clock cycles

199
ADD with both operands in register: 1 clock cycle
Instruction fetch and decode: 2 clock cycles per word
The total number of clock cycles required to execute the program is
(A) 29 (B) 24
(C) 23 (D) 20

SOLUTION

The clock cycles are per block so if an instruction size is 2 then it requires
twice no. of clock cycles.
Instruction No. Size No. of clock cycles
1 2 3X2+2 8
2 1 1X3+2 5
3 1 1(add only) 1
4 2 3X2+2 8
5 1 2(fetch & decode) 2

Total 24

Hence (B) is correct option.

Question. 28
Consider a small two-way set-associative cache memory, consisting of
four blocks. For choosing the block to be replaced, use the least recently
used (LRU) scheme. The number of cache misses for the following
sequence of block addresses is 8, 12,0, 12,8
(A) 2 (B) 3
(C) 4 (D) 5

SOLUTION

200
P4 = 5 −4 = 1
Total = 22
Average turnaround time = 22/4
= 5.5
Hence (A) is correct option.

Question. 22

Consider a system with a two-level paging scheme in which a regular memory access takes 150
nanoseconds, and servicing a page fault takes 8 milliseconds. An average instruction takes 100
nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is 99%, and the page
fault rate is one in every 10,000 instructions. What is the effective average instruction execution
time?

(A) 645 nanoseconds (B) 1050 nanoseconds

(C) 1215 nanoseconds (D) 1230 nanoseconds
SOLUTION
Memory access time
=0.90*150 +0.10*(150 +150)
=135 +30
=165 ns
The error rate = 1/10000 = 10−4
CPU burst time = 100 ns
Total execution time
=[100 +2[165] +10−4*8*106]
=100 +330 +800
=100 +1130
=1230 ns
Hence (D) is correct option.

Question. 23

Consider two processes P1 and P2 accessing the shared variables X and Y protected by two
binary semaphores Sx and Sy respectively, both initialized to 1. P and V denote the usual
semaphore operators, where P decrements the semaphore value, and V increments the
semaphore value. The pseudo-code of P1 and P2 is as follows:

P1: P 2:
{ {
while true do while true do
L1:……… L3:………
L2:……… L4:………
X = X+1; Y = Y+1;
Y = Y-1; X = Y-1;
V(Sx); V(Sy);
V(Sy); V(Sx);
} }

100
After than 12 & 8 are referred but this does not cause any miss So no. of miss = 3
This stars ()) shows the misses. Hence (B) is correct option.

Question. 29
The microinstructions stored in the control memory of a processor have a width of 26 bits. Each
microinstruction is divided into three fields: a micro-operation field of 13 bits, a next address field (X),
and a MUX select field (Y). There are 8 status bits in the inputs of the MUX.

How many bits are there in the X and Y fields, and what is the size of the control memory in number of
words?
(A) 10, 3, 1024 (B) 8, 5, 256
(C) 5, 8, 2048 (D) 10, 3, 512

SOLUTION

MUX has 8 states bits as input lines so we require 3 select inputs to select & input lines.
No. of bits in control memory next address field
= 26 − 13 − 3
= 10
10 bit addressing, we have 210 memory size. So X, Y size = 10,3,1024
Hence (A) is correct option.

Question. 30
A hard disk with a transfer rate of 10 M bytes/second is constantly

201
transferring data to memory using DMA. The processor runs at 600 MHz.
and takes 300 and 900 clock cycles to initiate and complete DMA transfer
respectively. If the size of the transfer is 20 Kbytes, what is the percentage
of processor time consumed for the transfer operation?
(A) 5.0% (B) 1.0%
(C) 0.5% (D) 0.1%

SOLUTION
Transfer rate = 10 MB ps
Data = 20 KB
Time = 20 X210 = 2 X 10−3
10 X 220
= 2 ms
Processor speed = 600 MHz
= 600 cycles/sec.
Cycles required by CPU = 300 + 900
For DMA = 1200
1200
So time = = .002 ms
6
600 X 10
.002
%= X 100
2
= 0.1%
Hence (D) is correct.

Question. 31
A 4-stage pipeline has the stage delays as 150, 120, 160 and 140
nanoseconds respectively. Registers that are used between the stages have
a delay of 5 nanoseconds each. Assuming constant clocking rate, the total
time taken to process 1000 data items on this pipeline will be
(A) 120.4 microseconds (B) 160.5 microseconds
(C) 165.5 microseconds (D) 590.0 microseconds

SOLUTION

Delay = 5 ns/stage
Total delay in pipline.

202
 = 150 + 120 + 160 + 140 = 570 Delay due to 4 stages.
Stage 1 delay 1 stage 2 delay 2 stage 3 stage 4 5 X 3 = 15
Total = 570 + 15 = 585
Total time = 1000 data items 585 ns

= 165.5 microseconds. Hence (C) is correct option

YEAR 2005

Question. 32
Which one of the following is true for a CPU having a single interrupt request line and a single interrupt
grant line?
(A) Neither vectored interrupt nor multiple interrupting devices are possible
(B) Vectored interrupts are not possible but multiple interrupting devices are possible
(C) vectored interrupts and multiple interrupting devices are both possible
(D) vectored interrupt is possible but multiple interrupting devices are not possible

SOLUTION

CPU has single interrupt request and grant line

Here multiple request can be given to CPU but CPU interrupts only for highest priority interrupt so
option (A) & (D) are wrong.
But here in case of single interrupt lines definitely vectored interrupts are not possible.
Hence (B) is correct option.

203
Question. 33
Normally user programs are prevented from handing I/O directly by I/O
instructions in them. For CPUs having explicit I/O instructions, such I/O
protection is ensured by having the I/O instructions privileged. In a CPU
with memory mapped I/O, there is no explicit I/O instruction. Which one
of the following is true for a CPU with memory mapped I/O?
(E) I/O protection is ensured by operating system routine(s)
(F) I/O protection is ensured by a hardware trap
(G) I/O protection is ensured during system configuration
(H) I/O protection is not possible

SOLUTION

In memory mapped I/0 the complete system (memory + I/0 ports) hold the
same set of addresses. They are considered to be the part of that memory
only. This management is done by OS only.
Hence (A) is correct option.

Question. 34
What is the swap apace in the disk used for?
(E) Saving temporary html pages
(F) Saving process data
(G) Storing the super-block
(H) Storing device drivers

SOLUTION

Swap space is the memory pre allowed to store process’s data. This can be
compared with virtual memory. The data required to complete process is
kept here.
Hence (B) is correct option.

Question. 35
Increasing the RAM of a computer typically improves performance
because
(E) Virtual memory increases
(F) Larger RAMs are faster
204
(C) Fewer page faults occur
(D) Fewer segmentation faults occur

SOLUTION

Due to increase in RAM size all the pages required by CPU are available in RAM so page fault chance
are less, so virtual memory access chances are less and latency is reduced for secondary memory. Hence
(C) is correct option.

Question. 36
Consider a three word machine instruction
ADD A [R0],@B
The first operand (destination) “A [R0]” uses indexed addressing mode with R0 as the index register.
The second operand (source) "@B" uses indirect addressing mode. A and B are memory addresses
residing at the second and the third words, respectively. The first word of the instruction specifies the
opcode, the index register designation and the source and destination addressing modes. During
execution of ADD instruction, the two operands are added and stored in the destination (first operand).
The number of memory cycles needed during the execution cycle of the instruction is
(A) 3 (B) 4
(C) 5 (D) 6

SOLUTION
ADD A [ R 0],@B
This is instruction has 3 computational parts. ADD instruction requires 1 machine cycle, A [ R0] here R0
is index register which has starting address of index then this index has the block address. This whole
operation require 3 machine cycles. Now @ B is indirect addressing. This takes 2 machine cycles. So
overall 1 + 3 + 2 = 6 machine cycles.
Hence (D) is correct option.

205
Question. 37
Match List-I with List-II and select the correct answer using the codes
given below the lists:

List-I List-II
A. A [1] = B [j]; 1. Indirect addressing
B. while [* A ++]; 2. Indexed addressing
C. int temp=*x ; 3. Auto increment
Codes:
A B C
(A) 3 2 1
(B) 1 3 2
(C) 2 3 1
S 123

SOLUTION
LIST-I LIST-II
(iv) A [1] = B [ J]; 2 Indexed addressing here the
indexing is used
(v) While [) A ++] 3. Auto increment the memory
locations is A are automatically
incriminated.
(vi) int temp=) X
1. Indirect addressing here temp
is assigned the value of int type
stored at the address contained
in X
A2
B3
C1
Hence (C) is correct option.

Question. 38

206
Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU generates 32 bit
addresses. The number of bits needed for cache indexing and the number of tag bits are respectively
(A) 10,17 (B) 10,22

(C) 15,17 (D) 5,17

SOLUTION

Cache is direct mapped.

Size of Cache = 32 KB
= 25 X 210 B
= 215 Bytes.
Require 15 bits for cache addressing so CPU address has tag and index
No. of tag bits = 32 − 15 = 17
From 15 Cache addressing bits consist of blocks & words. Each block has 32 words (bytes) So require 5
bit.
Index = block + word
Block = 15 − 5 = 10

So, 10, 17
Hence (A) is correct option.

Question. 39
A 5 stage pipelined CPU has the following sequence of stages
IF-Instruction fetch from instruction memory.
RD-Instruction decode and register read,
EX- Execute:ALU operation for data and address computation,
MA-Data memory access-for write access the register read at
RD stage it used,
WB-register write back.
Consider the following sequence of instruction:
I 1 : LR0,Locl; R0 <= M[Locl]
I 2 AR0,R0; R0 <= R0 + R0
I 3 AR2,R0; R2 <= R2 − R0
Let each stage take one clock cycle.
What is the number of clock cycles taken to complete the above sequence of instruction starting from
the fetch of I1?
207
(A) 8 (B) 10
(C) 12 (D) 15

SOLUTION
Order of phase in instruction cycle.
IF " A 3" E X MA " WB
1 2 3 4 5 6 7 8 9 10
R 0 ! M [ LOC] IF RD EX MA WB

R 0 ! R 0 + R0 IF RD EX MA WB
R 2 ! R 2 − R0 IF RD EX MA WB

R 0 ! R 0 + R0 can’t start before 3 since R0 has not been read by I1.

R 2 ! R 2 − R0 can’t start before 6th since I2 has not executed

R 0 ! R 0 + R0 till 5th cycle

Total cycles = 10
Hence (B) is correct option.

Question. 40
A device with data transfer rate 10 KB/sec is connected to a CPU. Data is
transferred byte-wise. Let the interrupt overhead be 4 μ sec.

The byte transfer time between the device interface register and CPU or
memory is negligible. What is the minimum performance gain of
operating the device under interrupt mode over operating it under program
controlled mode?
(A) 15 (B) 25
(C) 35 (D) 45

SOLUTION

Data transfer rate = 10000 B/sec

Total data = 25 X 103
Rate = 104
Performance gain = 10254 X 100
= 25%

208
Hence (B) is correct option.

Question. 41

Consider a disk drive with the following specification

16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is
operated in cycle stealing mode whereby whenever one byte word is ready it is sent to memory;
similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle.
Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during
DMA operation is
(A) 10 (B) 25
(C) 40 (D) 50

SOLUTION

Disk revolutions = 3000 PM or 50 RPS

At a time can read in
One revolution = 512 KB
= 219 )
Tracks read/sec 22 50

= 50 X 217 per sec.

Interrupt = .2621 sec

Percentage gain = .26211 X 100

, 26%

Hence (B) is correct option.

Data for Q. 42 & 43 are given below

Consider the following data path of a CPU

209
The, ALU, the bus and all the registers in the data path are of identical
size. All operations including incrementation of the PC and the GPRs are
to be carried out in the ALU. Two clock cycle are needed for memory read
operation-the first one for loading data from the memory but into the
MDR.

Question. 42
The instruction “add R0,R1” has the register transfer in terpretation R0 <=
R0 + R1. The minimum number of clock cycles needed for execution
cycle of this instruction is
(A) 2 (B) 3
(C) 4 (D) 5

SOLUTION
R0 ! R 0 + R1
First cycle require to fetch operands two cycles required for this. The
next cycle required to use ALU to perform ADD operation.
So total cycles required = 3

Hence (D) is correct option.

Question. 43
The instruction “call Rn, sub” is a two word instruction. Assuming that PC
is incremented during the fetch cycle of the first word of the instruction,
its register transfer interpretation is
Rn <= PC = 1;
PC <= M [PC];
210
The minimum number of CPU clock cycles needed during the execution cycle of this instruction is
(A) 2 (B) 3
(C) 4 (D) 5

SOLUTION
Rn ! PC + 1 PC = M [ PC]
Program outer is itself a register so incremented in 1 cycle.
Now fetching the memory at PC & the value of at address stored in PC takes 2 cycles.
So total 1 + 2 = 3 cycles. Hence (B) is correct option.

Question. 44
A CPU has 24-bit instructions. A program starts at address 300(in decimal). Which one of the
following is a legal program counter (all values in decimal)?
(A) 400 (B) 500
(C) 600 (D) 700

SOLUTION

Size of instruction = 24 bits.

Since each instruction require 243 = 3 bytes & start address is 300 so the address for this range can be
multiple of 3 only so 600.
Hence (C) is correct option.

YEAR 2006

Question. 45
A CPU has a cache with block size 64 bytes. The main memory has k banks, each bank being c bytes
wide. Consecutive c-bute chunks are mapped on consecutive banks with warp-around. All the k banks
can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access
may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by
accessing all the k banks in parallel. Each iteration requires decoding

211
the bank numbers to be accessed in parallel and this takes k /2 ns. The
latency of one bank access is 80 ns. If c = 2 and k=24, then latency of
retrieving a cache block starting at address zero
from main
memory is (B) 104 ns
(A) 92 ns (D) 184 ns
(C) 172 ns

SOLUTION

Size of Cache block = 64 B

No. of main memory banks K = 24
Size of each bank C = 2 bytes.

So time taken for < access.

T = decoding time + latency time
T = K/2 + latency
= 12 + 80
= 92 ns.
But since C = 2 for accesses. 2
X 92 = 189 ns.
Hence (D) is correct option

Question. 46
A CPU has five-stages pipeline and runs at 1GHz frequency. Instruction
fetch happens in the first stage of the pipeline. A conditional branch
instruction computes the target address and evaluates the condition in the
third stage of the pipeline. The processor stops fetching new instructions
following a conditional branch until the branch outcome is known. A
program executes 109 instructions out of which 20% are conditional
branches. If each instruction takes one cycle to complete on average, then
total execution time of the program is
(A) 1.0 second (B) 1.2 seconds
(C) 1.4 seconds (D) 11.6 seconds

SOLUTION

Given that 80% of 109 instruction require single cycle i.e. no conditional
branching & for 20% an extra cycle required.
Time taken by 1 cycle = 10−9 sec.
212
 Total time = 10−9 b 10080 X 109 + 10020 X 2 X 109l
= 10−9 X 109 b 54 + 25 l
6
= 5 = 1.2 seconds.
Hence (B) is correct option.

Question. 47
Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction “bbs reg, pos,
labbel” jumps to label if bit in position pos of register operand reg is one. a register is 32 bits wide and
the bits are numbered 0 to 31, bit in position 0 being the least significant. Consider the following
emulation of this instruction on a processor that does not have bbs implemented.
temp!reg and mask
Branch to label if temp is non-zero
The variable temp is a temporary register. For correct emulation the variable mask must be generated
by
(A) mask! 0x1 << pos (B) musk! 0x ffffffff >> pos
(C) mask! pos (D) msdk! 0xf

SOLUTION

Given instruction bbs reg, pos, Label

Here pos bit decided whether to jump to label. So all other bits in temp set to 0.
Temp ! reg and mask.
So of temp is not zero branch to label.
So shifting left over.
Mask ! 0 X 1 << pos Hence (D) is correct option.

Data for Q. 48 & Q. 49 are given below. Solve the problem and choose the correct answers.
Consider two cache organizations: The first one is 32 KB 2-way set associative with 32-bytes block
size. The second one is of the same

213
size but direct mapped. The size of an address is 32 bits in both cases A2-
to-1 multiplexes has latency of 0.6 ns where a k-bit comparator has a
latency of k /10ns. The hit latency of the set associative organization is h1
while that of the direct mapped one is h2.

Question. 48
The value of h1 is
(A) 2.4ns (B) 2.3ns
(C) 1.8ns (D) 1.7ns

SOLUTION

2 way set-associative Cache.

Size 32 KB
2 way so 16 KB sets.
Require 14 bits for 214 B
Block size = 32 Byte.
= 5 bits.
No. of blocks14 − 5 = 9

Tag index

h1 = 1810 + 0.6 ns

= 2.4 ns.

Hence (A) is correct option.

Question. 49
The value of h2 is
(A) 2.4ns (B) 2.3ns

214
(C) 1.8ns (D) 1.7ns

SOLUTION

Similarly to previous question. The CPU address is same but Direct coaching require for 32 KB 15 bits.
Which would be 10 + 5 = 17

17 10 5
h2 = 1710 + 0.6
= 2.3 ns Hence (B) is correct option.

Data for Q. 50 & Q. 51 are given below.

A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a two dimensional
array of size 512X512 with elements that occupy 8-bytes each. Consider the following two C code
segments,
P1 and P2,
P1 : for (i=0;i<512;i++)
{
for (j=0;j<512;j++)
{
x+=A[i][j];
}
}
P2 : for (i=0;i<512;i++) {
for (j=0;j<512;j++) { {x+=A[j][i];}
}
}
P1 and P2are executed independently with the same initial state, namely, the array A is not in the cache
and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be
M2.

Question. 50
The value of M1 is

215
(A) 0 (B) 2048
(C) 16384 (D) 262144

SOLUTION
Given loop P1 accesses array A row wise & P2 access column wise.
M1 = ?
Cache Capacity = 215 B.
1 element = 23 B
Total elements 512 X 512
Total data = 512 X 512 X 8 B =
221 B
Block size = 128 B
1 block can have = 1288 = 16 elements
512 X 512
So total blocks require = 16

= 1638 blocks
Since the memory is initially empty so all blocks are required at least
once.
So, M1 = 16384 Hence (C) is
correct option.

Question. 51
The value of the ratio M1/M2 is
(A) 0 (B) 1/16
(C) 1/8 (D) −16

SOLUTION
Now M2 =?

In the case (P2 loop) the array is accessed column wise, so even the block
brought for A [0][0] − A[0][15] would not be used for second column wise
access i.e. A[1][0] So new block need to swap, similarly for A[3][0] & So
on. This would continue for every element, since memory is contiguous.
So M2 = 512 X 512 = 262144

216
& M1 = 16384 = 1 M2 262144 16

Hence (B) is correct option.

YEAR 2007

Question. 52
Consider a 4-way set associative cache consisting of 120 lines with a line size of 64 words. The CPU
generates a 20-bit address of a word in main memory. The number of bits in the TAG, LINE and
WORD fields are respectively
(A) 9,6,5 (B) 7,7,6
(C) 7,5,8 (D) 9,5,6

SOLUTION

4 way set associative cache

Size = 128 X 64 words
128 X 64
But for 4 sets = 32 X 64 4

For 32 lines we require 5 bits. For 64 words we require 6 bits.

Indexing = 6 + 5 = 11 bits. Tag = 20 − 11
= 9 bits

9 5 6

Hence (D ) is correct option.

Question. 53
Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 bytes of
data are stored in a bit serial manner in a sector. The capacity of the disk pack and the number of bits
required to specify a particular sector in the disk are respectively
(A) 256 Mbytes, 19 bits (B) 256 Mbyte, 28 bits
(C) 512 Mbytes, 20 bits (D) 64 Gbyte, 28 bits

217
SOLUTION

Surface = 6 Tracks = 16 X 128

Sectors = 16 X 128 X 256
= 2 4 X 2 7 X 28 = 219
So 19 lines are required to address all sectors. Bytes = 219 X 512 B
= 219 X 29 B = 228
= 256 MB Hence (A) is correct option.

Question. 54
Consider a pipelined processor with the following four stages
IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Bank
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock
cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle
and the MUL instruction need 3 clock cycles in the EX stage. Operand forwarding is used in the
pipelined processor. What is the number of clock cycles taken to complete the following sequence of
instructions?

ADD R2, R1, R0 R2!R1+R0

MUL R4, R3, R2 R4!R3*R2
SUB R6, R5, R4 R6!R5−R4
(A) 7 (B) 8
(C) 10 (D) 14

SOLUTION

Order of instruction cycle-phases.

IF " ID " EX " WB
We have 3 instructions.

1 2 3 4 5 6 7 8
R 2 ! R 1 ! R0 IF ID EX WB

R 4 ! R 3 ! R2 IF ID EX EX EX WB

R 6 ! R 5 ! R4 IF ID - - EX WB
218
Represent wait in pipeline due to result dependently. Clock cycles require = 8
Hence (B) is correct option.

Data for Q. 55, 56 & 57 are given below.

Consider the following program segment. Here R1, R2 and R3 are the
general purpose registers.

Instruction Operation Instruction size

(no. of words)
MOV R1,(3000) R1!M[3000] 2
LOOP:
MOV R2,R1 R2!M[R3] 1
ADD R2,R1 R2!R1+R2 1
MOV (R3),R2 M(R3]!R2 1
INC R3 R3!R3+1 1
DEC R1 R1!R1-1 1
BNZ LOOP Branch on not zero 2
HALT Stop

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The
content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the
memory location 100. All the numbers are in decided.

Question. 55

Assume that the memory is word addressable. The number of memory references for accessing the data
in executing the program completely is
(A) 10 (B) 11
(C) 20 (D) 21

219
SOLUTION
1st memory reference R1 ! M 3000 and then in the loop which
^h
runs for 10 times there are 2 memory reference every iteration.
10 X 2 = 20
Instruction Words Location
Total 20 + 1 = 21
R2 ! M [ R3]
M [R3] ! R2
Hence (D) is correct option

Question. 56
Assume that the memory is word addressable. After the execution of this program, the content of memory
location 2010 is
(A) 100 (B) 101
(C) 102 (D) 110

SOLUTION

Program stores results from 2000 to 2010. It stores 110, 109, 108......100 at 2010 location.
DEC R1
Hence (A) is correct option.

Question. 57
Assume that the memory is byte addressable and the word size is 32 bits. If an interrupt occurs during the
execution of the instruction “INC R3”, what return address will be pushed on to the stack?
(A) 1005 (B) 1020
(C) 1024 (D) 1040

SOLUTION

Now byte addressable memory so 1 word i.e. 4 bytes require 4 addresses.

MOV (R3), R2 1 1016-1019
INC R3 1 1020-1023
DEC R1 1 1024-1027

220
 MOV R1, (3000) 2 1000-1007
MOV R2, R1 1 1008-1011
ADD R2, R1 1 1012-1015

Interrupt occurs during execution of INC R3, So CPU will complete the execution of this instruction and then
Push the next address 1024 to the stack, so after interrupt service the program can be resumed from next
instruction.
Hence (C) is correct option.

Data for Q. 58 & Q. 59 are given below.

Consider a machine with a byte addressable main memory of 216 bytes. Assume that a direct mapped data cache
consisting of 32 lines of 64 bytes each is used in the system. A 50 X 50 two-dimensional array of bytes is stored
in the main memory stating from memory location 1100H.Assume that the data cache is initially empty. The
complete array is accessed twice. Assume that the contents of the data cache do not change in between the two
accesses.

Question. 58
How many data cache misses will occur in total?
(A) 48 (B) 50
(C) 56 (D) 59

SOLUTION

Size of main memory 216 bytes. Size of Cache = 32 X 64 B

= 211 B Size of array = 2500 B
Array is stored in main memory but cache is empty. Size of Cache = 2048 B
So no. of page faults = 2500 − 2048 = 452
For second access = 452 X 2 = 904 Total = 1356
Hence (C) is correct option.

221
Question. 59
Which of the following lines of the data cache will be replaced by new
blocks in accessing the array
(A) line 4 to line 11 (B) line 4 to line 12
(C) line 0 to line 7 (D) line 0 to line 8

SOLUTION

No of page faults = 452

One line has 64 B
So the line at which these page faults will finish.
= 45264 , 7
So 0 to 7 line
Hence (C) is correct option.

YEAR 2008

Question. 60
For a magnetic disk with concentric circular track, the latency is not
linearly proportional to the seek distance due to
(A) non-uniform distribution of requests
(B) arm starting and stopping inertia
(C) higher capacity of tracks on the periphery of the platter
(D) use of unfair arm scheduling policies.

SOLUTION

Tracks on magnetic disks are concentric a seek is from me sector to other

may or mayn’t be in different tracks.
This seek distance is not proportional to latency since the tracks at
periphery has higher diameter so high in capacity to store data. Hence (C)
is correct option.

Question. 61
Which of the following is/are true of the auto increment addressing mode?
1. It is useful in creating self relocating code
2. If it is included in an Instruction Set Architecture, then an

222
 additional ALU is required for effective address calculation
3. The amount of increment depends on the size of the data item
accessed.
(A) 1 only (B) 2 only
(C) 3 only (D) 2 and 3 only

SOLUTION

In auto increment addressing mode the address where next data block to be stored is generated automatically
depending upon the size of single data item required to store. So statement 3 is correct.
Statement says that this mode is used for self relocating code, but this is false since self relocating code, takes
always some address in memory.
Statement 2 is also incorrect since no additional ALV is required. Hence (C) is correct option.

Question. 62
Which of the following must be true for the RFE (Return from Expectation) instruction on a general purpose
processor.
1. It must be a trap instruction
2. It must be a privileged instruction
3. An exception can not be allowed to occur during execution of an RFE instruction.
(A) 1 only (B) 2 only
(C) 1 and 2 only (D) 1, 2 and 3 only

SOLUTION

RFE (Return From Exception) is a privileged trap trap instruction which is executed when exception occurs, so
an exception is not allowed to execute.
Hence (D) is correct option.

Question. 63
For inclusion to hold between two cache level L1 and L2 in a multilevel cache hierarchy, which of the following
are necessary?
1. L1 must be a write-through cache
2. L2 must be write-through cache

223
3. The associativity of L2 must be greater that of L1
4. The L2 cache must be at least as large as the L1 cache
(A) 4 only (B) 1 and 2 only
(C) 1, 2 and 4 only (D) 1, 2, 3 and 4

SOLUTION

Level 1 (L1) & Level 2 (L2) cache are placed between CPV & they can be
both write through cache but this is not necessary. Associativity has no
dependence but L2 cache must be at least as large as L1 cache, since all
the words in L1 are also is L2.
Hence (A) is correct option.

Question. 64
Which of the following are NOT true in a pipe lined processor?
1. Bypassing can handle alll Raw hazards.
2. Register renaming can eliminate all register carried WAR hazards.
3. Control hazard penalties can be eliminated by dynamic branch
prediction.
(A) 1 and 2 only (B) 1 and 3 only
(C) 2 and 3 only (D) 1,2 and 3

SOLUTION

In a pipelined processor by passing can’t handle all the row hazards.

Registers carried WAR doesn’t have register naming as proper solution.
And control hazard penalties are eliminated by delayed branching not by
dynamic branch prediction.
So all are false.
Hence (D) is correct option.

Question. 65
The use of multiple register windows with overlap causes a reduction in
the number of memory accesses for
1. Function locals and parameters
2. Register saves and restores

224
3. Instruction fetches
(A) 1 only (B) 2 only
(C) 3 only (D) 1,2 and 3

SOLUTION

Multiple register windows with overlap causes a reduction in the number of memory accesses for instruction
fetching.
Hence (C) is correct option.

Question. 66
In an instruction execution pipeline, the earliest that the data TLB (Translation Look aside Buffer) can be
accessed is
(A) before effective address calculation has started
(B) during effective address calculation
(C) after effective address calculation has completed
(D) after data cache lookup has completed

SOLUTION

TLB is used during effective address calculation in an instruction execution pipeline.

Hence (B) is correct option.

Data for Q. 67, 68 & 69 are given below.

Consider a machine a 2-way set associative data cache of size 64 kbytes and block size 16 bytes. The cache is
managed using 32 bit virtual addressed and the page size is 4 kbytes. A program to be run on this machine
begins as follows:
Double APR[1024]]1024]
int i,j ;
/*Initalize array APR to 0.0*/ for (i = 0;i < 1024;i ++)
for (j = 0;k < 1024;j ++) APR[i][j] = 0.0;
The size of double 8 bytes. Array APR is in memory stating at the beginning of virtual page 0 # FF000 and
stored in row major order. The cache is initially empty and no pre-fetching is done. The only

225
data memory references made by the program are those to array APR.

Question. 67
The total size of the tags in the cache directory is
(A) 32 kbits (B) 34 kbits
(C) 64 kbits (D) 68 kbits

SOLUTION
Virtual (CPU) address has = 32 bits
2 way set associative cache size = 64 KB
Size of 1 set = 32 KB
Require 15 bits for indexing.
So Tag = 32 − 15 = 17
Size of block = 16 bytes
= 4 bits are required
Index = block + word
Block = 15 − 4 = 11

17 11 4
CPV address
17
Size of tags = There are 2 bytes of tags in every set of cache. So
total = 17 X 2 X 1024
= 34 KB.
Hence (B) is correct option.

Question. 68
Which of the following array elements has the same cache index as APR
[0][0]?
(A) APR[0][4] (B) APR[4][0]
(C) APR[0][5] (D) APR[5][0]

SOLUTION

Elements stored in row major order. Two elements should have same
cache index (15 bits) & their tags may be different (17 bits). SoAPR[%][
%] the MSB 17 bits will be changed.

226
APR[%][ %] APR[%][1]...............
APR[2][%]................................
APR[4][%]................................

So on.
This is virtual memory storage.
So 15 LSB of APR [%][ %] & APR [%][ %] are same so same index APR [%] & APR [4] 17 MSB are different
so tags differ.
Hence (B) is correct option.

Question. 69
The cache hit ratio for this initialization loop is
(A) 0% (B) 25%
(C) 50% (D) 75%

SOLUTION
No. of hits
Cache hit ratio =
Total accesses
1024
= = 1 = 0.5
1024 + 1024 2
or = 50%
Hence (C) is correct option.

Data for Q. 70 & 71 are given below.

Delayed branching can help in the handling of control hazardous

Question. 70
For all delayed conditional branch instruction, irrespective of weather the condition evato true or false, A
(A) the instruction following the conditional branch instruction in memory is executed
(B) the first instruction in the fall through path is executed
(C) the first instruction in the taken path is executed
(D) the branch takes longer to execute that any other instruction
227
SOLUTION

Delayed branching for conditional instructions, irrespective of whether the

condition evaluates to true or false, the first instruction in the fall through
path would be executed this prevent from hazardous control transfer.
Hence (B) is correct option.

Question. 71
The following code is to run on a pipe lined processor with one branch
delay slot
11: ADD R2 ! R7+R8
12: SUB R4 ! R5− R6
13: ADD R1 ! R2+ R3
14: STORE Memory [R4] ! R1
BRANCH to Label if R1==0
Which of the instruction 11,12,13 or 14 can legitimately occupy the delay
slot without any other program modification?
(A) 11 (B) 12
(C) 13 (D) 14

SOLUTION

In pipelining result of 1 instruction is used for the next in pipeline. Delay

slot will be occupied by the next instruction in the fall through path. The
branching instruction R1 == 0 goto Label X.
So in delay slot I2 will be there.

Hence (B) is correct option.

YEAR 2009

Question. 72
How many 32KX1 RAM chips are needed to provide a memory capacity
of 356-bytes ?
(A) 8 (B) 32
(C) 64 (D) 128

228
SOLUTION

Memory capacity of 1 RAM = 32 K bits Total Memory required = 256 K bytes

3
No. of RAM = 256 X K X 2 X bits 32 X K X bits

Chips required = 28 X25 23

= 26
= 64
Hence (C) is correct option.

Question. 73
A CPU generally handles are interrupt by executing an interrupt service routine
(A) As soon as an interrupt is raised
(B) By checking the interrupt register at the end of fetch cycle
(C) By checking the interrupt register after finishing the execution of the current instruction
(D) By checking the interrupt register at fixed time intervals

SOLUTION

An interrupt is a signal delivered to CPU, which tells to stop its normal service routine & execute interrupt
service routine.
This interrupt service routine is checked as soon as CPU receives the interrupt but since CPU working unit is an
instruction so CPU can switch to ISR only after execution of current instruction.
Hence (C) is correct option.

Question. 74
Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions 11, 12, 13, 14 in
stages S1, S2, S3, S4 is shown below:

S1 S2 S3 S4
I1 2 1 1 1
I2 2 3 2 2
I3 2 1 1 3

229
 I4 1 2 2 2

What is the number of cycles needed to execute the following loop?

for (i = 1to 2){I1; I2; I3; I4;}
(A) 16 (B) 23
(C) 28 (D) 30

SOLUTION

We can see a single iteration of given for loop according to the cycles
required.
Cycle S1 S2 S3 S4 Completion
1 I1
2 I1
3 I2 I1
4 I3 I2 I1
5 I3 I2 I1 I1
6 I4 I2
7 I3 I2
8 I4 I2
9 I4 I3 I2
10 I4 I2 I2
11 I4 I3
12 I3
13 I3 I3
14 I4
15 I4 I4

No. of cycle of 2 iteration = 2 X 15 =

30
Hence (D) is correct option.

Question. 75
Consider a 4 way set associative cache (initially empty) with total 16
cache blocks. The main memory consists of 256 blocks and the request for
memory blocks is in the following order :
230
0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155
Which one of the following memory block will NOT be in the cache if LRU replacement policy is used ?
(A) 3 (B) 8
(C) 129 (D) 216

SOLUTION

4 way set associative so 16 block will be divided in 4 sets of 4 blocks each.

We apply (Address mod 4) function to decide set.
0 48 0 mod4 = 0 )
4 32 255 mod4 = 3 )
Set 0
8 8 1 mod4 = 1 )
216 92 4 mod4 = 0 )
1 1 3 mod4 = 3 )
133 133 8 mod4 = 0 )
Set 1
129 129 133 mod4 = 1 )
73 73 159 mod4 = 3 )

216 mod4 = 0 )
129 mod4 = 1 )
Set 2
63 mod4 = 3 )
8 mod4 = 0 )
255 155 98 mod4 = 0 )
3 3 32 mod4 = 0 )
Set 3
159 159 73 mod4 = 1 )
63 63 92 mod4 = 0 )
155 mod4 = 3 )

All ) are misses S1 is the first stage & S2 is second. In the second stage 216 is not present in
Cache Hence (D) is correct option.

Common Data for Question 76 & 77

A hard disk has 63 sectors per track, 10 platters each with 2 recording
231
surfaces and 1000 cylinders. The address of a sector is given as a triple
c , h, s , where c is the cylinder number, h is the surface number and s is
the sector number. Thus, the 0th sector is addressed as 0,0,0 , the 1st
sector as 0,0,1 , and so on.

Question. 76
The address 400,16,29 , corresponds to sector number:
(A) 505035 (B) 505036
(C) 505037 (D) 505038

SOLUTION

Each cylinder has 10 platters or 20 recording surfaces or

63 X 20 sector = 1260 sectors.
Each recording surface has 63 sectors.
So < 400,16,297 =< c , h, s >
400 X 1260 + 16 X 63 + 29
50503
7 Hence (C) is correct option.

Question. 77
The address of 1039th sector is
(A) 0,15,31 (B) 0,16,30
(C) 0,16,31 (D) 0,17,31

SOLUTION

1 cylinder has 1260 sectors

So address for 1039th sector.
C=0
Each surface has 63 sectors.
Total surface here = 103963 = 16 surfaces

Remainder here 31 sectors

So < 0, 16, 31 >.
Hence (C) is correct option.
232
YEAR 2010

Question. 78
A main memory unit with a capacity of 4 megabytes is build using 1M X 1 − bit DRAM chips. Each DRAM
chip has 1K rows of cells with 1 K cells in each row. The time taken for a single refresh operation is 100
nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is
(A) 100 nanoseconds (B) 100)210nanoseconds
(C) 100)220nanoseconds (D) 3200)220nanoseconds

SOLUTION

Size of main memory = 4 MB 1 DRAM size = 1 Mb

4XMX8Xb
No. of chips required =
1XMXb

= 32
1 DRAM has 1 K rows
1 ROW has 1 K cells
Total cells in 1 DRAM = K2 = 220
In 32 DRAM = 32 X 220 Cells 1 cell refresh take 100 ns.
So total refresh time
= 32 X 100 X 220 ns
= 3200 X 220 ns.

Hence (D) is correct option.

Question. 79
A-5 stage pipelined processor has Instruction Fetch. (IF), Instruction Decode (ID), Operand Fetch (OF),
Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle
each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instruction. The PO stage takes 1
stake clock cycle for ADD and SUB instructions 3 clock cycles for MUL instruction, and 6 clock cycles for
DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles
needed to execute the following sequence of instructions ?

233
Instruction Meaning of instruction
I0 : MUL R 2, R 0, R1 R 2 ! R 0)R1
I1: DIV R 5, R 3, R4 R 5 ! R 3 /R4
I2 : ADD R 2, R 5, R2 R 2 ! R 5 + R2
I3 : SUB R 5, R 2, R6 R 5 ! R 2 − R6

(A) 13 (B) 15
(C) 17 (D) 19

SOLUTION

The order of operations IF " ID " OF " PO " WO

Figure

Here A = (R 3 /R 4) + R 2, R6

So we can see that all the instruction can be executed in 17 clock cycles
using piplining.

Hence (C) is correct option.

Question. 80
The program below uses six temporary variables a, b, c , d, e, f a
=1
b = 10
c = 20
d=a+b
e=c+d
f = c + e
b=c+e
e = b + f
d=5+e
Assuming that all operations take their operands from register, what is the
minimum number of registers needed to execute this program
without spilling ?
(A) 2 (B) 3
(C) 4 (D) 6
234
SOLUTION

Replacement
R1 R2 R3
a b c
d b c
d e c
f e c
f b c
f e c
f e d
So all the operations done using 3 registers only.
Hence (B) is correct option.

Common Data for Questions 81 & 82

A computer system has an L1 and L2 cache, an L2 cache, and a main memory unit connected as shown below.
The block size in L1 cache is 4 words. The block size is L2 cache is 16 words. The memory access times are 2
nanoseconds, 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unity respectively.

Question. 81
When there is a miss in L1 cache and a hit in L2 cache, a block is transferred form L2 cache to L1 cache. What is
the time taken for this transfer ?
(A) 2 nanoseconds (B) 20 nanoseconds
(C) 22 nanoseconds (D) 88 nanoseconds

SOLUTION

Each block is L2 Cache is 4 times L1 Cache. So far 1 block miss in L1 Cache the block from L2 to L1 will be
transferred, but L2 block has size 16 words & L1 data bus of 4 words, so 4L2 & 4L1 access are

235
required.
4 X 2 + 4 X 20
8 + 80
88 ns
Hence (D) is correct option.

Question. 82
When there is a miss in both L1 cache and L2 cache, first a block is transferred from
memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is
the total time taken for these transfers ?
(A) 222 nanoseconds (B) 888 nanoseconds
(C) 902 nanoseconds (D) 968 nanoseconds

SOLUTION

Miss in both L1 & L2. Cause main memory to transfer that block in both cache.
1 block of Main memory has 16 words but data bus of L2 has only 4 words. So 4 access
of Main memory & 4 access of L2 Cache required to update L2
4 X 20 + 4 X 200
80 + 800 = 880 ns

Now L2 updates L1, this takes 4 access to L1 & 4 access to L2 4 X 2 + 4 X 20

8 + 80 = 88 ns Total time = 880 +
88
= 968 ns
Hence (D) is correct option.

YEAR 2013

92. Consider an instruction pipeline with five stages without any branch prediction:
Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute
Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and
WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate
storage buffers after each stage and the delay of each buffer is 1 ns. A program
consisting of 12 instructions I1 ,I2 ,I3 ,......I12 is executed in this pipelined
processor. Instruction I4 is the only branch instruction and its branch target is I9 .
If the branch is taken during the execution of this program, the time (in ns)
needed to complete the program is
(A) 132 (B) 165 (C) 176 (D) 328

236
Ans: (C)

Exp: Total clock slots taken are 16. Each slot will take maximum of {5, 7, 10, 8 ,7} =10.

Hence total slots for all the instructions =

DIGITAL DESIGN

YEAR 2001

Question. 1

Given the following Karnaugh map, which one of the following represents the minimal sum-of-Products
of the map ?

(A) xy + y' z (B) wx' y' + xy + xz

(C) w' x + y' z + xy (D) xz + y

237
SOLUTION

There are 2 quads.

y' z + yx
So xy + y' z

Hence (A) is correct option.

Question. 2

Consider the following circuit with initial state Q 0 = Q1 = 0. The D flip-flops are positive edged
triggered and have set up times 20 nanosecond and hold times 0.

Consider the following timing diagrams of X and C ; the clock of C $ 40 nanosecond. Which one is the
correct plot of Y

238
SOLUTION

Consider the following circuit with initial state Q 0 = Q1 = 0. The D flip-

flops are positive edged triggered and have set up times 20 nanosecond
and hold times 0.

Consider the following timing diagrams of X and C ; the clock period of C

$ 40 nanosecond. Which one is the correct plot of Y ?
Figure

Question. 3
The 2’s complement representation of (− 539)10 is hexadecimal is
(A) ABE (B) DBC
(C) DE5 (D) 9E7

SOLUTION

Binary of 539 = 1000011011

239
 Binary :0010 0001 1011
2's comp :1101 1110 0101
Hexadecimal D E 5

(DES)16
Hence (C) is correct option.

Question. 4
Consider the circuit shown below. The output of a 2:1 Mux is given by the function (ac ' + bc).

Which of the following is true ?

(A) f = x1' + x2 (B) f = x1' x2 + x1x2'
(C) f = x1x2 + x1' x2' (D) f = x1 + x2

SOLUTION

Output of any 2:1 MUX = ac' + bc

Here output of MUX 1.
g = ax 1' + bx1
Output of MVX 2
(I) = gx 2' + x 1 x2
(J) = (ax 1' + bx 1) x 2' + x 1 x2
(K) = ax 1' x 2' + bx 1 x 2' + x 1 x2
Given a = 1, b = 0
(L) = x 1' x 2' + x 1 x2
Hence (C) is correct option.

Question. 5
Consider the circuit given below the initial state Q 0 = 1,Q 1 = Q2 = 0. The state of the circuit is given by
the value 4Q 2 + 2Q 1 + Q0

240
Which one of the following is the correct state sequence of the circuit
?

(A) 1, 3, 4, 6, 7, 5, 2 (B) 1, 2, 5, 3, 7, 6, 4

(C) 1, 2, 7, 3, 5, 6, 4 (D) 1, 6, 5, 7, 2, 3, 5

SOLUTION

Initially Q0 Q1 Q2 Value 4Q 2 + 2Q 1 + Q0
Clk 1 0 0 1
1 0 1 0 2

2 1 0 1 5
3 1 1 0 3
4 1 1 1 7
5 0 1 1 6
6 0 0 1 4

Hence (B) is correct option.

YEAR 2002

Question. 6

Minimum sum of product expression for f (w, x, y, z) shown in Karnaugh-

map below is

241
(A) xz + y' z (B) xz' + zx'
(C) x' y + zx' (D) None of the above

SOLUTION

There are 2 quads possible xz' + x' z

Hence (B) is correct option.

Question. 7

The decimal value of 0.25

(E) is equivalent to the binary value 0.1
(F) is equivalent to the binary value 0.01
(G) is equivalent to the binary value 0.00111.....
(H) cannot be represented precisely in binary.

242
SOLUTION

Given decimal no. 0.25

Binary = ?
.25 # 2 = .5
.5 # 2 = 1
(.01)2
Hence (B) is correct option.

Question. 8
The 2’s complement represent representation of the decimal value −15 is
(A) 1111 (B) 11111
(C) 111111 (D) 10001

SOLUTION
Given (− 15)10
Binary of 15 = (01111)2
2’s complement of 15 would represent (− 15).
01111
(10001)2
Hence (D) is correct option.

Question. 9
Sign extension is a step in
(I) floating point multiplication
(J) signed 16 bit integer addition
(K) arithmetic left shift
(L) converting a signed integer from one size to another.

SOLUTION

Sign extension is the operation in computer arithmetic of increasing no. of

bits of a binary no., while preserving sign and value done by appending
MSB’s. In the floating point multiplication to bring the no. in desired no.
of significant digits sign extension is done.
Hence (A) is correct option.

243
Question. 10

In 2’s complement addition, overflow

(H) Relational algebra is more powerful than relational calculus
(I) Relational algebra has the same power as relational calculus.
(J) Relational algebra has the same power as safe relational calculus.
(K) None of the above.

SOLUTION

In 2’s complement addition, overflow occurs when the carries from sign bit & previous bit doesn’t
match. So overflow can’t occur when a positive value is added to some negative value.
Hence (B) is correct option.

Question. 11
Consider the following logic circuit whose inputs are functions f1, f2, f3 and output is f

Given that
f1(x, y, z) = Σ(0,1,3,5)
f2(x, y, z) = Σ(6,7), and
f (x, y, z) = Σ(1,4,5)
f3 is
(A) Σ(1,4,5) (B) Σ(6,7)
(C) Σ(0,1,3,5) (D) None of the above

SOLUTION
f1 (x, y, z) = Σ(0,1,3,5)

244
 = x' y' + y' z + x'
z f2 (x, y, z) = Σ(6,7)

= xy
f (x, y, z) = Σ(1,4,5)

= xy' + y' z
f (x, y, z) = f1 f2 : f3
(I) f1 : f2 + f3
(J)xy (x' y' + y' z + x' z) + (xy' + y' z)
f3 = xy' z + xy' z' + xy' z + x' y'
z f3 = Σ(1,4,5)
Hence (A) is correct option.

Question. 12
Consider the following multiplexor where 10, 11, 12, 13 are
four data input lines selected by two address line combinations
A1A0 = 00,01,10,11 respectively and f is the output of the
multiplexor. EN is the Enable input.

245
The function f (x, y, z) implemented by the above circuit is
(A) xyz' (B) xy + z
(C) x + y (D) None of the above

SOLUTION

A1 A0 EN (MUX) work
0 0 1 do not
0 1 0 (MUX) Work
1 0 1 do not
1 1 0
So MUX is ENABLED only if A0 = 0
So output should have Z'.
Consider xyz' option (A)
A, A0 = 1 0 gives correct answer.
Hence (A) is correct option.

Question. 13
Let f (A, B) = A' + B. Simplified expression for function f (f (x + y, y), z) is
(A) x' + z (B) xyz
(C) xy' + z (D) None of the above

SOLUTION

f (x + y, y) = (x + y)' + y & x + y + y
f (f (x + y, y), z) = x + y + y + z & (x + y : y ) + z
[(x + y) : y ] + z

246
 [xy + yy ] + z
xy + z
Hence (C) is correct option.

Question. 14

What are the states of the Auxiliary Carry (AC) and Carry Flag (CY) after
executing the following 8085 program ?

MIV H, 5DH

MIV L, 6BH

MOV A, H

ADD L
(A) AC = 0 and CY = 0 (B) AC = 1 and CY = 1
(C) AC = 1 and CY = 0 (D) AC = 0 and CY = 1

SOLUTION

Program is to add 2 nos kept in H & L, result of addition is stored in A.

(5D) 16 + (6B)16 &

is the carry so CY = 0
(I) is auxillary carry AC = 1
Hence (C) is correct option.

Question. 15

The finite state machine described by the following state diagram

x
y and x stands for
with A as starting state, where an arc label is 1-bit
input and y stands for 2-bit output.
247
(A) Outputs the sum of the present and the previous bits of the input.
(B) Outputs 01 whenever the input sequence contains 11
(C) Outputs 00 whenever the input sequence contains 10
(D) None of the above.

SOLUTION

Previous input Present i/p Output

0(A) 0(A) 00

0(A) 1(B) 01
1(B) 0(A) 01
1(B) 1(C) 10

1(C) 1(C) 10

1(C) 0(A) 01

So output is always sum of the present and previous bits of input. Hence (A) is correct option.

YEAR 2003
Question. 16
Assuming all numbers are in 2’s complement representation, which of the following number is
divisible by 11111011?
(A) 11100111 (B) 11100100
(C) 11010111 (D) 11011011

SOLUTION

248
We can’t judge the no’s in 2’s complement first we need to convert them in decimal
Given no. 11111011"00000101=5

11100111 " 00011001 = 25

(A) 11100100 " 00011100 = 28

(B) 11010111 " 00101001 = 41
(C) 11011011 " 00100101 = 37 From all only option (A) is
divisible by 5.
Shortcut : To convert 2’s complement no. directly into original binary, we should complement all the
digits from MSB till the last one (1). Keep the last 1 from the LSB as it is. Observe in the example.

Question. 17
The following is a scheme for floating point number representation using 16 bits.

Let s, c and m be the number represented in binary in the sign, exponent, and mantissa fields
respectively. Then the flouting point number represented id
− 9 e−31
)(− 1) (1 + m # 2 )2
2
, if the exponent 111111 0 otherwise

What is the maximum difference between two successive real numbers

representable in this system?
(A) 2−40 (B) 2−9
(C) 222 (D) 231

SOLUTION

e has 6 bits so max value can be

26 − 1 = 63 when e = 111111 But given e =Y 111111
So max e = 62 = 111110
Two consecutive number will have same exponent but difference in mantissa by 1.
Difference would be
(− 1)2 (1 + (m + 1)2− 9)262 − 31 − (− 1)2 (1 + m # 2− 9)262 − 31 231 # 2−9
= 222
Hence (C) is correct option.

Question. 18
A 1-input, 2-output synchronous sequential circuit behaves as follows.
249
Let zk , nk denote the number of 0’s and 1’s respectively in initial k bits of the input (zk + nk = k). The
circuit outputs 00 until one of the following conditions holds.
1. nk − nk = 2. In this case, the output at the k -th and all subsequency clock ticks is 10.
2. nk − zk = 2. In this case, the output at the k -th and all subsequent clock ticks is 01.
What in the minimum number of states required in the state transition graph of the above circuit?
(A) 5 (B) 6
(C) 7 (D) 8

SOLUTION

The sequential circuit has 3 variables to decide the state in which input & 2 inputs are present. Output
for particular inputs decide states.
i/p op 1 op 2 State
0 0 0 Intial
0 0 1 nK−zK=2

0 1 0 zK−nK=2
0 1 1 Not applicable
1 0 0 Initial
1 0 1 nK−zK=2
1 1 0 zK−nK=2
1 1 1 is correct
Using 3 bits we require 23 − 1 = 7 states here.
Hence (C) is correct option.

Question. 19
The literal count of a boolean expression is the sum of the number of times each literal appears in the
expression. For example, the literal count of (xy + xz) is 4. What are the minimum possible literal
counts of the product-of-sum and sum-of-product representations respectively of the function given by
the following karnaugh map?

Here, denotes “don’t care”

250
(A) (11,9) (B) (9,13)
(C) (9,10) (D) (11,11)

SOLUTION

Considering product of sum & sum of product separately.

Sum of product Product of sum

= wy + w' y' + z' wx' + xyz' = (y' + z')(z' + y)(w' + z')
12 34 567 8910 (x + z + w)
Lateral count =9
Literal count =10

Hence (C) is correct option.

In SOP the K-map is solved for 1 & POS K-map solved for 0

Question. 20
Consider the following circuit composed of XOR gates and non-inverting buffers.

The non-inverting buffers have delays δ1 = 2ns and δ2 = 4ns as shown

in the figure. both XOR gates and al wires have zero delay. Assume that all gate inputs, outputs and
251
wires are stable at logic level 0. If the following waveform is applied at input. A, how many transition
(s) (change of logic levels) occur (s) at B during the interval from 0 to 10 ns?

(A) 1 (B) 2
(C) 3 (D) 4

SOLUTION
Due to delays S1 = 2 & S2 = 4 the transitions would occur at time 1, 2 & 4.
Time Input (A) Output (B)
0 1 0
I 1 1 0 Transition
II 2 1 0 Transition
III 4 0 1 Transition
So total 3 transitions
Hence (C) is correct option.

YEAR 2004

Question. 21
The Boolean function x' y' + xy + x' y is equivalent to

252
(A) x' + y' (B) x + y
(C) x + y' (D) x' + y

SOLUTION

x' y' + xy + xy'

x'(y + y') + xy (A + A') = 1
x' + xy (A + AB) = (A + A) : (A + B)
(x' + x) : (x' + y)
1 : (x' + y)
x' + y
Hence (D) is correct option.

Question. 22
In an SR latch made by cross-coupling two NAND gates, if both S and R
inputs are set to 0, then it will result in
(A) Q = 0,Q' = 1 (B) Q = 1,Q' = 0
(C) Q = 1,Q' = 1 (D) Indeterminate states

SOLUTION

SR latch both S and R when 0 leads to invalid state.

Transition table for SR flip flop.

S R Q(Next state)
ii 0 Invalid so Q=Q’=1 change
0 1 1
1 0 0
1 1 previous state
For S=R=0 Q=Q’=1

253
Hence (C) is correct option.

254
Question. 23
If 73x (in base-x number system) is equal to 54, (in base-y number system), the possible values of x and
y are
(A) 8, 16 (B) 10, 12
(C) 9, 13 (D) 8, 11

SOLUTION
(73)x = (54)y
7x + 3 = 5y + 4
(x', y) 7x + 3 5y + 4
8, 16 59 84
10, 12 73 64
9, 13 64 69
8, 11 59 59
Hence (D) is correct option.

Question. 24
What is the result of evaluating the following two expressions using three-digit floating point arithmetic
with rounding?
(113.+−111.)+7.51
113.+(−111.+7.51)
(A) 9.51 and 10.0 respectively (B) 10.0 and 9.51 respectively
(C) 9.51 and 9.51 respectively (D) 10.0 and 10.0 respectively

SOLUTION
Expression 1
(113.0 + (− 111.) + 7.51
(113.0 − 111.0) + 7.51
2.0 + 7.51
9.51
10 rounded off
Expression 2
113.0 + (− 111.0 + 7.51)
113.0 + (− 103.49)
113.0 − 103.00
10.0 rounded off Hence (D) is correct option

255
Question. 25
A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1
by 0001,...9 by 1001. A combinational circuit is to be diesigned which
takes these 4 bits as input and outputs 1 if the digit $ 5, and 0 otherwise. If
only AND, OR and NOT gates may be used, what is the minimum number
of gates required?
(A) 2 (B) 3
(C) 4 (D) 5

SOLUTION

CKT takes 4 bits as the input so K-Map will have 4 variable so 16 options
are available.

1 digit = 5
0 otherwise
Here for 0 to 4 we have 0 output, from 5 to 9 1 output & for 10 to 15 don’t
care. 1 octed & 2 pounds.
a + bd + bc
a + b (d + c)
Two OR gates
One AND gate
Total 3
Hence (B) is correct option.

Question. 26
Which are the essential prime implicates of the following Boolean
function?
f (a, b , c ) = a' c + ac ' + b ' c

256
(A) a' c and ac' (B) a' c and b ' c

257
(C) a' c only (D) ac' and bc'

SOLUTION

f (a, b , c) = a' c + ac ' + b ' c

Making min terms a' bc + a' b' c + abc ' + ab' c ' + a' b' c + ab' c Since b ' c gives no new
term.
So a' c & ac' are only essential prime implicants. Solution detailed method
Tabulation method
Since b ' c gives no new term.
So a' c & ac' are only essential prime implicants. Solution detailed method
Tabulation method
f (a, b , c ) = /m(1,3,5,6,4) Figure Figure
3 & 6 have only 1 cross they are in a' c & ac'

Question. 27
Consider the partial implementation fo a 2-bit counter using T flip flops following the sequence 0-2-3-
1-0, as shown below

To complete the circuit, the input X should be

(A) Q2' (B) Q2 + Q1
(C) (Q1 5 Q2)' (D) Q1 5 Q2

SOLUTION
Counter counts the no. of signal inversion change of states. Sequence input is 0 − 2 − 3 − 1 −
0

258
Binary 00 − 10 − 11 − 01 − 00 to generate signals if we XOR gate then it outputs 1 if both are
different.
So output sequence would be. 0 − 1 − 0 − 1 − 0 & the sequence would be counted.
So. X = Q 1 5 Q2
Hence (D) is correct option.

Question. 28
A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT,
NAND, NOR gates only. Assuming that all the inputs are available in both complemented and
uncompensated forms and the delay of each gate is one time unit, what is the overall propagation
delay of the adder? Assume that the carry network has been implemented using two-level AND-OR
logic.
(A) 4 time units (B) 6 time units
(C) 10 time units (D) 12 time units

SOLUTION

Carry of any higher order bit is dependent upon previous order bit addition generated carry.
C out = g 0 + p0 C in
P3 P2 P1 P0 g 3 g 2 g 1 g0
c 3 c 2 c 1 c0

c3 g 3 + P3 g 2 + P3 P2 g 1 + | P3 P2 P1 g 0 + P3 P2 P2 P0 C in This is 4 bit look

ahead adder equation total gate delay
= 1+1+2+2
= 6
Hence (B) is correct option.

Question. 29
Let A = 11111010 and B 0000 1010 be two 8-bit 2’s complement numbers. Their product in 2’s
complement is
(A) 1100 0100 (B) 1001 1100
(C) 1010 0101 (D) 1101 0101

SOLUTION

A and B are in 2’s complement form.

259
 A = 11111010
Binary = 00000110 = 6
2’s complement represent −ve number So A =− 6
B = 00001010
MSB is 0 so +ve no. decimal 10.
B = 10
A # B =− 6 # 10
=− 60 Binary of 60 = 00111100
2’s complement 11000100
Hence (A) is correct option.

YEAR 2005

Question. 30

Consider the following circuit.

Which one of the following is TRUE?

(A) f is independent of X (B) f is independent of Y

(C) f is independent of Z (D) None of X, Y, Z is redundant

260
SOLUTION

f =X:Y:Y:Z
= X:Y+Y:Z
= X:Y+Y:Z
For redundant check we need to draw K map to min terms.
XY (Z + Z ) + (X + X ) : YZ
XYZ + XY Z + XYZ + X YZ

XY + YZ + XZ
Hence (D) is correct option.

Question. 31
The range of integers that can be represented by an a bit 2’s complement
number system is
(A) − 2 n − 1 to (2n−1 − 1) (B) − (2 n − 1 − 1) to (2n−1 − 1)
(C) −2n − 1 to 2n−1 (D) − (2 n − 1 + 1) to (2n−1 − 1)

SOLUTION

n bit 2’s complement system must have corresponding bit binary system.
But to implement +ve & −ve nos. Both
we require MSB to be sign bit.
So maximum magnitude can be 2n−1 − 1 suppose we take n = 4.

261
Using 4 bits.
1 1 1 1,. . . . . .0 0 0 0, . . . . .01 1 1
−7 +7 This would be the range.

So − (2 n−1 − 1) to + (2 n−1 − 1) Hence (B) is correct option.

Question. 32
The hexadecimal representation of 6578 is
(A) 1AF (B) D78
(C) D71 (D) 32F

SOLUTION
(657)8 = (?)16 Making binary
S S=
0 0 010101111 (IAF)
16
A BBC
Hence (A) is correct option.

Question. 33
The switching expression corresponding to
f (A, B, C , D) = /(1,4,5,9,11,12) is
(A) BC' D' + A' C ' D + AB' D (B) ABC' + ACF + B' C ' D
(C) ACD ' + A' BC' + AC' D' (D) A' BD + ACD ' + BCD'

SOLUTION
f (A, B, C , D) = /(1,4,5,9,11,12) Drawing K map for min terms.

262
 BC D + A C D + AB D
So min terms are
BC D + A CD + AB D
Hence (A) is correct option.

Question. 34
Consider the following circuit involving a positive edge triggered D -FF.

Consider the following timing diagram. Let Ai represent the logic level on
the line A in the i − th clock period.

Let A represent the complement of A. The correct output sequence on Y

over the clock perids 1 through 5 is
(A) A0 A1 A1 ' A3 A4 (B) A0 A1 A2 ' A3 A4
(C) A1 A2 A2 ' A3 A4 (D) A1 A2 ' A3 A4 A5

SOLUTION

We need to calculate equation for D input.

(D) = (A i X')' − (X' Q')'
=Ai+X+X+Q
(E) =Ai'+X+Q
Drawing truth table for ckt
Clock X Q0 = 0 Q1 = 1 Ai Y

263
 0 1 0 1 A0' A0'

1 1 0 1 A1' A0'

2 0 0 1 A2' A1'

3 1 0 1 A3' A1'

4 1 0 1 A4 ' A3'

5 0 0 1 A5' A4 '

Hence (A) is correct option.

Question. 35
The following diagram represents a finite state machine which takes as input a binary number from the
least significant bit

Which one of the following is TRUE?

(J) It computes 1’s complement of the input number
(K) It computes 2’s complement of the input number
(L) It increments the input number
(M) It decrements the input number

SOLUTION

The transition table for the diagram

Present state Input Next state Output
Q0 0 Q0 0
Q0 1 Q1 1
Q1 0 Q1 1
Q1 1 Q1 0
264
So the FSM takes input from LSB side it doesn’t change state till the first 1 comes from LSB side, after
that it complement all the bits. This is logic for 2’s complement.
Hence (B) is correct option.

Question. 36
Consider the following circuit

The flip-flops are positive edge triggered DFFs. Each state is designated as a two bit string Q0, Q1. Let
the initial state be 00. The state transition sequence is
(A) 00 " 11 " 01 (B) 00 " 11
A
BBBBBBBC A BBBC
(C) 00 " 10 " 01 " 11 (D) 00 " 11 " 01 " 10
A BBBBBBBBBBC A BBBBBBBBBBC

SOLUTION
Truth table for DFF

CP D Qn+1 Action
0 X Qn No change
1 0 0 Reset
1 1 1 Set
D here AX + X' Q'
Truth table for ckt

and so on.
265
Hence (D) is correct option.

Data for Q. 37 & 38 are given below.

Solve the problems and choose the correct answers.
Consider the following floating point format

Mantissa is a pure fraction is sign-magnitude form.

Question. 37
The decimal number 0.239 # 213 has the following hexadecimal
representation without normalization and rounding off
(A) 0D 24 (B) 0D 4D
(C) 4D 0D (D) 4D 3D

SOLUTION

Sign bit 0
Exponent = 13
Excess 64 = 13 + 64 = 77 = 1001101
Binary of 239

266
We have 8 bits for Mantissa 0 0 1 1 1 1 0 1 So the floating point format.

0 1001101 00111101
0100 1101 0011 1101
4 D 3 D
Hence (D) is correct option.

Question. 38
The normalized representation for the above format is specified as
follows. The mantissa has an implicit 1 preceding the binary (radix) point.
Assume that only 0’s are padded in while shifting a field. The normalized
representation of the above number (0.239 # 213) is
(A) 0A 20 (B) 11 34
(C) 4D D0 (D) 4A E8

SOLUTION

Given no. .239 # 213

Normalized form of binary.
Binary " .239 = (00111101)2
Normalized = 1.11101 # 210
-
Proceeding implicit 1
So 8 bit mantissa
11101000S
padding

267
Excess 64 exponent
1 0 0 1 0 1 0 = 74
Sign bit = 0
Floating Point Format
0 1001010 11101000
0100 1010 1110 1000
4 A E 8
GAE8
Hence (D) is correct option.

268
YEAR 2006

Question. 39

You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes
only at the negative edge of the clock. Which one of the following circuits (using clocked D flip flops)
will delay the phase of f by 180c ?

SOLUTION

We require phase shift of 180 in f In ckt (B) the negation of signal f

& clock delays signal f by 180.

269
So phase shift occurs.
Hence (B) is correct option.

Question. 40
Consider the circuit below. Which one of the following options correctly represents f (x, y, z)?

− − − −
(A) xz + xy + yz (B) xz + xy + yz
−− − −
(C) xz + xy + yz (D) xz + xy + yz

SOLUTION
MVXI
Selects X when Z = 0
Y' when Z = 0
MVX II
Selects (XZ' + Y' Z) when y = 0
X when y = 0 so (XZ' + YZ) Y' + XY
Simplifying = xz' y' + zy' y' + xy
= xz' y' + xy (z + z') + zy'
= xz' y' + xyz + xyz' + zy'(x + x') = xz' y' + xyz + xyz' + xy' z + x' y'
z
= y' z + xy' z + xyz' + xyz + xyz'[a + a = a] = y' z + xz'(y + y') + xy (z + z')
= y' z + xz' + xy

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Hence (A) is correct option.

Question. 41
Given two three bit numbers a2 a1 a0 and b2 b1 b0 and c, the carry in, the function that represents the
carry generate function when these two numbers are added is
(E) a2 b2 + a1 a1 b1 + a2 a1 a0 b0 + a2 a0 b1 b0 + a1 b2 b1 + a1 a0 b2 b0 + a0 b2 b1 b0
(F) a2 b2 + a2 b1 b0 + a2 a1 b1 b0 + a1 a0 b21 b1 + a1 a0 b2 + a1 a0 b2 b0 + a2 a0 b1 b0
(G) a2 + b2 + (a2 5 b2)[a1 + b1 + (a1 5 b1)(a0 + b0)]
(H) a2 b2 + a2 a1 b1 + a2 a1 a0 b0 + a2 a0 b1 b0 + a1 b2 b1 a1 a0 b2 b0 + a0 b2 b1 b0

SOLUTION

a2 a1 a0 b2 b1 b0 C

0 0 0 0 0 0 0
0 0 1 0 0 1 1
0 1 0 0 1 0
0 1 0 0 1 1
1 0 1 1 0 0
1 0 0 1 0 1
1 1 1 1 1 0
1 1 0 1 1 1
Case I These are the possible value of a 2 a 1 a0 & b 2 b 1 b0 when a2 = 1
c=1
Case II b2 = 1 c = 1 so a 2 + b2
Case III If any 1 of a2 or b2 is 1 a 2 5 b2
then if a1 = 1 c = 1
b1 = 1 c = 1 so a 2 5 b 2 [ a 1 + b1]
Case IV If any of a2 or b2 is 1 & any of a2 or b1 is 1
then if a0 = 1 c = 1 or if b0 = 1 then c = 1 so overall.
a 2 + b 2 + [(a 2 5 b 2){a 1 + b 1 + (a 1 5 b 1)(a 0 + b0)}]
Hence (C) is correct option.

Question. 42
Consider a boolean function f (w, x, y, z). Suppose that exactly one of its inputs is allowed to change at a
time. If the function happens to be true for two input vectors i1 +< w1, x1, y1, x1 > and i2 +< w2, x2, y2, z2
>

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, we would like the function to remain true as the input changes from i1 to
i2 (i1 and i2 differ in exactly one bit position), without becoming false
momentarily. Let f (w, x, y, z) = /(5,, 711,12,13,15). Which of
the following cube covers of f will ensure that the required property
is satisfied?

(A) wxz, wxy, xyz, xyz, wyz (B) wxy, wxz, wyz

(C) wxyz , xz, wxyz (D) wzy, wyz, wxz, wwxz , xyz, xyz

SOLUTION
Given function f (w, x, y, z) = Σ(5,7,11,12,13,15) draw K-map of the above
function.

1 quad = xz = xz (y + y') = xzy + xy' z

2 pairs = wxy' + wyz xyz
+ xy' z + wxy' + wyz
Hence (A) is correct option.

Question. 43
We consider addition of two 2’s complement numbers bn − 1 bn −2 .....b0
and an − 1 an −2 ....a0. A binary adder for adding unsigned binary numbers
is used to add the two numbers. The sum is denoted by cn − 1 cn −2 ....c0 and
the carryout by cout . Which one of the following options correctly
identifies the overflow condition?

(B) an − 1 bn − cn − an − 1 bn − 1
(A) cout (an − 1 5 bn−1) 1 1 +cn−1

(C) cout 5 cn−1 (D) an − 1 5 bn − 1 5 cn−1

SOLUTION

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Binary adder generates C out only if

1 C in 1 0 1
0a 1 1 1
1b 0 1 1
1 C out 1 1 1
C out in this case is Cn−1 generated carry.
C in is Cn−2
So
b ' n − 1 a' n − 1 c n − 2 + b n − 1 a n − 1 c'n−2
f = Cout 5 Cn−1
Hence (C) is correct option.

Question. 44
Consider number represented in 4-bit gray code. Let h3 h2 h1 h0 be the gray code representation of a
number n and let g3 g2 g1 g0 be the gray code of (n + 1) (modulo 16) value of the number. Which one of
the following functions is correct?
E g0 (h1 h2 h1 h0) = /(1,2,3,6,10,13,14,15)
E g1 (h1 h2 h1 h0) = /(4,9,10,11,12,,13,14,15)
E g2 (h1 h2 h1 h0) = /(2,4, 5,6,7,12,,13,15)
E g3 (h1 h2 h1 h0) = /(0,1,6,7, 10,11,12,,13,)

SOLUTION
g3g2g1
Binary h h 3 h 2 h 1 h0 (n + 1) g0
mod 16
0000 0 0000 1 0001
0001 1 0001 2 0011
0010 2 0011 3 0010
0011 3 0010 4 0110
0100 4 0110 5 0111
0101 5 0111 6 0101
0110 6 0101 7 0100
0111 7 0100 8 1100
1000 8 1100 9 1101

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 1001 9 1101 10 1111
1010 10 1111 11 1110
1011 11 1110 12 1010
1100 12 1010 13 1011
1101 13 1011 14 1001
1110 14 1001 15 1000
1111 15 1000 0 0000
This gives the solution option (B)
g 1 (h 3, h 2, h 1, h0) = /(4,9,10,11,12,13,14,15)

YEAR 2007

Question. 45
What is the maximum number of different Boolean
functions involving
n Boolean variables? (B) 2n
(A) n2 (D) 2n2
(C) 22n

SOLUTION

Each boolean variable can have values 0 or 1, so for expression involving

n boolean variables will have terms 2n . These 2n terms need to be
arranged in different manner and nos., suppose 2n = M. So this
arrangement would take 2M ways or 22n ways.
Hence (C) is correct option.

Question. 46
How many 3-to-8 line decoders with an enable input are needed to
construct a 6-to-64 line decoder without using any other logic gates?
(A) 7 (B) 8
(C) 9 (D) 10

SOLUTION

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Total output lines required = 64 We need to use 3 to 8 decoders.
So decoders required 648 = 8 decoders for output.

But we need one more decoder i.e for combining result. 8 + 1 = 9 decoders.
Hence (C) is correct option.

Question. 47
Consider the following Boolean function of four variables f (w, x,, y, z) =
/(1,3,4,6,9,11,12,14)
The function is
(I) independent of one variable
(J) independent of two variables
(K) independent of three variables
(L) dependent on all the variables

SOLUTION
f (w, x, y, z) = /m(1,3,4,6,9,11,12,14)

2 qlead
1st qlead xz'
2nd qlead x' z
xz' + x' z xz' + x' z
So independent of 2 variables.
Hence (B) is correct option.

Question. 48
Let f (w, x, y, z) = /(0,4,5,7,8,9,13,15). Which of the following
expressions are NOT equivalent to f ?
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(A) x' y' z + w' xy' + wy' z + xz (B) w' y' x' + wx' y' + xz
(C) w' y' z' + wx' y' + xyz + xy' z (D) x' y' z + wx' y' + w' y

276
SOLUTION
f (w, x, y, z) = /m(0,4,5,7,8,9,13,15)
Drawing K-map.

xz + w' y' z' + wx' y'

Hence (B) is correct option.

Question. 49
Define the connective* for the boolean variable X and Y as: X * Y
= XY + X' Y'
Let Z = X * Z
Consider the following expression P, Q and R.
P: X = Y * ZQ: Y = X * Z
R: X * Y * Z = 1
Which of the following is TRUE?
(A) only P and Qare valid (B) Only Qand Rare valid
(C) Only P and Rare valid (D) AllP, Q,Rare valid

SOLUTION

Given Z = X ) Z & XZ + X' Z'

P: X = Y ) Z
(I) YZ + Y' Z'
(J)Y (XZ + X' Z') + Y' Z'
(K) XYZ + X' YZ' + Y' Z'
(L) XYZ + X' YZ' + XY' Z' + X' Y' Z' valid.
Q: Y = X ) Z
(M) XZ + X' Z'
(N) X (XZ + X' Z') + X' Z'
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 (G) XZ + X' Z'
(H) X (Y + Y') Z + X'(Y + Y') Z'
(I)XYZ + XY' Z + X' YZ' + X' Y' Z' valid R : X ) Y ) Z = 1
(XY + X' Y') ) Z & (XZ + X' Y') Z + (XY + X' Y') Z'
(E)XYZ + X' Y' Z + [(XY : X' Y') Z']
(F) XYZ + X' Y' Z + [(X + Y ) : (X + Y)] Z'
(G) XYZ + X' Y' Z + X' YZ' + XY' Z' =Y 1
So invalid
Hence (A) is correct option.

Question. 50
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean
function of nvariables. What is the minimum size of the multiplexer needed?
(A) 2n line to 1 line (B) 2n+1 line to 1 line
(C) 2n−1 line to 1 line (D) 2n−2 line to 1 line

SOLUTION
To select 2n lines we need a select function with n bits.
Here with n variables we have (n − 1) select bits thus 2n−1 data lines. So MUX has 2n−1 lines to 1.
Hence (C) is correct option.

Question. 51
In a look-ahead carry generator, the carry generate function Gi and the carry propagate function Pi for
inputs, Ai and Bi are given by
Pi = Ai 5 Bi and Gi = Ai Bi
The expressions for the sum bit S and carry bit Ci+1 of the look ahead carry adder are given by
Si + Pi 5 Ci and Ci + 1Gi + Pi Ci , Where C0 is the input carry.

Consider a two-level logic implementation of the look-ahead carry generator.. Assume that all Pi and Gi
are available for the carry generator circuit and that the AND and OR gates can have any number of
inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator
for a 4-bit adder with S3, S2, S1, S0 and C4 as its outputs are respectively

278
(A) 6,3 (B) 10,4
(C) 6,4 (D) 10,5

SOLUTION

The equation for 4 bit carry look ahead adder is

Cout g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 + p 3 p 2 p 1
p 0 Cin
Here
no. of AND gates = 10
OR gates = 4
Hence (B) is correct option.

Question. 52
The control signal functions of 4-bit binary counter are given below
(where X is “don’t care”)

Clear Clock Load Count Function

1 X X X Clear to 0
0 X 0 0 No change

0 - 1 X Load input
0 - 0 1 Count next
The counter is connected as follows

279
Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through
the following sequence
(A) 0,3,4 (B) 0,3,4,5
(C) 0,1,2,3,4 (D) 0,1,2,3,4,5

SOLUTION

From the truth table for the counter ckt we can see that when counter = 1. & load = 0, count next is the
function.
So it would count from 0 to 4 & then clear to 0 & again start if clock input is increasing.
Hence (C) is correct option.

YEAR 2008

Question. 53
In the IEEE floating point representation the hexadecimal value 0x00000000 corresponds to
(A) the normalized value 2−127 (B) the normalized value 2−126
(C) the normalized value +0 (D) the special value +0

SOLUTION

This 0X00000000 hexadecimal value can be converted into 32 bit binary.

0000 0000 0000 0000 0000 0000 0000 0000
0 # 2c
This is representation in IEEE floating point format. Case for special +0.
Hence (D) is correct option.

Question. 54
In the karnaugh map shown below, X denoted a don’t care term. What is the nominal form of the
function represented by the karnaugh map

280
 −− −− −− −− −−−
(A) b .d + a. d (B) a. b + b . d + a.b . d
−− −−− −− −− −−
(C) b .d + a. b. d (D) a. b + b . d + a. d

SOLUTION
Given K-map is

quad 1 " a b quad 2 " b d pair 1 " a c d

So a b + b d + a d (c + c) a b + b d + a d
Hence (D) is correct option.

Question. 55
Let a denote number system radix. The only value(s) of r that satisfy
the equation 121 + 11, is/are
(A) decimal 10
(C) decimal 10 and 11
(B) decimal 11
SOLUTION (D) any value> 2

(121)r = (11)r
If r = 10 it is true it can’t be 2 since bit value can’t be 2 then. It is not true for r
= 11
It is true for 3 to 10.
So it is true for r > 2
Hence (D) is correct option.

Question. 56
Give f1, f3 and f in canonical sum of products form (in decimal) for the circuit
281
 f1 = /m(4,5,6,7,8) f3 = /m(1,6,15)
f = /m(1,6,8,15)
Then f2 is
(A) /m(4,6) (B) /m(4,8)
(C) /m(6,8) (D) /m(4,6,8)

SOLUTION

Given f = Σm(1,6,8,15) f3 = Σm(1,6,15)

So output 1,6,8,15 here 1,6,15 can come form f3.
Since the final gate is OR gate so from f1 AND f2 no minterm except 1,6,8,15 should come.
f1 = Σm(4,5,6,7,8)
So f2 can be Σm(6,8)
Since 4,5, & 7 should no 7 come here.
Hence (C) is correct option.

Question. 57
− − −− −
If P , Q, R are Boolean variables, (P + Q) (P.Q + P. R) (P. R + Q)
simplifies to
− −
(A) P. Q (B) P. R

282
 − −
(C) P. Q + R (D) P. R + Q

SOLUTION

S (P + Q ) : (P Q + PR) : (P R + Q)
S (PPQ + PPR + PQ Q + PQR)(P R + Q)
S (P Q + PR + PQ + PQR)(P R + Q)
S (PQ + PR + PQR)(P R + Q)
S [ PQ (1 + R ) + PR](P R + Q)
S P (Q + R)(P R + Q)
S (P P R + PQ )(Q + R)
S PQ : (Q + R)
S PQ + PQR
S PQ (1 + R)
S PQ
Hence (A) is correct option.

YEAR 2009

Question. 58
(1217)8 is equivalent to
(A) (1217)16 (B) (028F)16
(C) (2297)10 (D) (0B17)16

SOLUTION

(vii) (1217)8
(viii) 001010001111SSS
(ix) (028F)1
6 Hence (B) is correct option.

Question. 59
What is the minimum number of gates required to implement the Boolean
function (AB + C) if we have to use only 2-input NOR gates
?
(A) 2 (B) 3
(C) 4 (D) 5
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SOLUTION

AB+C implementation through NOR gate (X + Y ) We require one AND gate & 1 OR
gate

AND gate & OR gate can be implemented by NOR gate.

2 A+C+B+C
2 A+C:B+C
2 (A + C ) : (B + C)
2 C + AB
So we require & NOR gates.
Hence (B) is correct option.

YEAR 2010

Question. 60
The minterm expansion of f (P, Q, R) = PQ + QR + PR is
(A) m 2 + m 4 + m 6 + m1 (B) m 0 + m 1 + m 3 + m5
(C) m 0 + m 1 + m 6 + m1 (D) m 2 + m 3 + m 4 + m5

SOLUTION

Given expression is
f (P, Q, R) = PQ + QR + PR
For min term expansion we add the remaining variables in the expression.
2. PQ (R + R ) + (P + P ) QR + P (Q + Q ) R
3. PQR + PQR + PQR + PQR + PQR + PQR
4. PQR + PQR + PQR + PQ R
5. m 7 + m 6 + m 2 + m4
6. 111 + 110 + 010 + 100
So = m 2 + m 4 + m 6 + m7

284
Hence (A) is correct option.

Question. 61
P is a 16-bit signed integer. The 2’s complement representation of P is (F
87B)16. The 2’s complement representation of 8)P is
(A) (C 3D8)16 (B) (187B)16
(C) (F878)16 (D) (987B)16

SOLUTIO
N
P’s 2’s complement.
= (F87B)16 Is
complement= F 87B − 1 =
(F87A)16
In base 16 complement is done by subtracting from 15 i.e F.
= = (0785)16
(0000 01111000 0101)2
1 # 2c + 1 # 2 2 + 1 # 2 7 + 1 # 2 8 + 1 # 2 9 + 1 # 210
= = 1925
8 # P = 8 # 1925 = 15400
Its binary 0011110000101000SSSS
For hexadecimal make pairs of 4 i.e. (3C28)16
2’s complement P = 1100 0011 1101 1000
C 3 D 8
2’s complement of P = (C 3D8)16
Hence (A) is correct option.

Question. 62
The Boolean expression for the output f of the multiplexer shown below is

(A) P 5 Q 5 R (B) P 5 Q 5 R

285
(C) P + Q + R (D) P + Q + R

SOLUTION
S1 & so are the select bits which are used to select any 1 of the 4 inputs.
Selection table
S 1 (P) S 0 (Q) Input
0 0 0R

0 1 1R

1 0 2R
1 1 3R
The expression has 3 variables
So K-map

This is K-map for P 5 Q 5 R

i.e PQ R + P Q R + PQR + P QR
Hence (B) is correct option.

Question. 64
In the sequential circuit shown below, if the initial value of the output Q 1 Q0 is 00, what
are the next four values of Q 1 Q0 ?

286
(A) 11, 10, 01, 00 (B) 10, 11, 01, 00
(C) 10, 00, 01, 11 (D) 11, 10, 00, 01

SOLUTION

There are 2 T-toggle flip flops in the ckt. Truth table for TFF.

CP T Qn+1

0 X Qn Qn previous state

1 0 Qn CP clock pulse

1 1 Qn Qn+1 next state

T toggle input
Since initially Q, Q0 = 00, so during 1st clock cycle both T & clock signals in
ckt are 1. After Q0 = 1 this fed to 2nd TFF which invert previous state Q1 = 1
so Q 1 Q0 = 11
11 when fed to next cycle clock = 1 so Q0 = 0 Q1 = 1 since no inversion Q,
Q0 = 10
In next cycle clock = 1 Q0 = 1 inverse, Q1 = 0 in the end Q 1 Q0 = 00 So
order 11, 10, 01, 00
Hence (A) is correct option. Which one of the following circuits is NOT
equivalent to a 2-input XNOR (exclusive NOR) gate?

(A) (B)
287
 (C) (D)

Answer: - (D)

Exp: - All options except option ‘D’ gives EX-NOR gates

67. The minimum number of D flip-flops needed to design a mod-258 counter is

(A) 9 (B) 8 (C) 512 (D) 258
Answer: - (A)
Exp: - 2n ≥ 258 ⇒

Common Data Questions: 50 & 51

Consider the following circuit involving three D-type flip-flops used in a certain type
of counter configuration.

P
D Q
Clock
Q

Q
D Q
Clock
Q

R
D Q
Clock
Q

288
68. If all the flip-flops were reset to 0 at power on, what is the total number of distinct
outputs (states) represented by PQR generated by the counter?
(A) 3 (B) 4 (C) 5 (D) 6
Answer: - (B)
Exp: -

CLOCK Inputs Outputs

D2
D1 D3 R P Q R

1 0 1 0 0 1 0

2 0 1 1 0 1 1

3 1 0 0 1 0 0

4 0 0 0 0 0 0

So Total number of distinct outputs is 4

69. If at some instance prior to the occurrence of the clock edge, P. Q and R have a
value 0, 1 and 0 respectively, what shall be the value of PQR after the clock
edge?
(A) 000 (B) 001 (C) 010 (D) 011
Answer: - (D)

Exp: -From the Table Shown in the explanation of question 50, if first state is 010 next
State is 011

289
 YEAR 2013

73. Which one of the following expressions does NOT represent exclusive NOR of x and
y?

(B) x ⊕ y' (C) x'⊕ y (D) x'⊕ y'

Ans: (D)

Exp:
⊕

⊕
⊕ ⊕y

74. In the following truth table, V = 1 if and only if the input is valid.
Inputs Outputs

D0 D1 D2 D3 X0 X1 V

0 0 0 0 X X 0
1 0 0 0 0 0 1

0 1 0 0 1 1

1 X 1 0 0 1

X X X 1 1 1 1
What function does the truth table represent?
(A) Priority encoder (B) Decoder
(C) Multiplexer (D) Demultiplexer
Ans: (A)
Exp: 4 to 2 priority encoder.

75. The smallest integer than can be represented byan 8-bit number in 2’s
complement form is
(A) -256 (B) -128 (C) -127 (D) 0
Ans: (B)
Exp: − 28 −1 −128. Range is -2(n-1) to +2(n-1)-1

76. A RAM chip has a capacity of 1024 words of 8 bi ts each 8 . The number of
290
 decoders with enable line needed to construct a

(A) 4 (B) 5 (C) 6 (D) 7

Ans: (B)
Exp.

16
Number of chips required = 2 [16 chips vertically with each

having 2 chips horizontally]

So to select one chip out of 16 vertical chips, we need 4 x 16 decoder.
Available decoder is – 2 x 4 decoder
To be constructed is 4 x 16 decoder

So we need 5, 2 x 4 decoder in total to construct 4 x 16 decoder.

291