EE444 Power Electronics SIMULATION

Prof. Jevti

Zero-Voltage-Transition Converter
Objectives 1. 2. 3. 4. 5. Study the operation of a zero-voltage-transition converter. Simulate a full-bridge phase-shift DC-DC converter with ideal switches. Compare analytical and simulation results. Investigate the effect of load current and leakage inductance on commutation. Investigate the operation at different phase-shift settings.

Instructions (Items shown boxed should be submitted with the report.) A. Front matter 1. Cover page to include: course number, course name, simulation title, your name, date simulation was due, date simulation is submitted. 2. Copy of these instructions. B. Description of circuit operation 1. A schematic of the full-bridge phase-shift DC-DC converter is shown in Figure 1. The output capacitances and the body diodes of the MOSFET switches are shown explicitly in order to facilitate analysis. The output of the rectifier is connected to an ideal current source which models a highly inductive load. 2. Please refer to the PowerPoint presentation entitled Zero-voltage-transition Full-bridge Phaseshift DC-DC Converter: Characteristic time intervals during one-half of the switching cycle for a detailed description of the circuit operation. 3. Study the PowerPoint presentation carefully, paying particular attention to the following for each of the time intervals described: a. Paths of current flow, b. Voltages across the switches, c. Voltage across the transformer, d. Voltage at the output of the rectifier, e. Current through the transformer leakage inductance, f. Currents through the rectifier diodes, g. Equations which govern charging and discharging of the capacitors. 4. Figure 2 shows the simulated waveforms for the converter described in the PowerPoint presentation. The switching period is 10s, phase-shift is 3s, and the blanking time is 0.6s. 5. Directly from the waveforms shown in Figure 3, read off the values of all time instants t1 ,..., t8 , as defined in the PowerPoint presentation, assuming t0 = 41 s . Your answers must be accurate to within 0.1s.

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EE444 Power Electronics

Prof. Jevti

Vx

Ls VA Vin VB

1:n:n

Io

ip

i
Dn

M2 C2 D2

M4 C4 D4

in

Fig. 1 Full-bridge phase-shift DC-DC converter. C. Setup and Verification 1. Build the circuit shown in Fig. 2 in Multisim, exactly as shown. a. Use DIODE_VIRTUAL component for all diodes. b. Use a VOLTAGE_CONTROLLED_SWITCH for all switches. c. Use a PULSE_VOLTAGE component for all switch controlling sources. d. Use TS_XFMR_TAP component for the transformer and set the Primary-toSecondary Turn Ratio to 0.2. 2. Set the PULSE_VOLTAGE source rise and fall times to 1ns. Adjust the Period, Delay Time, and Pulse Width parameters for each source in order to simulate the following conditions: switching period of 10s, phase-shift of 3s, and the blanking time of 0.6s. This requires some thinking! 3. Provide the values of the Period, Delay Time, and Pulse Width parameters you have selected for each source.
XSC1
G T A B C D A B C

XSC2
G T D

G1 C1 5nF D1

G3 C3 5nF D3

Vg1 J1

Vg3 J3

G1 G2 G3 G4 Dp

VAVBVx Vx I0 50 A

VA Vin 400 V VB

Ls 20uH

1T1 4

G2 C2 5nF

G4 C4 5nF

Dn

Vg2 J2

D2

Vg4 J4

D4

Fig. 2 Schematics of the converter as simulated in Multisim.

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EE444 Power Electronics

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Fig. 3 One full cycle of simulated switching waveforms for a full-bridge phase-shift DC-DC converter with 2 diode full-wave rectifier. Input voltage 400V, transformation ratio 1 : 0.2 : 0.2, output current 50A, switching frequency 100kHz, leakage inductance 20H, switch capacitance 5nF, phase shift 3s, blanking time 0.6s.

EE444 Power Electronics

Prof. Jevti

4. Under Simulate Interactive Simulation Settings set the maximum time step to TMAX=1ns. 5. To verify that you have the correct gating sequence, compare your waveforms G1, G2, G3, G4 to the waveforms Vg1, Vg2, Vg3, Vg4, shown in Figure 3. They should be identical. If not, return to step 2. 6. To verify the correct simulation of the entire circuit, compare the waveforms Va, Vb, and Vx to the waveforms shown in Figure 3. They should be identical. D. Comparison with Analytical Results 1. Consider the time interval 2 (see step B2 for reference,) which starts when M4 turns off. C4 is charging and C3 is discharging, such that the voltage VB increases from 0 to Vin. 2. Provide an analytical expression for the time interval t2 t1 required for a full discharge of the capacitor C3 in terms of C3, C4, n, Io, and Vin. 3. Calculate the numerical value of the expression and compare it to the t2 t1 interval as previously found in step B5 from the simulated waveforms shown in Figure 3. 4. Is the blanking time in our example longer or shorter than the time required for C3 to fully discharge? Explain how this leads to a drastic reduction of the switching losses for transistor M3 (and M1 in the next half-cycle.) 5. Consider next the time interval 5 (see step B2 for reference,) which starts when M1 turns off. 6. Calculate the period of oscillation To of a resonant LC circuit when L=Ls and C=C1+C2. 7. Compare the value of To/4 to the time t5 t4 it takes for C2 to fully discharge, as previously found in step B5 from the simulated waveforms shown in Figure 3. 8. Is the blanking time in our example longer or shorter than the time required for C2 to fully discharge? Explain how this leads to a drastic reduction of the switching losses for transistor M2 (and M4 in the next half-cycle.) 9. The resonant discharge of C2 is driven by the magnetic energy stored in Ls at the beginning of the discharge interval. For C2 to discharge fully and C1 to fully charge, the initial magnetic energy must be larger than the final electrical energy, that is: 2 2 1 1 2 Ls ( nI o ) > 2 (C1 + C2 )Vin . 10. Verify that the above inequality is satisfied for the converter shown in Figure 2. 11. All other parameters being the same as in Figure 2, but with Ls variable, what is the minimum value of the transformer leakage inductance required for the above inequality to hold? 12. All other parameters being the same as in Figure 2, but with I o variable, what is the minimum value of the load current required for the above inequality to hold? 13. To illustrate what happens when either the leakage inductance or the load current are too small, modify the circuit shown in Figure 2 by reducing the load current to Io=30A. 14. Provide a plot of the voltage waveform Va, focusing on the discharge interval. 15. What does the new waveform imply for the switching losses of transistor M2 and why?

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EE444 Power Electronics

Prof. Jevti

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.

E. Output DC Voltage Set to load current back to Io=50A, as originally shown in Figure 2. To find the output DC voltage Vo we will perform a transient analysis to find Vx(t) and then calculate the running average of Vx over one switching cycle. Under Simulate Analyses Transient Analysis set the Maximum time step to TMAX=1ns and End time to TSTOP=30s. Under the Output tab add V(vx) to the list of variables for analysis. In addition, enter the following expression: avgx(V(vx),10e-6). Show both Vx waveform and its running average on the same plot. Use cursors to find the value of the output DC voltage. What is the largest possible value of the phase-shift in micro-seconds? Keeping the period and the blanking time the same, change the phase-shift to its maximum value. See step C2. Provide the new values of the Period, Time Delay, and Pulse Width parameters for each source, required for simulating maximum output voltage. Show both Vx waveform and its running average on the same plot. Use cursors to find the value of the maximum output DC voltage. Explain why is the maximum achievable output DC voltage lower than 400Vx0.2=80V, as would expected from a transformer turn ratio of 0.2.

F. Bonus Questions 1. With reference to Vx waveform in Figure 3, explain why the overshoot and ringing occur only on the rising edge and not on the falling edge of the waveform. 2. What would you add to the rectifier in order to minimize the ringing? Demonstrate the effectiveness of your design via simulation. Show the schematics and the new waveform Vx.

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