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Cod Ass 4

This document is an assignment for a B.Tech. course in Computer Science and Engineering, focusing on Computer Organization and Design. It consists of three sections with questions covering topics such as memory techniques, memory hierarchy, cache memory, and various types of RAM and ROM. The assignment emphasizes clarity and correctness in the answers, with a total of 64 marks available.

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dakeshav000
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5 views1 page

Cod Ass 4

This document is an assignment for a B.Tech. course in Computer Science and Engineering, focusing on Computer Organization and Design. It consists of three sections with questions covering topics such as memory techniques, memory hierarchy, cache memory, and various types of RAM and ROM. The assignment emphasizes clarity and correctness in the answers, with a total of 64 marks available.

Uploaded by

dakeshav000
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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B.Tech.

(Computer Science and Engineering)


Semester-IV
Subject: Computer Organization and Design (BCO 009A)
Marks: 64
Instructions:
 Answer all questions.
 All questions carry equal marks.
 Write answers neatly and clearly.
 Marks will be awarded for both correctness and clarity of explanation.

Assignment #4

Section A Answer the following Questions: (5*2=10 marks)

1. [CO4] How we can overcome the speed mismatch between CPU and Main Memory?
2. [CO4] What do you mean by write-through and write-back techniques?
3. [CO4] What are the different types of ROM?
4. [CO4] Differentiate between Static RAM and Dynamic RAM.
5. [CO4] Differentiate between Static EEROM and EPROM.

Section B Answer the following Questions: (7x3=21Marks)


1. [CO4] Explain the Memory Techniques in detail.
2. [CO4] Explain the Memory Hierarchy in detail.
3. [CO4]Consider a direct mapped cache of size 16 KB with block size 256 bytes. The size of main memory is
128 KB. Find-
1. Number of bits in tag 2. Tag directory size

Section C Answer the following Questions: (11x3=33Marks)

1. [CO4] A cache memory that has a hit rate of 0.8 has an access latency 10ns and miss penalty
100ns.An optimization is done on the cache to reduce the miss rate. However, the optimization results
in an increase of cache access latency to whereas the miss penalty is not affected. The minimum hit
rate (rounded off to two decimal places) needed after the optimization such that it should not increase
the average memory access time is _______________.
2. [CO4] A digital computer has a memory unit of 64K *16 and a cache memory of 1K words. The
cache uses direct mapping with a block size of four words.
a.How many bits are there in the tag,index,block and word fields of the address formats?
b.How many bits are there in each word of cache, and how are they dividend into function?
Include a valid bit.
c.How many blocks can the cache accommodate?
3. [CO4] A two –way set associative cache memory uses block of 4 words. The cache can accommodate a total
of 2048 words from main memory. The main memory size is 128k* 32.

(i)Formulate all pertinent information required to construct the cache memory.

(ii)What is the size of cache memory and number of address bits required to define a block of main memory?

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