International Journal of Engineering and Advanced Technology (IJEAT)
ISSN: 2249-8958 (Online), Volume-2 Issue-2, December 2012
Design of a 1.5-V, 4-bit Flash ADC using 90nm
Technology
Arunkumar. P. Chavan, Rekha. G, P. Narashimaraja
Abstract - In this paper, a 4bit analog to digital converter is The 2N–1 comparator outputs therefore behave in a way
designed for low power CMOS. It requires 2N-1 comparators, an analogous to a mercury thermometer, and the output code at
encoder to convert thermometer code to binary code. The design this point is sometimes called a thermometer code. Since
is simulated in cadence environment using spectre simulator 2N–1 data outputs are not really practical, they are processed
under 90nm technology. The pre simulation results for the design
shows a low power dissipation of 1.984mW for the designed
by a decoder to generate an N-bit binary output.
ADC. The circuit operates with an input frequency of 25MHz
and 1.5V supply with a conversion time of 6.182ns.
Keywords – CMOS comparator, Thermometer encoder, Flash
ADC, Low-power.
I. INTRODUCTION
An analog-to-digital converter (ADC) is a device that
converts the input continuous physical quantity to a digital
number that represents the quantity's amplitude. The result
is a sequence of digital values that have converted a
continuous-time and continuous-amplitude analog signal to
a discrete-time and discrete-amplitude digital signal. A
direct-conversion ADC or flash ADC has a bank of
comparators sampling the input signal in parallel, each
firing for their decoded voltage range. The comparator bank
feeds an encoder logic circuit that generates a code for each
voltage range.
II. FLASH CONVERTER
Flash ADCs (sometimes called parallel ADCs) are the
fastest type of ADC and use large numbers of comparators.
The input signal is applied to all the comparators at once, so
the thermometer output is delayed by only one comparator
delay from the input, and the encoder N-bit output by only a
few gate delays on top of that, so the process is very fast. An
N-bit flash ADC consists of 2N resistors and 2N–1 Figure 1: N-Bit Flash ADC
comparators arranged as in Figure Fig 1. Each comparator The architecture uses large numbers of resistors and
has a reference voltage which is 1 LSB higher than that of comparators and is limited to low resolutions, and if it is to
the one below it in the chain. For a given input voltage, all be fast, each comparator must run at relatively high power
the comparators below a certain point will have their input levels. Hence, the problems of flash ADCs include limited
voltage larger than their reference voltage and a “1” logic resolution, high power dissipation because of the large
output, and all the comparators above that point will have a number of high speed comparators and relatively large (and
reference voltage larger than the input voltage and a “0” therefore expensive) chip sizes. In addition, the resistance of
logic output. the reference resistor chain must be kept low to supply
adequate bias current to the fast comparators.
A. Comparator
The low power comparator circuit used in the design of
Manuscript published on 30 December 2012.
* Correspondence Author (s)
Flash ADC is shown in fig 2 which is proposed in [1]. This
Arunkumar P Chavan Department of Electronics and Communication, circuit uses a preamplifier and a latch stage. In the
R V College of Engineering, Bangalore 560059, India. preamplifier stage to achieve an acceptable gain the input
Rekha G, Department of Electronics and Communication, R V College differential pair uses NMOS transistors and the load uses
of Engineering, Bangalore 560059, India.
P Narashimaraja, Department of Electronics and Communication, R V
PMOS transistors. The latch stage consists of two inverters
College of Engineering, Bangalore 560059, India. which are connected in a back to back fashion forming a
differential comparator and an NMOS transistor is
© The Authors. Published by Blue Eyes Intelligence Engineering and connected between the two differential nodes of the latch.
Sciences Publication (BEIESP). This is an open access article under the
CC-BY-NC-ND license http://creativecommons.org/licenses/by-nc-nd/4.0/
Published By:
Blue Eyes Intelligence Engineering
Retrieval Number B0932112212/12©BEIESP and Sciences Publication (BEIESP)
Journal Website: www.ijeat.org 274 © Copyright: All rights reserved.
Design of a 1.5-V, 4-bit Flash ADC using 90nm Technology
The design was implemented in cadence using 180nm
technology [1]. In our proposed work simulation results are
shown using 90nm technology.
III. PRE SIMULATION RESULTS
Fig 2: Preamplifier-Latch comparator
A. Comparator Output
The preamplifier stage improves the sensitivity of the
comparator and isolates the comparator input from The schematic of comparator using 90nm technology is
switching noise of the positive feedback stage [3]. The latch shown in fig 4. The input signal applied to the non-inverting
stage gives the information about which of the input signals terminal is a sine wave and a dc reference voltage is applied
is larger and amplifies the difference between the signals to the inverting terminal of the comparator. The resulting
[4]. waveform at the output of the comparator is as shown in fig
5.
B. Thermometer to Binary Code Converter
The logic encoder used for 4bit ADC is as shown in fig 3.
This is a multiplexer based encoder which converts
thermometer codes to binary codes. Table 1 show the truth
table for the 4bit encoder. The multiplexers used are
designed using transmission gates for better accuracy.
Fig 4: Schematic of comparator
Fig 3: Logic Encoder for 4bit ADC
Table 1: Truth table for 4bit encoder
Fig 5: Comparator output waveform
B. Flash ADC Output
The above obtained 2N-1 comparator outputs are encoded
into 4bit output using an encoder and the resulting
waveform of the ADC is as shown in fig 7. The schematic
view of ADC ia as shown in fig6.
Published By:
Blue Eyes Intelligence Engineering
Retrieval Number B0932112212/12©BEIESP and Sciences Publication (BEIESP)
Journal Website: www.ijeat.org 275 © Copyright: All rights reserved.
International Journal of Engineering and Advanced Technology (IJEAT)
ISSN: 2249-8958 (Online), Volume-2 Issue-2, December 2012
3) R. Wang, K. Li, J. Zhang and B. Nie, “A High Speed High Resolution
Latch Comparator For-Pipeline ADC,” IEEE International Workshop
on Anti-counterfeiting, Se- curity, Identification, Xiamen, 16-18 April
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27, 1992.
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Ciechocinek, 21-23 June 2007, pp. 305-308.
Fig 6: Schematic view of 4bit ADC
Arunkumar. P Chavan born on July, 4th, 1987 in
Karnataka, India, obtained his B.E degree in Electronics
and Communication Engineering from Visvesvaraya
Technological University (VTU), Belgaum, India.
Currently pursuing M.Tech in VLSI Design and
Embedded Systems. His areas of interest are VLSI
design, Analog circuit design and digital electronics.
Rekha. G born on March, 15th, 1990 in Karnataka,
India, obtained her B.E degree in Electronics and
Communication Engineering from Visvesvaraya
Technological University (VTU), Belgaum, India.
Currently pursuing M.Tech in VLSI Design and
Embedded Systems. Her areas of interest are VLSI
design, Image Processing, and Digital electronics.
Fig 7: Output waveform of 4bit ADC Narashimaraja. P born on January, 31st, 1982 in
Table 2 shows the parameter values obtained for the 4bit Tamilnadu, India, obtained his BE degree in
Electronics from Madurai Kamaraj university, in 2004
ADC circuit under 90nm technology with supply voltage and ME degree in VLSI Design from Bharath institute
equal to 1.5V. of higher education & research, in 2006. Currently, Is
an Assistant professor at RV College of Engineering.
Table 2: Parameter Values for 90nm His research interest are in the field of VLSI
architectures, Memory design and Analog design.
IV. CONCLUSIONS
The problem of flash ADCs lies with limited resolution,
high power dissipation because of the large number of high
speed comparator. In this regard we have made an attempt
to design a low-power 4bit ADC. The design and Pre
simulation are carried out in cadence environment using
spectre simulator under 90nm technology. The ADC design
can be used for low power and high speed applications.
REFERENCES
1) Shubhara Yewale, Radheshyam Gamad “Design of Low Power and
High SpeedMOS Comparator for A/D Converter application”,
Wireless Engineering and Technology, 2012, 3, 90-95.
2) B. Razavi, “Deign of Analog CMOS Integrated Circuits,” Tata
McGraw-Hill, Delhi, 2002.
Published By:
Blue Eyes Intelligence Engineering
Retrieval Number B0932112212/12©BEIESP and Sciences Publication (BEIESP)
Journal Website: www.ijeat.org 276 © Copyright: All rights reserved.
