Cheat Sheet VHDL Complet : Dataflow, Behavioral (PROCESS & CASE) & Structural

1. Portes Logiques
1.1 AND Gate
library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
port(A, B: in std_logic; Y: out std_logic);
end and_gate;

-- Dataflow
architecture dataflow of and_gate is
begin
Y <= A and B;
end dataflow;

-- Behavioral (PROCESS)
architecture behavioral_proc of and_gate is
begin
process(A, B)
begin
Y <= A and B;
end process;
end behavioral_proc;

-- Behavioral (CASE)*
architecture behavioral_case of
and_gate is
begin
process(A, B)
begin
case (A & B) is
when "11" => Y <= '1';
when others => Y <= '0';
end case;
end process;
end behavioral_case;

-- Structural
architecture structural of and_gate is
component nand2 port(A, B: in std_logic; Y: out std_logic); end
component;
component inv port(A: in std_logic; Y: out std_logic); end
component;
signal tmp: std_logic;
begin
U1: nand2 port map(A=>A, B=>B, Y=>tmp);
U2: inv port map(A=>tmp, Y=>Y);
end structural;

1.2 NOT Gate

entity not_gate is
port(A: in std_logic; Y: out std_logic);
end not_gate;

-- Dataflow
architecture dataflow of not_gate is
begin
Y <= not A;
end dataflow;

-- Behavioral (PROCESS)
architecture behavioral_proc of not_gate is
begin
process(A)
begin
Y <= not A;
end process;
end behavioral_proc;

-- Structural
architecture structural of not_gate is
component inv port(A: in std_logic; Y: out std_logic); end
component;
begin
U1: inv port map(A=>A, Y=>Y);
end structural;
1.3 OR Gate
entity or_gate is
port(A, B: in std_logic; Y: out std_logic);
end or_gate;

-- Dataflow
architecture dataflow of or_gate is
begin
Y <= A or B;
end dataflow;

-- Behavioral (PROCESS)
architecture behavioral_proc of or_gate is
begin
process(A, B)
begin
Y <= A or B;
end process;
end behavioral_proc;

-- Structural
architecture structural of or_gate is
component or2
port(A, B: in std_logic; Y: out std_logic);
end component;
begin
U1: or2 port map(A=>A, B=>B, Y=>Y);
end structural;
1.4 NAND Gate
entity nand_gate is
port(A, B: in std_logic; Y: out std_logic);
end nand_gate;

-- Dataflow
architecture dataflow of nand_gate is
begin
Y <= not (A and B);
end dataflow;

-- Behavioral (PROCESS)
architecture behavioral_proc of nand_gate is
begin
process(A, B)
begin
Y <= not (A and B);
end process;
end behavioral_proc;

-- Structural
architecture structural of nand_gate is
component and2 port(A, B: in std_logic; Y: out std_logic); end
component;
component inv
port(A: in std_logic; Y: out std_logic);
end component;
signal tmp: std_logic;
begin
U1: and2 port map(A=>A, B=>B, Y=>tmp);
U2: inv port map(A=>tmp, Y=>Y);
end structural;
1.5 XOR Gate
entity xor_gate is
port(A, B: in std_logic; Y: out std_logic);
end xor_gate;

-- Dataflow
architecture dataflow of xor_gate is
begin
Y <= A xor B;
end dataflow;

-- Behavioral (PROCESS)
architecture behavioral_proc of xor_gate is
begin
process(A, B)
begin
Y <= A xor B;
end process;
end behavioral_proc;

-- Structural
architecture structural of xor_gate is
component and2
port(A, B: in std_logic; Y: out std_logic);
end component;

component or2
port(A, B: in std_logic;
Y: out std_logic);
end component;
component inv
port(A: in std_logic;
Y: out std_logic);
end component;
signal t1, t2: std_logic;
begin
U1: and2 port map(A=>A, B=>not B, Y=>t1);
U2: and2 port map(A=>not A, B=>B, Y=>t2);
U3: or2 port map(A=>t1, B=>t2, Y=>Y);
end structural;
1.6 XNOR Gate
entity xnor_gate is
port(A, B: in std_logic; Y: out std_logic);
end xnor_gate;

-- Dataflow
architecture dataflow of xnor_gate is
begin
Y <= A xnor B;
end dataflow;

-- Behavioral (PROCESS)
architecture behavioral_proc of xnor_gate is
begin
process(A, B)
begin
Y <= A xnor B;
end process;
end behavioral_proc;

-- Structural
architecture structural of xnor_gate is
component xor2
port(A, B: in std_logic;
Y: out std_logic);
end component;
component inv
port(A: in std_logic;
Y: out std_logic);
end component;
signal tmp: std_logic;
begin
U1: xor2 port map(A=>A, B=>B, Y=>tmp);
U2: inv port map(A=>tmp, Y=>Y);
end structural;
2. Multiplexeurs & Démultiplexeurs
2.1 MUX 2→1
entity mux2to1 is
port(A, B: in std_logic;
SEL: in std_logic;
Y: out std_logic);
end mux2to1;

-- Dataflow
architecture dataflow of mux2to1 is
begin
Y <= (not SEL and A) or (SEL and B);
end dataflow;

-- Behavioral (PROCESS)
architecture behavioral_proc of mux2to1 is
begin
process(A, B, SEL)
begin
if SEL='0' then
Y <= A;
else
Y <= B;
end if;
end process;
end behavioral_proc;

-- Behavioral (CASE)
architecture behavioral_case of
mux2to1 is
begin
process(A, B, SEL)
begin
case SEL is
when '0' => Y <= A;
when '1' => Y <= B;
when others => Y <= '0';
end case;
end process;
end behavioral_case;

-- Structural
architecture structural of mux2to1 is
component and2, or2, inv
port(A,B:in std_logic;
Y:out std_logic);
end component;
signal nsel, t1, t2: std_logic;
begin
U0: inv port map(A=>SEL, Y=>nsel);
U1: and2 port map(A=>nsel,B=>A, Y=>t1);
U2: and2 port map(A=>SEL, B=>B, Y=>t2);
U3: or2 port map(A=>t1, B=>t2, Y=>Y);
end structural;
2.2 MUX 4→1
entity mux4to1 is
port(A,B,C,D: in std_logic;
SEL: in std_logic_vector(1 downto 0);
Y: out std_logic);
end mux4to1;

-- Dataflow
architecture dataflow of mux4to1 is
begin
Y <= (not SEL(1) and not SEL(0) and A) or
(not SEL(1) and SEL(0) and B) or
(SEL(1) and not SEL(0) and C) or
(SEL(1) and SEL(0) and D);
end dataflow;

-- Behavioral (PROCESS)
architecture behavioral_proc of mux4to1 is
begin
process(A,B,C,D,SEL)
begin
if SEL="00" then
Y<=A;
elsif SEL="01" then
Y<=B;
elsif SEL="10" then
Y<=C;
else
Y<=D;
end if;
end process;
end behavioral_proc;

-- Behavioral (CASE)
architecture behavioral_case of mux4to1 is
begin
process(A,B,C,D,SEL)
begin
case SEL is
when "00" => Y<=A;
when "01" => Y<=B;
when "10" => Y<=C;
when "11" => Y<=D;
when others => Y<= '0';
end case;
end process;
end behavioral_case;
-- Structural
architecture structural of mux4to1 is
component mux2to1 port(A,B:in std_logic;
SEL:in std_logic;
Y:out std_logic);
end component;
signal y0,y1: std_logic;
begin
U0: mux2to1 port map(A=>A,B=>B,SEL=>SEL(0),Y=>y0);
U1: mux2to1 port map(A=>C,B=>D,SEL=>SEL(0),Y=>y1);
U2: mux2to1 port map(A=>y0,B=>y1,SEL=>SEL(1),Y=>Y);
end structural ;
2.3 DEMUX 1→4
entity demux_1to4 is
port(D: in std_logic;
SEL: in std_logic_vector(1 downto 0);
Y0,Y1,Y2,Y3: out std_logic);
end demux_1to4;

-- Dataflow
architecture dataflow of demux_1to4 is
begin
Y0<=D when SEL="00" else '0';
Y1<=D when SEL="01" else '0';
Y2<=D when SEL="10" else '0';
Y3<=D when SEL="11" else '0';
end dataflow;

-- Behavioral (PROCESS)
architecture behavioral_proc of
demux_1to4 is
begin
process(D,SEL)
begin
Y0<= '0';Y1<= '0';Y2<= '0';Y3<= '0';
if SEL="00" then
Y0<=D;
elsif SEL="01" then
Y1<=D;
elsif SEL="10" then
Y2<=D;
else
Y3<=D;
end if;
end process;
end behavioral_proc;

-- Behavioral (CASE)
architecture behavioral_case of demux_1to4 is
begin
process(D,SEL)
begin
Y0<= '0';Y1<= '0';Y2<= '0';Y3<= '0';
case SEL is
when "00" => Y0<=D;
when "01" => Y1<=D;
when "10" => Y2<=D;
when "11" => Y3<=D;
when others => null;
end case;
end process;
end behavioral_case;
-- Structural
architecture structural of demux_1to4 is
component and2 port(A,B:in std_logic;
Y:out std_logic);
end component;
component inv port(A:in std_logic;
Y:out std_logic);
end component;
signal n0,n1: std_logic;
begin
inv0: inv port map(A=>SEL(0), Y=>n0);
inv1: inv port map(A=>SEL(1), Y=>n1);
U0: and2 port map(A=>D, B=>n1 and n0, Y=>Y0);
U1: and2 port map(A=>D, B=>SEL(1) and n0, Y=>Y1);
U2: and2 port map(A=>D, B=>n1 and SEL(0), Y=>Y2);
U3: and2 port map(A=>D, B=>SEL(1) and SEL(0), Y=>Y3);
end structural;
3. Additionneurs & Soustracteurs
3.1 Demi-Adder
entity half_adder is
port(A,B: in std_logic; SUM,COUT: out std_logic);
end half_adder;

-- Dataflow
architecture dataflow of half_adder is
begin
SUM<=A xor B;
COUT<=A and B;
end dataflow;

-- Behavioral (PROCESS)
architecture behavioral_proc of half_adder is
begin
process(A,B)
begin
SUM<=A xor B;
COUT<=A and B;
end process;
end behavioral_proc;

-- Structural
architecture structural of half_adder is
component xor2 port(A,B:in std_logic;
Y:out std_logic);
end component;
component and2 port(A,B:in std_logic;
Y:out std_logic);
end component;
begin
U1: xor2 port map(A=>A,B=>B,Y=>SUM);
U2: and2 port map(A=>A,B=>B,Y=>COUT);
end structural;
3.2 Additionneur Complet
entity full_adder is
port(A,B,CI:in std_logic; SUM,CO:out std_logic);
end full_adder;

-- Dataflow
architecture dataflow of full_adder is
begin
SUM<=A xor B xor CI;
CO<= (A and B) or (B and CI) or (A and CI);
end dataflow;

-- Behavioral (PROCESS)
architecture behavioral_proc of full_adder is
begin
process(A,B,CI)
begin
SUM<=A xor B xor CI;
CO<= (A and B) or (B and CI) or (A and CI);
end process;
end behavioral_proc;

-- Structural
architecture structural of full_adder is
component half_adder
port(A,B:in std_logic;
SUM,COUT:out std_logic);
end component;
component or2
port(A,B:in std_logic;
Y:out std_logic);
end component;
signal s1,c1,c2: std_logic;
begin
HA1: half_adder port map(A=>A,B=>B,SUM=>s1,COUT=>c1);
HA2: half_adder port map(A=>s1,B=>CI,SUM=>SUM,COUT=>c2);
U3: or2 port map(A=>c1,B=>c2,Y=>CO);
end structural;
3.3 Demi-Soustracteur
entity half_subtractor is
port(A,B:in std_logic;
DIF,BOUT:out std_logic);
end half_subtractor;

-- Dataflow
architecture dataflow of half_subtractor is
begin
DIF<=A xor B;
BOUT<= (not A) and B;
end dataflow;

-- Behavioral (PROCESS)
architecture behavioral_proc of half_subtractor is
begin
process(A,B)
begin
DIF<=A xor B;
BOUT<= (not A) and B;
end process;
end behavioral_proc;

-- Structural
architecture structural of half_subtractor is
component xor2
port(A,B:in std_logic;
Y:out std_logic);
end component;
component inv
port(A:in std_logic;
Y:out std_logic);
end component;
component and2
port(A,B:in std_logic;
Y:out std_logic);
end component;
signal nA: std_logic;
begin
U0: inv port map(A=>A, Y=>nA);
U1: xor2 port map(A=>A,B=>B, Y=>DIF);
U2: and2 port map(A=>nA,B=>B,Y=>BOUT);
end structural;
3.4 Soustracteur Complet
entity full_subtractor is
port(A,B,BI:in std_logic;
DIF,BO:out std_logic);
end full_subtractor;

-- Dataflow
architecture dataflow of full_subtractor is
begin
DIF<=A xor B xor BI;
BO<= (not A and B) or (BI and (not A or B));
end dataflow;

-- Behavioral (PROCESS)
architecture behavioral_proc of full_subtractor is
begin
process(A,B,BI)
begin
DIF<=A xor B xor BI;
BO<= (not A and B) or (BI and (not A or B));
end process;
end behavioral_proc;

-- Structural
architecture structural of full_subtractor is
component half_subtractor
port(A,B:in std_logic;
DIF,BOUT:out std_logic);
end component;
component or2
port(A,B:in std_logic;
Y:out std_logic);
end component;
signal d1,b1,b2: std_logic;
begin
HS1: half_subtractor port map(A=>A,B=>B, DIF=>d1,BOUT=>b1);
HS2: half_subtractor port map(A=>d1,B=>BI,DIF=>DIF,BOUT=>b2);
U5: or2 port map(A=>b1,B=>b2,Y=>BO);
end structural;
4. Compteurs & Registres
4.1 Compteur Up & Down Synthétique
entity up_down_counter is
port(CLK, UP: in std_logic;
Q: out std_logic_vector(3 downto 0));
end up_down_counter;

-- Behavioral (PROCESS)
architecture behavioral of up_down_counter is
begin
process(CLK)
begin
if rising_edge(CLK) then
if UP='1' then
Q <= Q + 1;
else
Q <= Q - 1;
end if;
end if;
end process;
end behavioral;

-- Structural (schéma partiel)

architecture structural of up_down_counter is
component full_adder
port(A,B,CI:in std_logic;
SUM,CO:out std_logic);
end component;
component full_subtractor
port(A,B,BI:in std_logic;
DIF,BO:out std_logic);
end component;
component mux2to1
port(A,B,SEL:in std_logic;
Y:out std_logic);
end component;
signal c0,c1,c2: std_logic;
begin
bit0: mux2to1 port map(A=>Q(0)+ '0', B=>Q(0)- '0', SEL=>UP,
Y=>Q(0));
-- suivre en cascade avec c0, c1...
end structural;
4.2 Registre PISO 4 bits
entity shift_reg is
port(CLK: in std_logic; D: in std_logic;
Q: out std_logic_vector(3 downto 0));
end shift_reg;

-- Behavioral (PROCESS)
architecture behavioral of shift_reg is
begin
process(CLK)
begin
if rising_edge(CLK)
then Q <= D & Q(3 downto 1);
end if;
end process;
end behavioral;

-- Structural
architecture structural of shift_reg is
component d_ff port(D,CLK:in std_logic; Q:out std_logic); end
component;
signal q0,q1,q2,q3: std_logic;
begin
U0: d_ff port map(D=>D, CLK=>CLK, Q=>q0);
U1: d_ff port map(D=>q0, CLK=>CLK, Q=>q1);
U2: d_ff port map(D=>q1, CLK=>CLK, Q=>q2);
U3: d_ff port map(D=>q2, CLK=>CLK, Q=>q3);
Q <= q3 & q2 & q1 & q0;
end structural;
5. Codeur & Décodeur
5.1 Codeur 4→2
entity encoder_4to2 is
port(I: in std_logic_vector(3 downto 0);
Y: out std_logic_vector(1 downto 0));
end encoder_4to2;

-- Dataflow
architecture dataflow of encoder_4to2 is
begin
Y(1)<=I(3) or I(2);
Y(0)<=I(3) or I(1);
end dataflow;

-- Behavioral (PROCESS)
architecture behavioral_proc of encoder_4to2 is
begin
process(I)
begin
case I is
when "0001" => Y<="00";
when "0010" => Y<="01";
when "0100" => Y<="10";
when "1000" => Y<="11";
when others => Y<="00";
end case;
end process;
end behavioral_proc;

-- Structural
architecture structural of
encoder_4to2 is
component or2 port(A,B:in std_logic;
Y:out std_logic);
end component;
begin
U0: or2 port map(A=>I(3), B=>I(2), Y=>Y(1));
U1: or2 port map(A=>I(3), B=>I(1), Y=>Y(0));
end structural;
5.2 Décodeur 2→4
entity decoder_2to4 is
port(I0,I1: in std_logic;
Y0,Y1,Y2,Y3: out std_logic);
end decoder_2to4;

-- Dataflow
architecture dataflow of decoder_2to4 is
begin
Y0<=not I0 and not I1;
Y1<=I0 and not I1;
Y2<=not I0 and I1;
Y3<=I0 and I1;
end dataflow;

-- Behavioral (PROCESS)
architecture behavioral_proc of decoder_2to4 is
begin
process(I0,I1)
begin
Y0<='0';Y1<='0';Y2<='0';Y3<='0';
if I1='0' and I0='0' then Y0<='1';
elsif I1='0' and I0='1' then Y1<='1';
elsif I1='1' and I0='0' then Y2<='1';
else Y3<='1'; end if;
end process;
end behavioral_proc;

-- Structural
architecture structural of decoder_2to4 is
component and2
port(A,B:in std_logic;
Y:out std_logic);
end component;
component inv
port(A:in std_logic;
Y:out std_logic);
end component;
signal n0,n1: std_logic;
begin
inv0: inv port map(A=>I0, Y=>n0);
inv1: inv port map(A=>I1, Y=>n1);
U0: and2 port map(A=>n0, B=>n1, Y=>Y0);
U1: and2 port map(A=>I0,B=>n1, Y=>Y1);
U2: and2 port map(A=>n0,B=>I1, Y=>Y2);
U3: and2 port map(A=>I0,B=>I1, Y=>Y3);
end structural;
6. Bascules
6.1 Bascule D
entity d_ff is
port(D, CLK: in std_logic; Q: out std_logic);
end d_ff;

-- Behavioral
architecture behavioral of d_ff is
begin
process(CLK)
begin
if rising_edge(CLK)
then Q<=D;
end if;
end process;
end behavioral;

-- Structural (Latch Master/Slave)

architecture structural of d_ff is
component d_latch
port(D,EN:in std_logic;
Q:out std_logic);
end component;
signal m_q: std_logic;
begin
U_master: d_latch port map(D=>D, EN=>not CLK, Q=>m_q);
U_slave : d_latch port map(D=>m_q,EN=>CLK, Q=>Q);
end structural;
6.2 Bascule JK
entity jk_ff is
port(J, K, CLK: in std_logic; Q: out std_logic);
end jk_ff;

-- Behavioral
architecture behavioral of jk_ff is
begin
process(CLK)
begin
if rising_edge(CLK) then
case (J & K) is
when "00" => Q<=Q;
when "01" => Q<='0';
when "10" => Q<='1';
when "11" => Q<=not Q;
end case;
end if;
end process;
end behavioral;

-- Structural (JK->D+ D-FF)

architecture structural of jk_ff is
component d_ff
port(D,CLK:in std_logic;
Q:out std_logic);
end component;
signal d_in: std_logic;
begin
d_in<= (J and not Q) or (Q and not K);
U0: d_ff port map(D=>d_in, CLK=>CLK, Q=>Q);
end structural;
6.3 Bascule RS
entity basc is
port(R, S, CLK: in std_logic; Q, QN: out std_logic);
end rs_ff;

Port (R, S, H: in std_logic ;

Q, Q_bar: out std_logic);
end RSH;

architecture basc of RSH is

Signal SIG : std_logic :=0 ;
Signal SIG : std_logic_vector (1 downto 0) ;
Begin
RS(1) <= R;
RS(0) <= S;
process (RS, SIG, H)
if (H=’1’) then
Case RS is

When “00” => SIG<= SIG;

When “01” => SIG<= ‘1’;
When “10” => SIG<= ‘0’;
When others => SIG<= ‘-’;
End case;
else
SIG <= SIG;
End if;
Q <= SIG;
Q_bar <= not SIG;

End process;
end basc ;