MADHAV INSTITUTE OF TECHNOLOGY AND SCIENCE, GWALIOR (M.P.

)
(A Govt. Aided UGC Autonomous & NAAC Accredited Institute, Affiliated to R.G.P.V, Bhopal)

Unit-5
Introduction to Memory, Memory Decoding, Error Detection and
Correction, Programmable Logic Array, Programmable Array Logic,
Sequential Programmable Devices, RTL and DTL Circuits, TTL, ECL, MOS,
CMOS, Application Specific Integrated Circuits.
COURSE OUTCOMES
After completion of the course students would be able to:
CO1. explain the computer architecture for defining basic component and
functional unit.
CO2. recall different number system and solve the basic arithmetic operations.
CO3. develop the understanding of combinational circuits.
CO4. analyze the basic concept of sequential circuits.
CO5. compare various memories.
CO6. solve the boolean functions using logic gates.
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 5-1. Introduction
 There are two types of memories that are used in digital
systems:
Random-access memory(RAM): perform both the write and
read operations.
Read-only memory(ROM): perform only the read operation.

 The read-only memory is a programmable logic device.

Other such units are the programmable logic array(PLA),
the programmable array logic(PAL), and the field-
programmable gate array(FPGA).
 Array logic
 A typical programmable logic device may have hundreds to
millions of gates interconnected through hundreds to
thousands of internal paths.
 In order to show the internal logic diagram in a concise
form, it is necessary to employ a special gate symbology
applicable to array logic.

Fig. 5-1 Conventional and Array Logic Diagrams for OR Gate

 5-2. Random-Access Memory
 A memory unit stores binary information in groups of bits called words.
1 byte = 8 bits
1 word = 2 bytes
 The communication between a memory and its environment is
achieved through data input and output lines, address selection lines,
and control lines that specify the direction of transfer.

Fig. 5-2 Block Diagram of a Memory Unit

 Content of a memory
 Each word in memory is
assigned an identification
number, called an address,
starting from 0 up to 2k-1,
where k is the number of
address lines.
 The number of words in a
memory with one of the
letters K=210, M=220, or G=230.
64K = 216 2M = 221
4G = 232
Fig. 5-3 Content of a 1024 X 16 Memory
Fig. 5-3 Content of a 1024 X 16 Memory 1 Fig. 5-4 Content of a 1024 X 16 Memory 2
 1GB 00 0000 RAM 1
01 0000 RAM 2
0 0000000----0(30)
10 0000 RAM 3
11 0000
31 + 1 = 32
G=30 G=30
RAM - 1

G =31
G=30
RAM – 2
RAM - 1

2GB
G=30

1-chip select: memory location select 0000000--------00(31)

 Write and Read operations
 Transferring a new word to be stored into
memory:
1. Apply the binary address of the desired word to
the address lines.
2. Apply the data bits that must be stored in
memory to the data input lines.
3. Activate the write input.
 Write and Read operations
 Transferring a stored word out of memory:
1. Apply the binary address of the desired word to the
address lines.
2. Activate the read input.
 Commercial memory sometimes provide the two control
inputs for reading and writing in a somewhat different
configuration in table 5-1.
Table – 5-1
 Memory description in HDL
A memory of 1024 words with
16-bits per word is declared
as
reg [15:0] memword[0:1023];

Read/Write = 1
DataOut  Mem[Address];

Read/Write =0
Mem[Address]  DataIn;
 Timing Waveforms (write)
 The access time and cycle time
of the memory must be within a
time equal to a fixed number of
CPU clock cycles.
 The memory enable and the
read/write signals must be
activated after the signals in
the address lines are stable to
avoid destroying data in other
memory words.
 Enable and read/write signals
must stay active for at least
50ns.
 Timing Waveforms (read)
 The CPU can transfer
the data into one of its
internal registers
during the negative
transition of T3.

Fig. 5-4 Memory Cycle Timing Waveform

 Types of memories
 In random-access memory, the word locations may
be thought of as being separated in space, with
each word occupying one particular location.
 In sequential-access memory, the information
stored in some medium is not immediately
accessible, but is available only certain intervals
of time. A magnetic disk or tape unit is of this
type.
 Static RAM
 SRAM consists essentially of internal latches that store the
binary information.
 The stored information remains valid as long as power is
applied to the unit.
 SRAM is easier to use and has shorter read and write cycles.
 Low density, low capacity, high cost, high speed, high
power consumption.
 Dynamic RAM
 DRAM stores the binary information in the form of electric
charges on capacitors.
 The capacitors are provided inside the chip by MOS
transistors.
 The capacitors tends to discharge with time and must be
periodically recharged by refreshing the dynamic memory.
 Types of memories
 Memory units that lose stored information when
power is turned off are said to be volatile.
 Both static and dynamic, are of this category since
the binary cells need external power to maintain
the stored information.
 Nonvolatile memory, such as magnetic disk, ROM,
retains its stored information after removal of
power.
 5-3. Memory decoding
 The equivalent logic of a binary cell that stores one bit of
information is shown below.
Read/Write = 0, select = 1, input data to S-R latch
Read/Write = 1, select = 1, output data from S-R latch

Fig. 5-5 Memory Cell

SR latch with NOR gates
 4X4 RAM
 There is a need for decoding
circuits to select the memory
word specified by the input
address.
 During the read operation, the
four bits of the selected word go
through OR gates to the output
terminals.
 During the write operation, the
data available in the input lines
are transferred into the four
binary cells of the selected word. Fig. 5-6 Diagram of a 4 X 4 RAM

• A memory with 2k words of n bits per word requires k address lines that go into
kx2k decoder.
 Coincident decoding
address
 A decoder with k inputs
and 2k outputs requires 2k 10 X 1024
AND gates with k inputs
per gate.
 Two decoding in a two-
dimensional selection
scheme can reduce the
number of inputs per gate.
 1K-word memory, instead
of using a single 10X1024
decoder, we use two 5X32 Fig. 5-7 Two-Dimensional Decoding
Structure for a
decoders. 1K-Word Memory
 Address multiplexing
 DRAMs typically have four times the density of SRAM.

 The cost per bit of DRAM storage is three to four times less
than SRAM. Another factor is lower power requirement.
 Address multiplexing
 Address multiplexing will reduce the number of pins in the
IC package.

 In a two-dimensional array, the address is applied in two

parts at different times, with the row address first and the
column address second. Since the same set of pins is used
for both parts of the address, so can decrease the size of
package significantly.
 Address multiplexing for 64K DRAM
 After a time equivalent to Column Address Selection

the settling time of the row

selection, RAS goes back to
the 1 level.
Row Address Selection
 Registers are used to store
the addresses of the row
and column.
 CAS must go back to the 1
level before initialing
another memory operation.
Fig. 5.8 Address Multiplexing for a 64K DRAM
 5-4. Error detection and correction
 It is protecting the occasional errors in storing and
retrieving the binary information.
 Parity can be checked the error, but it can’t be
corrected.
 An error-correcting code generates multiple parity
check bits that are stored with the data word in
memory.
 1 0 0 1 1 1 0 0
Hamming Code 1 2 3 4 5 6 7 8

 One of the most common used in RAM was devised by R. W.

Hamming (called Hamming code).
 In Hamming code:
k = parity bits in n-bit data word,
forming a new word of n + k bits. Those positions
numbered as a power of 2 are reserved for the parity bits.
the remaining bits are the data bits.
 Hamming Code
Ex. Consider the 8-bit data word 11000100. we include four
parity bits with it and arrange the 12 bits as follows:
Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
P1 P2 1 P4 1 0 0 P8 0 1 0 0

P1 = XOR of bits(3,5,7,9,11) = 1 ⊕ 1 ⊕ 0 ⊕ 0 ⊕ 0 = 0
P2 = XOR of bits(3,6,7,10,11) = 1 ⊕ 0 ⊕ 0 ⊕ 1 ⊕ 0 = 0
P4 = XOR of bits(5,6,7,12) = 1 ⊕ 0 ⊕ 0 ⊕ 0 = 1
P8 = XOR of bits(9,10,11,12) = 0 ⊕ 1 ⊕ 0 ⊕ 0 = 1
 P8 P4 P2 P1
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
 Hamming Code
 The data is stored in memory together with the parity bit as 12-bit
composite word.
Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
0 0 1 1 1 0 0 1 0 1 0 0
 When read from memory, the parity is checked over the same
combination of bits including the parity bit.

C1 = XOR of bits(1,3,5,7,9,11)
C2 = XOR of bits(2,3,6,7,10,11)
C4 = XOR of bits(4,5,6,7,12)
C8 = XOR of bits(8,9,10,11,12)
 Error-Detection
 A 0 check bit designates an even parity over the
checked bits and a 1 designates an odd parity.
 Since the bits were stored with even parity, the
result,
C = C8C4C2C1 = 0000, indicates that no error has
occurred.
 If C ≠ 0, then the 4-bit binary number formed by
the check bits gives the position of the erroneous
bit.
 C1 = XOR of bits(1,3,5,7,9,11)
C2 = XOR of bits(2,3,6,7,10,11)

Example C4 = XOR of bits(4,5,6,7,12)

C8 = XOR of bits(8,9,10,11,12)
Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
0 0 1 1 1 0 0 1 0 1 0 0 No error
1 0 1 1 1 0 0 1 0 1 0 0 Error in bit 1 (Case 1)

0 0 1 1 0 0 0 1 0 1 0 0 Error in bit 5

0 0 1 1 1 0 0 1 0 1 1 0 Error in bit 11

 Evaluating the XOR of the corresponding bits, get the four check bits

 C8 C4 C2 C1
For no error: 0 0 0 0
with error in bit 1: 0 0 0 1
with error in bit 5: 0 1 0 1
with error in bit 11: 1 0 1 1
 1 1 1 1 p1 p2 p4
P1 p2 1 p4 111 p8 11111111
Hamming Code
 The Hamming Code can be Table 5-2
used for data words of any
length.
 Total bit in Hamming Code
is n + k bits, the syndrome
value C consists of k bits
and has a range of 2k value
between 0 and 2k − 1. the
range of k must be equal
to or greater than n + k,
giving the relationship
2k-1 ≥ n + k
 Single-Error correction, Double-Error
detection
 The Hamming Code can detect and correct only a single
error.
 By adding another parity bit to the coded word, the
Hamming Code can be used to correct a single error and
detect double errors. Becomes 001110010100P13.

001110010100 P13  001110010100 1

101111010100 P13 -> 101111010100 1 p = 0
P= XOR( 001110010100 1 )

if P = 0, the parity is correct (even parity), but if P = 1,

then the parity over the 13 bits is incorrect (odd parity).
 Single-Error correction, Double-Error
detection
1. If C = 0 and P = 0, no error occurred
2. If C ≠ 0 and P = 1, a single error occurred that
can be corrected
3. If C ≠ 0 and P = 0, a double error occurred that
is detected but that cannot be corrected
4. If C = 0 and P = 1, an error occurred in the P13
bit
 5-5. Read-Only Memory
 A block diagram of a ROM is shown below. It consists of k
address inputs and n data outputs.
 The number of words in a ROM is determined from the fact
that k address input lines are needed to specify 2k words.

Fig. 5-9 ROM Block Diagram

 32 X 8 ROM 2^5 X 8
K=5
Construction of ROM N=8
K x 2^k = 5 X 32 decoder
OR gate =8
 Each output of the decoder represents a memory address.
 Each OR gate must be considered as having 32 inputs.
 A 2k X n ROM will have an internal k X 2k decoder and n
OR gates. 256 x 16 ROM 8 x 256 DECODER, n=16

Fig. 5-10 Internal Logic of a 32 X 8 ROM

 Truth table of ROM
 A programmable connection between to lines is logically
equivalent to a switch that can be altered to either be close
or open.
 Intersection between two lines is sometimes called a cross-
point.
Table 5-3
 Programming the ROM
In Table 5-3, 0  no connection
1  connection
Address 3 = 10110010 is permanent storage using fuse link

1 0 1 1 0 0 1 0

X : means connection

Fig. 5-11 Programming the ROM According to Table 5-3

 Combinational circuit implementation
 The internal operation of a ROM can be interpreted in two
way: First, a memory unit that contains a fixed pattern of
stored words. Second, implements a combinational circuit.
 Fig. 5-11 may be considered as a combinational circuit with
eight outputs, each being a function of the five input
variables.

A7(I4, I3, I2, I1, I0) = Σ(0,2,3…,29)

Sum of minterms

In Table 5-3, output A7

 Example
 Design a combinational circuit using a ROM. The circuit
accepts a 3-bit number and generates an output binary
number equal to the square of the input number.
Derive truth table first
Table 5-4
Example

Fig. 5-12 ROM Implementation of example

 Types of ROMs
 The required paths in a ROM may be programmed in four
different ways.
1. Mask programming: fabrication process
2. Read-only memory or PROM: blown fuse /fuse intact
3. Erasable PROM or EPROM: placed under a special
ultraviolet light for a given period of time will erase the
pattern in ROM.
4. Electrically-erasable PROM(EEPROM): erased with an
electrical signal instead of ultraviolet light.
 Combinational PLDs
 A combinational PLD is an integrated circuit with
programmable gates divided into an AND array and an OR
array to provide an AND-OR sum of product implementation.
 PROM: fixed AND array constructed as a decoder and
programmable OR array.
 PAL: programmable AND array and fixed OR array.
 PLA: both the AND and OR arrays can be programmed.
Combinational PLDs

Fig. 5-13 Basic Configuration of Three PLDs

 5-6. Programmable Logic Array
 Fig.5-14, the decoder in PROM is replaced by an array of
AND gates that can be programmed to generate any
product term of the input variables.
 The product terms are then connected to OR gates to
provide the sum of products for the required Boolean
functions.
 The output is inverted when the XOR input is connected to
1 (since x⊕1 = x’). The output doesn’t change and connect
to 0 (since x⊕0 = x).
 PLA
F1 = AB’+AC+A’BC’
F2 = (AC+BC)’

Table 5-5

Fig. 5-14 PLA with 3 Inputs 4 Product Terms and 2 Outputs

 Programming Table
1. First: lists the product terms numerically
2. Second: specifies the required paths between
inputs and AND gates
3. Third: specifies the paths between the AND and
OR gates
4. For each output variable, we may have a T(ture)
or C(complement) for programming the XOR gate
 Simplification of PLA
 Careful investigation must be undertaken in order
to reduce the number of distinct product terms,
PLA has a finite number of AND gates.
 Both the true and complement of each function
should be simplified to see which one can be
expressed with fewer product terms and which one
provides product terms that are common to other
functions.
 Example
Implement the following two Boolean functions with a PLA:
F1(A, B, C) = ∑(0, 1, 2, 4)
F2(A, B, C) = ∑(0, 5, 6, 7)

The two functions are simplified in the maps of Fig.5-15

1 elements

0 elements
 PLA table by simplifying the function
 Both the true and complement
of the functions are simplified in
sum of products.
 We can find the same terms
from the group terms of the
functions of F1, F1’,F2 and F2’
which will make the minimum
terms.

F1 = (AB + AC + BC)’
F2 = AB + AC + A’B’C’ Fig. 5-15 Solution to the Example
PLA implementation

Fig. 5.15
 5-7. Programmable Array Logic
 The PAL is a programmable logic device with a fixed OR array and a
programmable AND array.

Fig. 5-16 PAL with Four Inputs. Four Outputs, and Three-Wide AND-OR Structure
 PAL
 When designing with a PAL, the Boolean functions
must be simplified to fit into each section.
 Unlike the PLA, a product term cannot be shared
among two or more OR gates. Therefore, each
function can be simplified by itself without regard
to common product terms.
 The output terminals are sometimes driven by
three-state buffers or inverters.
 Example
w(A, B, C, D) = ∑(2, 12, 13)
x(A, B, C, D) = ∑(7, 8, 9, 10, 11, 12, 13, 14, 15)
y(A, B, C, D) = ∑(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z(A, B, C, D) = ∑(1, 2, 8, 12, 13)

Simplifying the four functions as following Boolean functions:

w = ABC’ + A’B’CD’
x = A + BCD
w = A’B + CD + B’D’
w = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D = w + AC’D’ + A’B’C’D
 PAL Table
 z has four product terms, and we can replace by w with two
product terms, this will reduce the number of terms for z from
four to three.
Table 5-6
PAL implementation

D
Fuse map for example

Fig. 5-17 Fuse Map for PAL as Specified in Table 5-6

 5-8. Sequential Programmable Devices

 Sequential programmable devices include both

gates and flip-flops.
 There are several types of sequential
programmable devices, but the internal logic of
these devices is too complex to be shown here.
 We will describe three major types without going
into their detailed construction.
 Sequential Programmable Devices
1. Sequential (or simple) Programmable Logic Device (SPLD)
2. Complex Programmable Logic Device (CPLD)
3. Field Programmable Gate Array (FPGA)

Fig. 5-18 Sequential Programmable Logic Device

 FPLS
 The first programmable device developed to support
sequential circuit implementation is the field-programmable
logic sequencer(FPLS).
 A typical FPLS is organized around a PLA with several
outputs driving flip-flops.
 The flip-flops are flexible in that they can be programmed
to operate as either JK or D type.
 The FPLS did not succeed commercially because it has too
many programmable connections.
 SPLD
 Each section of an SPLD is called a macrocell.
 A macrocell is a circuit that contains a sum-of-
products combinational logic function and an
optional flip-flop.
 We will assume an AND-OR sum of products but in
practice, it can be any one of the two-level
implementation.
 Macrocell
 Fig.5-19 shows the logic of a basic macrocell.
 The AND-OR array is the same as in the combinational PAL
shown in Fig.5-16.

Fig. 5-19 Basic Macrocell Logic

 CPLD
 A typical SPLD has from 8 to 10 macrocells within one IC
package. All the flip-flops are connected to the common
CLK input and all three-state buffers are controlled by the
EO input.
 The design of a digital system using PLD often requires the
connection of several devices to produce the complete
specification. For this type of application, it is more
economical to use a complex programmable logic device
(CPLD).
 A CPLD is a collection of individual PLDs on a single
integrated circuit.
 CPLD
 Fig.5-20 shows a general configuration of a CPLD. It consists of
multiple PLDs interconnected through a programmable switch
matrix. 8 to 16 macrocell per PLD.

Fig. 5-20 General CPLD Configuration

 Gate Array
 The basic component used in VLSI design is the
gate array.
 A gate array consists of a pattern of gates
fabricated in an area of silicon that is repeated
thousands of times until the entire chip is covered
with the gates.
 Arrays of one thousand to hundred thousand gates
are fabricated within a single IC chip depending on
the technology used.
 FPGA
 FPGA is a VLSI circuit that can be programmed in the user’s
location.
 A typical FPGA logic block consists of look-up tables,
multiplexers, gates, and flip-flops.
 Look-up table is a truth table stored in a SRAM and
provides the combinational circuit functions for the logic
block.
 Differential of RAM and ROM in FPGA
 The advantage of using RAM instead of ROM to store the truth
table is that the table can be programmed by writing into
memory.

 The disadvantage is that the memory is volatile and presents

the need for the look-up table content to be reloaded in the
event that power is disrupted.