International Journal of Engineering Research & Technology (IJERT)

ISSN: 2278-0181
Vol. 4 Issue 08, August-2015

Design and Performance Evaluation of Error

Detection and Correction using Concatenated
BCH and LDPC coding Scheme for Data Streams
in Satellite Communication
Girish Kumar N G, Dr. M N Sree Ranga Raju,
Reasearch Scholar Professor
Department of Electronics and Communication Department of Electronics and Communication
Regional Research Centre, Bangalore Institute of Technology
Visvesvaraya Technological University Bangalore, India
Belagavi, India

Abstract— Continued Research & Development is of paramount technique is then introduced in Section 3. Simulated results
importance in the area of error-revising code turns into a vital are presented in Section 4. Section 5 conclusion with future
interest for the perseverance these days in DVB-S2 and flash enhancement of this work.
memory. LDPC codes are proposed for their exceptional error
rectifying capability. Then again, the error floor marvel of II. CONCATENATED CODES
LDPC codes may not meet the substantial low error rate
Concatenated codes are widely used to increase the
requirements of flash memory applications. Along these lines,
efficiency of error control coding. For example DVB-S2
concatenation of BCH and LDPC codes results in greater
harmony between magnificent error remedying capability and second generation satellite systems, It is good to use highly
low error rate turns into an option coding structure. In this efficient LDPC codes concatenated with BCH codes to
work, concatenated coding scheme is proposed. By looking into achieve very low error rate which is much necessary for its
the past concatenated coding scheme, our outline enhances the applications and same coding scheme will also add advantage
error reducing capability in the waterfall region while keeps low in the usage of multilevel flash memories for storing the high
error floor. definition data as only LDPC will leave errors in the waterfall
region. Fig 1 illustrates the concatenated scheme. Here the
Keyword: Low-density parity-check code, BCH code, outer code is based on hard decision whereas inner code based
concatenated code, flash memory, error floor. on soft decision.
I. INTRODUCTION
As of late, usage of flash memory in second era satellites
like DVB-S2 frameworks and usage of flash memories to
store huge amount of data captured by the satellite systems
turns into a cutting edge exploration. In particular, the usage
of single-level cell flash memory utilizes traditionally Bose-
Chaudauri Hocquenghem (BCH) codes to ensure the
uprightness of information, yet the same method may not meet Fig 1. Concatenated codes
the error insurance for multiple cell flash memory. In this A. BCH codes:
manner, analysts started to look into alternative in error
adjusting codes, for example, Low Density Parity Check Numerous error revising strategies are exists, one of them
(LDPC) codes, [1], [2] to upgrade the error adjustment is direct block code and the least difficult block codes are
capability for satellite Applications. Hamming codes. They are fit for remedying stand out
irregular error and in this way are not for all intents and
LDPC codes have exceptional error rectifying capacity in the purposes helpful, unless a straightforward error control circuit
waterfall locale. Be that as it may, their error floor sensation is needed. More advanced error remedying codes are the Bose,
limits the use of LDPC codes for satellite media applications Chaudhuri and Hocquenghem (BCH) codes that are a
that regularly oblige to a greater degree with respect to low speculation of the Hamming codes for numerous error
error rates. The concatenated coding framework that serially rectifications. The (Bose-Chaudhuri-Hocquenghem) BCH
links BCH with LDPC codes is being proposed as an codes shape a substantial class of capable irregular error
alternative. Our proposed new outline has better error remedying cyclic codes having fit for various error revisions.
correcting capability in the waterfall region [3]. BCH codes work over limited fields or Galois fields and its
The rest of the paper is composed as takes after. Section 2 equipment usage can conceivable on parallel Galois Field
briefs the concatenated codes. The proposed code choice (2m) [4]. As innovation is changing quickly and the
information transmission is being digitize all over the place, a

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 4 Issue 08, August-2015

little error event amid information exchange can degenerate g(x) = LCM{M1 (x), M3 (x), … , M2t−1 (x)} (3)
the whole secure data simply like in bank. It is important to
recognize such error and right it to get unique data at the Then for a given message m(x) the code polynomial is given
receiver. by:

1. Encoding of BCH codes: In non-systematic form:

These codes are summed up type of Hamming codes that C(x) = g(x)m(x) (4)
permits various error redresses. They shape a class of effective In systematic form:
arbitrary error redressing cyclic codes which gives a
determination of bigger block lengths, code rates and error C(x) = P(x) + x n−k m(x) (5)
revising capacity. Where
BCH codes are characterized by the following parameters xn−k m(x)
P(x) = modulo of ( ) (6)
For any positive integer’s m where m ≥ 3 and t where t < 2 -1 m g(x)

there exist a binary BCH code where [4]:

Block Length: n=2m-1 2. Decoding of BCH codes:
Number of Parity-Check digits:r=n-k ≤ mt
Minimum distance: dmin ≥2t+1 Berlekamp Algorithm:

The Alphabet of a BCH code for n=2m-1 is represented as B. Find out the syndrome S=(S1,S2<… ..S2t) from the
the set of elements of an appropriate Galois field, GF(2m) received polynomial r(x)
where primitive element is α. C. Compute the error Location polynomial σ(x) from the
syndrome segments S1,S2,… … .S2t utilizing the
The generator polynomial of the t error correcting BCH iterative method
code is the Least Common Multiple of D. Focus the error area numbers.
M1 (x), M2 (x), … … … … , M2t (x) E. At that point focus the error polynomial e(x).
i.e., F. add e(x) to the received polynomial r(x) to get the
codeword
g(x) = LCM{M1 (x), M2 (x), … , M2t (x)} (1)
Where, For effortlessness it has been utilized thin sense BCH code
with settled code rate (0.7) and variable codeword length (n)
M(x) Minimal polynomial of αi , i=1,2,…2t (2)
and variable message length (k) to assess the execution of
Since the minimal polynomials for even power of α are such code to see the dynamic parameters. Fig.1 represents the
same as for the odd power of α, then the generator matrix aftereffect of BER when utilizing just BCH codes.
reduces to

Fig 2. BCH encoding and decoding for Different codewords

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 4 Issue 08, August-2015

B. LDPC codes:

1. Code Structure:
An LDPC code is defined as the null space of the (n-k) X
k parity check matrix where n is the block length and k is
the information binary bits. Such matrix consists of L 1’s
in each row and Y 1’s in each column. Where Y<L and
both Y and L are small compared to block length n. the
below matrix illustrates the (7,3) LDPC code parity check
matrix with above conditions [4].

1 1 0 1 0 0 0
0 1 1 0 1 0 0
0 0 1 1 0 1 0
H= 0 0 0 1 1 0 1
1 0 0 0 1 1 0
0 1 0 0 0 1 1
[1 0 1 0 0 0 1] Fig 3. Tanner Graph of (7, 3) LDPC code

Fig 4. Performance of LDPC codes for various iterations

2. Encoding using LDPC codes:

A −1
γk = γch + ∑i=0
v
γi − γold
k (9)
To perform the encoding the parity check matrix is first
converted into a systematic form and then the generator γch − Channels of LLR
matrix is obtained by: γi -LLR of incident edges

H = [P, In−k ] (7) Fig 4 shows simulation result of LDPC code. The parity
check matrix used here with dimension of (32400 × 64800),
G = [Ik , P T ] (8) six ones in the first row, seven ones in the (2 to 32400) rows,
eight ones in the columns of (1 to 12960) and three ones in
This resultant generator matrix is then used to encode. the columns (1261 to 32400), while columns (32401 to
64800) form a lower triangular matrix.
3. Decoding using LDPC codes: It can be observed that using LDPC code only can achieve
good performance. It needs only 1 dB signal to noise ratio to
In this research work sum product algorithm is used for achieve 10-5 BER with 5 iterations and it can be decreased
decoding. It exchanges soft information iteratively between much more by increasing number of iteration, but the large
variable and check nodes. Here the messages which are increase here will introduce delay time which make such
getting exchanged are Log Likelihood Ratios. Each variable system unsuitable for real time applications.
node of degree Av calculates an update of message k
according to [5]:

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 4 Issue 08, August-2015

Fig 5. Proposed Model of Concatenated BCH and LDPC code with interleaver

III. PROPOSED MODEL

As we seen earlier to get a better BER in LDPC more number
of iterations should be introduced which makes delay time.
So to overcome this issue a concatenated Coding scheme is
proposed [6], [7], [8], [9], [10] which concatenates BCH and
LDPC as shown in the fig 5.
A. Concatenated BCH and LDPC Encoding and Decoding:
In this coding scheme the outer encoder is BCH encoder and
Inner Encoder is LDPC encoder. That is one block of data is
first encoded by outer BCH encoder and then encoded BCH
codeword is partitioned into ‘X’ equal sized segments, and
each segment is encoded by the inner LDPC encoder. Let
NBCH and NLDPC be the code rate of outer BCH code and
inner LDPC code respectively. Then the overall code rate is
given by: Fig 7. Flowchart for concatenated LDPC and BCH decoder
Nt = NBCH ∗ NLDPC (10)
It is clear that such system achieve nearly to zero BER very
If all the inner code word from LDPC decoder is decoded near to 0 dB with only 6 iterations, so the curve has become
properly then it is not necessary to used BCH decoder for very sharp as seen in Fig 5 which indicate more than 1 dB
decoding. Because of LDPC code mis-correction at the gain in contrast with the curve of LDPC only so that our
waterfall region BCH decoder is used to detect the error system is success to get very low BER with low delay time.
practically.

So each MBCH symbol will be processed by forward error

correction encoder to generate KLDPC symbol codeword. The
KBCH - MBCH parity check symbol of the systematic BCH
encoder shall be added after MBCH symbol and the KLDPC –
MLDPC parity symbol of LDPC encoder are inserted after
MLDPC
MLDPC = KBCH

MBCH KBCH - MBCH KLDPC – MLDPC

KLDPC
Fig 6. Format of data after encoding

The length of code word for BCH code is n=63, while the
message k=45 only so the code rate is high (0.71) so it will Fig 8. The performance of the proposed scheme
not lead to reduced spectral efficiency but in return allows to
reduce the number of iterations which can get good
performance suitable to real time applications as shown in
Fig.8 which illustrates the results of proposed system.

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 4 Issue 08, August-2015

IV. RESULTS AND CONCLUSION REFERENCES

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GIRISH KUMAR N G Currently working as Assistant Professor in

Bangalore Institute of Technology, Visvesvaraya Technological
University, Karnataka, India. Has more than 7 years of teaching
experience in Electronics and Communication Engineering. Received
the B.E. degree in Electronics and Communication Engineering from
Visvesvaraya Technological University, Karnataka, India in 2005.
Received the Master of Science Degree in Intelligent Systems in
School Of Computing, from University of Sunderland, United
Kingdom. Presently he is pursuing his final year M.Sc Engg through
Research, with specialization in Electronics and Communication in
RRC, Visvesvaraya Technological University, Belagavi, Karnataka,
India.

Dr. M N SREERANGARAJU received BE Degree in 1985 from

Bangalore University and M.Tech in 1991 from University of Mysore
both in Electronics Engineering, and PhD(Telecommuniction Engg)
from VMU, Salem, TN, India in 2011.Professor of Electronics and
Communication Engineering at Bangalore Institute of Technology
(BIT), Bengaluru, India has been in Teaching UG and PG Students of
Electronics and Telecommunication Engineering students for nearly
Thirty Years. He has organized several National level conferences and
workshops in this tenure. He has published his Research papers in
Prestigious IEEE Conferences held in USA, China, Malaysia and
Egypt. He also has served has Session Chair for several National and
International Conferences held in India and aboard. He also has served
as editor of several journals and Magazine. He holds life member of
ISTE, MVLSI, and IMAPS and also member of IEEE. His research
interests include mobile and wireless communications and networks,
personnel communication services and high speed communication
routing protocols and wireless channel modeling.

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