Digital Signal Processing using FPGA (ECE-852)

Week 1 Part 1: Course Introduction

Instructor: Dr. Saad Qayyum

1
Outline
• Background
• Motivation
• Abstraction and Design Methodologies
• Steps Involved in Digital Design
• Comparison with Software flow
• Scope of this Course
• EDA Tools

2
Background

3
Real-world Problem Solving
• Generic block diagram of a real-world electronic system

4
Real-world Problem Solving

5
Sensors/Transducers

https://byjus.com/physics/difference-between-transducer-and-sensor/ 6
Interface/Signal Conditioning Circuitry

7
Interface/Signal Conditioning Circuitry

8
Signal Processing Circuitry
• Analog vs Digital Implementation

9
Signal Processing Circuitry
• Software vs Hardware Implementation

10
Motivation

11
Motivation
• With the advent of semiconductor technology, digital computation
power has grown exponentially.
• Computers, laptops, smart phones, gadgets etc. constitute a
substantial portion of digital logic.
• Application areas
• Signal Processing e.g., Medical informatics and Computer Vision
• Communications
• Artificial Intelligence e.g., Smart homes and Smart grids
• Digital Control of Power electronics (e.g., for Electric Vehicles)
• Crypto currency mining

12
VLSI Technology Growth (Moore’s Law)
• In 1965, Gordon Moore predicted
that semiconductor technology will
double its effectiveness every 18
months
• With every generation can integrate
2x more functions per chip; chip cost
does not increase significantly
• Technology shrinks by 0.7/generation

13
Technology Trends

EECS141- UC Berkely Lecture Notes 14

Specifications of Intel Microprocessors

15
EECS141- UC Berkely Lecture Notes
Complexity vs Productivity Gap
• Cost of a function
decreases by 2x but
design engineering
population does not
double every two years…
• Hence, a need for more
efficient design methods
• Exploit different levels of
abstraction
• E.g. Use design automation

16
Challenges in Digital System Design

• “Microscopic Problems” • “Macroscopic Issues”

• Ultra-high speed design • Complexity
• Interconnect • Time-to-Market
• Noise, Crosstalk • High-Level Abstractions
• Reliability, • Reuse & IP: Portability
Manufacturability • etc.
• Power Dissipation
• Clock distribution
• Quantum effects

EECS141- UC Berkely Lecture Notes 17

Abstraction and Design
Methodologies

18
Levels of Abstraction - Overview
• Helpful to
• Reduce design time
• Reduces design complexity
• Performance may not be as good
as we go higher up the abstraction
stack
• Not always true

19
Device-level Abstraction
• Fabs/Foundries provide a Process Design Kit
(PDK)
• The PDK includes:
• Devices (Transistors, Resistors, Capacitors, Diodes)
• Layers
• Design Rules
• Various “Flavors” of PDKs are available, e.g.:
• General Purpose/High Speed/Low Power
• Various number of Metal Interconnect Layers

https://www.eng.biu.ac.il/temanad/digital-integrated-circuits/ 20
Circuit Level Abstraction
• Using the devices supplied in the PDK,
Schematics are drawn.
• Simulators, such as SPICE, are used to test
and optimize the circuits.
• Component parameters can be modified to
optimize the schematic, e.g.:
• Length and Width of the transistors
• Capacitance and Resistance values
• Circuits are drawn with a Layout Editor and
parasitics are extracted for accurate
simulation.
https://www.eng.biu.ac.il/temanad/digital-integrated-circuits/ 21
Gate Level Abstraction
• Circuits are abstracted into a black box
• Logic gates, flip-flops, etc.
• Gates are defined by easy-to-use characteristics
• Boolean Functionality
• Interface (i.e. Pins or ports).
• Delay and power consumption.
• Input and output capacitance.
• Size and geometry.
• Once a gate is abstracted, it can be used by higher level
tools, such as HDLs.
https://www.eng.biu.ac.il/temanad/digital-integrated-circuits/ 22
Module Level Abstraction
• Gates and other low-level circuits are connected to make
modules (adders, multipliers, memories, etc.).
• The modules are tested for functionality and are
abstracted for system integration.
• Modules may also be defined using HDLs, instantiating
gates
• EDA tools are used to verify functionality at all levels of
hierarchy.

https://www.eng.biu.ac.il/temanad/digital-integrated-circuits/ 23
System Level Abstraction
• System are defined to comply with standards and
implement protocols.
• Architectural design defines high level abstractions to
build a system.
• This abstraction level defines:
• Registers
• Instruction Sets
• Control Blocks
• Buses etc.
• Systems can be implemented with HDLs by instantiating
modules.
https://www.eng.biu.ac.il/temanad/digital-integrated-circuits/ 24
Digital Design Methodologies
• Due to the time and cost constraints, design is rarely done from
device level through to system level by a team/company.
• Trade-offs are taken into consideration, as abstractions are usually
designed generically and therefore come with some overhead.
• Various Design methodologies can be used to reduce the time-to-
market and development cost.
• Full custom design
• Semi-custom design

25
Full Custom Design
• The original design style.
• Everything is done at transistor level
• Rarely used in digital design
• High cost/time to market/effort
• Significant gain in performance.
• Feasible for small-scale digital or analog
designs only

www.arstechnica.com 26
Semi Custom Design
• Large/complex digital systems are built using this design methodology
• Two major classes:
• Cell-based design and
• Array-based design.

27
Cell-based Design
• Used for ASIC flow
• Cell-based design leverages the use of library cells
• Standard-Cell based Design: Need to be designed once and stored or
• Macro Cell based Design: Use of cell generators that synthesize macro-cell
layouts from their functional specifications
• In cell-based design the manufacturing process is not simplified at all
with respect to custom design.
• Instead, the design process is simplified, because of the use of ready-
made building blocks.

28
Standard Cells based Design
• The standard cells are stored in a library.
• Cells are designed once
• Updates are required for new technology.
• The library maintenance is far from a trivial because every cell needs
to be parametrized
• In terms of area and delay
• Over ranges of temperatures and operating voltages
• An extension is the hierarchical standard-cell style, where larger cells
can be derived by combining smaller ones.

29
Standard Cells based Design
• Requires automation
• Library binding or Technology mapping is required
• The user of a standard-cell library must first conform his or her design to the
available library primitives
• Placement and routing
• Cells are placed and wired.
• Standard cell layouts meet placement guidelines for easy physical
implementation.
• Cell height and Cell width
• Position of Voltage rails and wells
• PR Boundary
• Metal layers

30
Array based Design
• Array-based design exploits the use of an unconnected matrix of
prefabricated components
• Personalized and interconnected as per design requirement.
• Array-based circuits can be further classified as
• Prediffused (Mask Programmable Gate Arrays aka MPGAs) or
• Prewired (Field Programmable Gate Arrays aka FPGAS).
• For first case, only the metal and contact layers are used to program
the chip, hence the name "mask programmable."
• Fewer manufacturing steps result into lower fabrication time and
cost.
31
FPGA based Design
• FPGA –Field Programmable Gate Array
• Array of configurable logic blocks, and
programmable interconnect structures
• Pros and cons
• Uses higher level of abstraction
• Design flexibility
• Quick time to market
• Low-cost for small-scale designs
• Limited Capacity

32
Comparison of Design Methodologies
• Full Custom Design
• Customization for optimized power, performance, area.
• High complexity, cost, time-to-market, high risk.
• Standard Cell based Design
• Simple, fast, reliable.
• Only Digital designs. Excess power, wirelength, etc.
• FPGA based Design
• Post silicon configurability, very inexpensive.
• High percentage of overhead. High cost per chip.

33
Stages for Implementing a
Digital Design

34
What is Digital Synthesis?
• Digital Synthesis is a process that converts an abstract description of a
system into
• a technology-specific, gate-level netlist
• optimized for a set of pre-defined constraints.
• You start with:
• A behavioral or RTL design
• A standard cell library
• A set of design constraints
• You end up with:
• A gate level netlist, mapped to the standard cell library
• For FPGAs: mapped to LUTs, flip flops, and RAM blocks
• It’s also optimized for a set of constraints e.g., speed, area, power, etc.

https://www.eng.biu.ac.il/temanad// 35
What is Synthesis?

https://www.eng.biu.ac.il/temanad/ 36
https://www.eng.biu.ac.il/temanad/digital-integrated-circuits/ 37
RTL vs High-Level Description

38
Comparison with Software Flow

39
https://www.eng.biu.ac.il/temanad/digital-integrated-circuits/ 40
https://www.eng.biu.ac.il/temanad/digital-integrated-circuits/ 41
https://www.eng.biu.ac.il/temanad/digital-integrated-circuits/ 42
https://www.eng.biu.ac.il/temanad/digital-integrated-circuits/ 43
https://www.eng.biu.ac.il/temanad/digital-integrated-circuits/ 44
https://www.eng.biu.ac.il/temanad/digital-integrated-circuits/ 45
Standard Cells based Design

https://www.eng.biu.ac.il/temanad/digital-integrated-circuits/ 46
Text Book
• Parallel programming for FPGAs - The HLS Book

47
EDA Tools
• Vivado/Vitis HLS – Proprietary toolchain for FPGA Synthesis (High
Level Synthesis)
• Open-Source HLS tools are also available

48