A Novel method of FPGA Implementation with High Performance

Design of FIR Filter Using Signed and Unsigned Detection of

Truncation Multiplier with Modified HSCG-SCS Unit Method of
SQRT based CSLA
Abstract:

A recent development method of FIR (Finite impulse response) filter design will have a
highly compactable with high performance and low power in all digital signal processing
application, such as audio processing, signal processing, software define radio and so on.
Now daysin our environment will have more signal noises, and fluctuation due to
technology development, here the Filter design is mainly configuring the priority to reduce
the signal noises and fluctuation in all type of gadgets. In this project, the design contains
Transpose form of high performance and high speed filter design using finite impulse
response (FIR) filter with technique of pipelined inherently and supported multiple constant
multiplication (MCM) in significant with saving power computation. In digital signal
processing, the multiplier is a highly required thing, the example of parallel multiplier
provide a high-speed and highly reliable method for multiplication, but this parallel
multiplier will take large area and also power consumption. In the FIR filter design,
multiplier and adders is the maximum priority will take to give the performance, but this
MCM multiplier and Adders it will take large area and maximum power consumption, and
this MCM multiplier will not detect the signed and unsigned input based operation in Signal
processing. So our Proposed approach of this work, will have replace the MCM multiplier to
Truncated Multiplier and using the technique of Truncated based both Signed and Unsigned
Operation with Proposed modified SQRT based Carry Select Adder (CSLA), and also replace
the normal adders in FIR Filter to Proposed modified HSCG-SCS Unit based SQRT method of
Carry Select Adder (CSLA). Normally the truncated will designed on full adder, based upon
this modification of HSCG-SCS Unit of SQRT based CSLA will perform high speed operation in
carry addition process, it will take less area and power consumption compared to normal
full adders, so this overall process of FIR filter design with truncated concept will take high
performance and better results. In the proposed system of FIR Filter design results to be
analysis with signed and unsigned Truncation using proposed modified SQRT-CSLA is better
than the regular FIR Filter design, FIR filter for Truncation multiplier with BEC based Adders,
FIR filter for Truncation multiplier with RCA, and FIR filter for Truncation multiplier with
Common Boolean logic based RCA, and finally implemented this design onVHDL with help of
Xilinx FPGA-S6LX9 and shown the performance of proposed design in terms of delay, area,
and power.

Index Terms – HSCG (Half Sum Carry Generation), SCS (Sum Carry Selection).
Introduction:

In the Finite Impulse response(FIR) is widely used in several digital signal processing
application, will have highly compactable with high performance and low power in gadgets
application, such as audio and video signal processing, software define radio,
telecommunication and so on. In this FIR filter is very often and need to support in digital
signal processing to high sampling rate, impulse response based filtering order and cut-off
frequency. In this FIR filter design, will have number of adders, multipliers and delayed
element required to response filter output. An FIR filter it not required a feedback based
inputs, which means, this filters is not computed any rounding errors in summing and
multiplication. An FIR filter is inherently stable to produce output values and it can be no
maximum value impulse response Nth order times, it can easily design and also easily
configure sequence of linear phase coefficient, it will also applicable to detect the phase
sensitive applications such as crossover filter design, mastering, seismology and data
communications. In this filter to meet the coefficient specification in certain things, which
can be suitable with time domain and frequency domain. The main disadvantages of FIR
filter design are more power consumption and large area size is required for multipliers,
adders and delayed element in number of Nth order based TAP. In the High performance FIR
Filter architecture will have MCM multiplication and normal adders will perform inherently
pipelined and also produced the results on significant way with save computation results. In
the FIR filter design will take large area and also take the stringent order to meet frequency
range with high performance. The main priority of this FIR filter design is Multiplier, adders
and delayed elements, the architecture of Fig.1 will have to used MCM (Multiplier constant
Multiplication) and Normal adders in this architecture design, it will take more area and
more power consumption, and also low performance to detect sign and unsigned operation
of multiplication and addition with carry operation.

X(n) 8

MCM MCM MCM MCM MCM

H(0) H (1) H (2) H (3) H (n)

16 16 16 16 16
Y(n)
D D D D
16
16 BIT ADDER 16 BIT ADDER 16 BIT ADDER 16 BIT ADDER

Figure 1:: FIR Filter Design with MCM and 16 bit Adder

In this architecture of Fig.1, it notified the FIR Filter will contain number of TAP (multiplier,
delay, adder), the area and power of this FIR filter will take this multiplier and adder only. In
the normal or MCM multiplier will provided the 16bit output for 8bit input, these output
isprovided to adder, So the adder design it will take 16bit addition. Here X(n) is the input
and Y(n) is the output of this filter design, H(0), H(1), H(2) ... H(n) is the coefficient of this
filter design, this coefficient will take from MATLAB with the help of FDA (Filter design
analysis) Tool, and also possible to fix the operations such as low pass filter design, band
pass filter design, high pass filter design, band stop filter design, and also fix the operation
range of cut off frequency, sampling frequency and so on.
A6B1

A6B0
A7B0
FA
A5B1

A6B2 A5B2
A7B1
FA FA
A4B2

A6B3 A5B3 A4B3

FA FA FA
A7B2 A3B3

A6B4 A5B4 A4B4 A3B4

A7B3
FA FA FA FA
A2B4

A6B5 A5B5 A4B5 A3B5 A2B5

FA FA FA FA FA
A7B4 A1B5

A6B6 A5B6 A4B6 A3B6 A2B6 A1B6

FA FA FA FA FA FA
A7B5 A0B6

A6B7 A5B7 A4B7 A3B7 A2B7 A1B7 A0B7

FA FA FA FA FA FA FA
A7B6

A7B7 FA FA FA FA FA FA FA 0

P15 P14 P13 P12 P11 P10 P9 P8

Figure 2: Truncated Multiplier Architecture using Normal Full Adders

In the architecture of Fig.2, the multiplier and adders will have designed for Truncated
Multiplier. In this method of truncated architecture is fully designed based on full adders,
here carry operation is followed as per the same operation of sum, based upon this
architecture it will take more critical path delay, propagation delay, and its perform slowest
operation of arithmetic functions. A goal of this truncated multiplier is to reduce the large
area in the internal and external architecture using rounded based technique, which
computed the truncation multiplier will have summing the two n-bit partial products, this
operation of two n-bits, the MSB of most significant rows and columns with truncated,
deletedand rounding to correction in variable method. A normal multiplier of n x n bit
computes and get the weighted sum of output of 2n bits. A multiplier in signal processing
the output represented the MSB part of n bits is useful, because it's signed oriented
outputs, example of this design such as digital signal based application.

A truncated multiplier is a hardware efficient multiplier, it will useful to increases the

tradeoff accuracy and reduced the hardware cost, since this truncated multiplier will help to
produce the output of n-bits form n x n bits of multiplication, it will take less significant, and
some of the partial products are removed and also replace using the technique of deletion,
reduction and truncation. In the partial products of this multiplier more number of columns
are eliminated regarding the area and power consumption, in case the delay also decreases
with compare to the normal operation of 2n outputs of n x n multiplier, but some
drawbacks will have on this truncated multiplication, because this multiplier is not
concentrated on carry operation, such as carry addition and carry skip operation, here used
number of full adders for addition, but not implemented the simple and efficient gate level
implementation with carry operation to significantly reduced the area, power and delay.

Research Objective:

Since a method of FIR Filter design will have highly compactable with high performance and
low power design in digital signal processing application, such as audio processing, signal
processing, software define radio and so on. The drawback of FIR filter design is large area
and more power consumption, because it uses impulse response of Nth order based circuit,
its contain multiplier, adder and delayed element, here the proposed thing is modified this
adders, multipliers using HSCG-SCS Unit based SQRT method of Carry Select adder with the
technique of truncated and partial product reduction method. This proposed work to be
analyze to multiple of adder with this Truncated FIR filter, finally choose, the best proposed
truncated adder, with low area and less power consumption, the list of adder is provided
below,

 Common Boolean Logic based Carry Select Adder

 Conventional RCA Based Carry Select Adder
 Conventional RCA with BEC Based Carry Select Adder
 SQRT Based Carry Select Adder

Using this adder, to be implemented in Modified architecture of Truncated multiplier, and

this modified truncated multiplier replaced to normal adders and multiplier in FIR filter,
then finally compare this all adder design, and shown the performance of which one adder
and multiplier is best in high performance, low power consumption, and finally
implemented this design on VHDL with help of Xilinx FPGA-S6LX9 and shown the
performance of proposed design in terms of delay, area, and power.
Research Methodology:

Module-1: Modified Signed and Unsigned Truncation Multiplier with Modified HSCG-SCS
Unit Method of SQRT based Carry Select Adder (Proposed Module)

In this proposed system of Digital FIR Filter architecture is modified with truncation
multiplier and SQRT CSLA architecture is shown in Fig.3. In this architecture the Multipliers is
modified with both signed and Unsigned operation of Truncated multiplier with Modified
SQRT based Carry Select adder and also the FIR Filters adders will have modified with SQRT
based Carry Select adder. In this proposed system of impulse response will contain a Nth
order of 8-Tap it will use on this FIR Filter design, here single Tap contains a single delay,
single adder and single multiplier, it contain to increase FIR Filter efficiency, the output
signals in sine wave with noise form, the Tap will reduce the high frequency noise with help
of cut-off frequency and sampling frequency. This cut-off frequency will decide to taken
response from the coefficient of H (0), H (1), H (2).... H (n).

Sign 8
X(n)
Detect
Truncated Truncated Truncated Truncated
Truncated
h(0) h(1) h(2) h(3) h(n)
T T T T T

8 8 8 8 8

Sign Y(n)
D D D D
8 Set
8 BIT CSLA 8 BIT CSLA 8 BIT CSLA 8 BIT CSLA

Figure 3: Proposed FIR Filter Design with Truncated and CSLA

Proposed Modified SQRT CSLA – HSCG and SCS based Adder Design:

A B C D

HSCG UNIT

n
SCS UNIT n

MUX MUX
CIN CIN
n
COUT SUM

Figure 4: Proposed Architecture of SQRT CSLA-HSCG(Half Sum carry Generation) and SCS(Sum carry Selection) based Adder
Design
In Fig.4 Shown the architecture of SQRT CSLA design of HSCG (Half-Sum Carry Generation)
and SCS (Sum carry Selection) based adder design, will help to process N number of
addition, using XOR, AND, OR Gate’s. These design will reduction of number of gate’s will
have compared to Ripple carry addition, and Existing SQRT CSLA Design. Here HSG will
provide the three outputs, such as operation of XOR, AND, OR Gates, the input CIN will
select the Sum and Carry using Multiplexer. Here CIN=0 the multiplexer will select Sum of
XOR outputs, and Carry of AND outputs, if CIN=1 the multiplexer will select Sum of Inverted
XOR outputs, and Carry of OR Gate outputs.
Table 1: Truth table for Proposed SQRT CSLA - HSCG - SCS UNIT

CIN A B XOR ~XOR OR AND SUM CARRY

0 0 0 0 1 0 0 0 0

0 0 1 1 0 1 0 1 0

0 1 0 1 0 1 0 1 0

0 1 1 0 1 1 1 0 1

1 0 0 0 1 0 0 1 0

1 0 1 1 0 1 0 0 1

1 1 0 1 0 1 0 0 1

1 1 1 0 1 1 1 1 1

Table 1, will have shown input and output values of SQRT CSLA using HSCG – SCG unit adder
design. Here the Multiplier selection will have happened from input of CIN, If CIN = 0, the
SUM Operation will get the input from XOR Gate, and Carry operation will get the input
from AND Gate, Once the CIN will goes high, the Multiplexer will switch the inputs, the SUM
Operation will get the input from inverted XOR Gate, and Carry operation will get the input
from OR Gate, here sharing process will have happen based upon CIN Inputs. This
Corresponding architecture gate count will take only Four logic gates and two multiplexers.

In Fig.5 Shown the architecture of Truncation Multiplier using SQRT based Carry Select
Adder design, this architecture contain after the operations of Unnecessary, Partial Product,
Deleted and Rounding operation from the partial product multiplier of 8x8bits, after
truncated partial products output values only given as a input of this architecture, it will
separate group by group, ex, SQRT-CSLA 3-Bit Structure, SQRT-CSLA 2-Bit Structure, SQRT-
CSLA 1-Bit Structure, this design will make this kind of outputs, P8, P9, P10, P11, P12, P13,
P14, P15 this output is similarly based upon the MSB bits of normal multipliers.
Proposed Block Diagram for Truncation Multiplier using Modified SQRT based CSLA with
HSCG and SCS based Adder Design:
A0B7 A0B6 A1B6 A1B5 A2B4 A2B3 A3B3 A3B4 A4B3 A4B2 A5B1 A5B2 A6B0 A6B1

HSCG UNIT HSCG UNIT HSCG UNIT

n n n
SCS UNIT n SCS UNIT n SCS UNIT n
A7B0
MUX MUX MUX MUX MUX MUX
CIN CIN CIN CIN CIN CIN
n n n
COUT SUM COUT SUM COUT SUM

A1B7 A2B6 A3B5 A4B4 A5B3 A6B2

HSCG UNIT HSCG UNIT HSCG UNIT

n n n
SCS UNIT n SCS UNIT n SCS UNIT n

MUX MUX MUX MUX MUX MUX A7B1

CIN CIN CIN CIN CIN CIN
n n n
COUT SUM COUT SUM COUT SUM

A2B7 A5B6 A4B5 A5B4 A6B3

P8

HSCG UNIT HSCG UNIT

n n
SCS UNIT n SCS UNIT n

MUX MUX MUX MUX A7B2

CIN CIN CIN CIN
n n
COUT SUM COUT SUM

A3B7 A6B6 A5B5 A6B4

P9

HSCG UNIT HSCG UNIT

n n
SCS UNIT n SCS UNIT n

MUX MUX MUX MUX A7B3

CIN CIN CIN CIN
n n
COUT SUM COUT SUM
A6B7 A5B6 A6B5
P10

HSCG UNIT HSCG UNIT

n n
SCS UNIT n SCS UNIT n

MUX MUX MUX MUX A7B4

CIN CIN CIN CIN
n n
COUT SUM COUT SUM
A5B7 A6B6
P11

HSCG UNIT

n
SCS UNIT n

MUX MUX A7B5

CIN CIN
n
COUT SUM
A6B7 P12

HSCG UNIT

n
SCS UNIT n

MUX MUX A7B6

CIN CIN
n
COUT SUM
P13

HSCG UNIT

n
SCS UNIT n

MUX MUX A7B7

CIN CIN
n
COUT SUM

P15 P14

Figure 5: Truncation Multiplier using Modified SQRT based CSLA with HSCG and SCS based Adder Design
Module-2: Modified Truncation Multiplier with Area and Delay Efficient SQRT Based CSLA

In this project, the design contains Transpose form of high performance and high speed
filter design using finite impulse response (FIR) filter with technique of pipelined inherently
and supported multiple constant multiplication (MCM) in significant with saving power
computation. In digital signal processing, the multiplier is a highly required thing, the
example of parallel multiplier provide a high-speed and highly reliable method for
multiplication, but this parallel multiplier will take large area and also power consumption.
In the FIR filter design, multiplier and adders is the maximum priority will take to give the
performance, but this MCM multiplier and Adders it will take large area and maximum
power consumption, so in this proposed work, replaced the MCM multiplier to Truncated
multiplier with design oflow power and area efficient SQRT based carry select adder with
modification to replaced parallel RCA architecture to SQRT CSLA based architecture and also
replaced the Adders in the FIR Filter design to low power and area efficient SQRT based
carry select adders. Normally the truncated will designed on full adder, based upon this
modification of SQRT CSLAbased carry select adder it will perform high speed operation in
carry addition process, it will take less area and power consumption compared to normal
full adders, so the overall process of FIR filter design with truncated will take high
performance and better results. In the proposed system of FIR Filter design results to be
analysis with Truncated conventional carry select adder is better than the regular FIR Filter
design, and also shown the performance of proposed design in terms of delay, area, and
power.

SQRT Based CSLA Design:

A B C D

HSG UNIT

CG0

CG0
n n
CIN
CG0
n-1 n

FSG UNIT
n
Gate level design of SQRT Based CSLA Design single bit adder:

A
B

CG1
CARRY

CS UNIT
HSG CG0

SUM
CIN

FSG

Truth table for SQRT Based CSLA Design:

CIN A B HSG HSG CG0 CG1 CS FSG

CARRY SUM

0 0 0 0 0 0 0 0 0

0 0 1 0 1 0 1 0 1

0 1 0 0 1 0 1 0 1

0 1 1 1 0 1 1 1 0

1 0 0 0 0 0 0 0 1

1 0 1 0 1 0 1 1 0

1 1 0 0 1 0 1 1 0

1 1 1 1 0 1 1 1 1
Proposed Block Diagram for Truncation Multiplier using SQRT based CSLA:

A0B7 A0B6 A1B6 A1B5 A2B4 A2B3 A3B3 A3B4 A4B3 A4B2 A5B1 A5B2 A6B0 A6B1

HSG UNIT HSG UNIT HSG UNIT

CG0 CG0 CG0

CG0 CG0 CG0

n n n n n n
CIN COUT CIN COUT CIN A7B0
CG0 CG0 CG0
n-1 n n-1 n n-1 n

FSG UNIT FSG UNIT FSG UNIT

n A1B7 A2B6 n A3B5 A4B4 A5B3 n A6B2

HSG UNIT HSG UNIT HSG UNIT

CG0 CG0 CG0

CG0 CG0 CG0

n n n n n n
COUT CIN COUT CIN COUT CIN A7B1
CS UNIT CS UNIT CS UNIT
n-1 n n-1 n n-1 n

FSG UNIT FSG UNIT FSG UNIT

n A2B7 n A5B6 A4B5 A5B4 n A6B3
P8
HSG UNIT HSG UNIT

CG0 CG0

CG0 CG0
n n n n
COUT CIN COUT CIN A7B2
CS UNIT CS UNIT
n-1 n n-1 n
P9
FSG UNIT FSG UNIT
A3B7 n A6B6 A5B5 n A6B4

HSG UNIT HSG UNIT

CG0 CG0

CG0 CG0
n n n n
COUT CIN COUT CIN A7B3
CS UNIT CS UNIT
n-1 n n-1 n
P10
FSG UNIT FSG UNIT
n A6B7 A5B6 n A6B5

HSG UNIT HSG UNIT

CG0 CG0

CG0 CG0
n n n n
COUT CIN COUT CIN A7B4
CS UNIT CS UNIT
n-1 n n-1 n

FSG UNIT FSG UNIT

n A5B7 A6B6 n
P11
HSG UNIT

CG0

CG0
n n
COUT CIN A7B5
CS UNIT
n-1 n
P12
FSG UNIT
A6B7 n

HSG UNIT

CG0

CG0
n n
COUT CIN A7B6
CS UNIT
n-1 n
P13
FSG UNIT
n

HSG UNIT

CG0

CG0
n n
COUT CIN A7B7
CS UNIT
P15 n-1 n

FSG UNIT
n

P14

Figure 6:Truncation Multiplier using SQRT Based CSLA

Module-3: Modified Truncation Multiplier with Conventional RCA and BEC based Carry
Select Adder

In this project, the design contains Transpose form of high performance and high speed
filter design using finite impulse response (FIR) filter with technique of pipelined inherently
and supported multiple constant multiplication (MCM) in significant with saving power
computation. In digital signal processing, the multiplier is a highly required thing, the
example of parallel multiplier provide a high-speed and highly reliable method for
multiplication, but this parallel multiplier will take large area and also power consumption.
In the FIR filter design, multiplier and adders is the maximum priority will take to give the
performance, but this MCM multiplier and Adders it will take large area and maximum
power consumption, so in this proposed work, replaced the MCM multiplier to Truncated
multiplier with design of conventional RCA based carry select adder with modification
replaced parallel RCA architecture to BEC based architecture and also replaced the Adders in
the FIR Filter design to Conventional RCA based Carry select adders. Normally the truncated
will designed on full adder, based upon this modification of BEC based conventional carry
select adder will perform high speed operation in carry addition process, it will take less
area and power consumption compared to normal full adders, so the overall process of FIR
filter design with truncated will take high performance and better results. In the proposed
system of FIR Filter design results to be analysis with Truncated conventional carry select
adder is better than the regular FIR Filter design, and also shown the performance of
proposed design in terms of delay, area, and power.

RCA and BEC Based CSLA Design:

A B C D

1:0 RCA 0

1:0 BEC 1

MUX

CARRY
SUM
Gate level design of RCA and BEC Based CSLA Single bit adder:

A B

RCA BEC

CIN

SUM CARRY

Truth table for SQRT Based CSLA Design:

RCA BEC A B RCA RCA BEC BEC CARRY SUM

CIN CIN CARRY SUM CARRY SUM

0 1 0 0 0 0 0 1 0 0

0 1 0 1 0 1 1 0 0 1

0 1 1 0 0 1 1 0 0 1

0 1 1 1 1 0 1 1 1 0

0 1 0 0 0 0 0 1 0 1

0 1 0 1 0 1 1 0 1 0

0 1 1 0 0 1 1 0 1 0

0 1 1 1 1 0 1 1 1 1
Truncation Multiplier Architecture using Conventional RCA and BEC based CSLA:
A5B1
A4B2 A5B2 A6B1
A0B7 A0B6 A1B6 A1B5 A2B4 A2B3 A3B3 A7B0
A3B4 A4B3 A6B0

1:0 RCA 0 RCA - 2 BIT 0 RCA - 3 BIT

0
1:0 BEC 1 BEC - 2 BIT 1 BEC - 3 BIT
1

MUX MUX MUX

A1B7 A2B6 A3B5 A4B4 A5B3 A6B2 A7B1

1:0 RCA 0 RCA - 2 BIT 0 RCA - 3 BIT 0

1:0 BEC 1 BEC - 2 BIT 1 BEC - 3 BIT
1

MUX MUX MUX

A6B3
A2B7 A5B6 A4B5 A5B4 A7B2
P8
RCA - 3 BIT 0 RCA - 3 BIT 0
BEC - 3 BIT 1 BEC - 3 BIT
1

MUX MUX
P9
A3B7 A6B6 A5B5 A6B4 A7B3
RCA - 2 BIT 0 RCA - 3 BIT 0
BEC - 2 BIT 1 BEC - 3 BIT
1

MUX MUX
P10
A6B7 A5B6 A6B5 A7B4
RCA - 1 BIT 0 RCA - 3 BIT 0
BEC - 1 BIT 1 BEC - 3 BIT
1

MUX MUX

P11 A5B7 A6B6 A7B5

RCA - 3 BIT 0
BEC - 3 BIT
1

MUX
P12
A6B7 A7B6
RCA - 2 BIT 0
BEC - 2 BIT
1

MUX
P13
A7B7

RCA - 1 BIT 0
BEC - 1 BIT
1

MUX

P15 P14
Module-4: Modified Truncation Multiplier with Conventional RCA Based Carry Select
Adder

In this project, the design contains Transpose form of high performance and high speed
filter design using finite impulse response (FIR) filter with technique of pipelined inherently
and supported multiple constant multiplication (MCM) in significant with saving power
computation. In digital signal processing, the multiplier is a highly required thing, the
example of parallel multiplier provide a high-speed and highly reliable method for
multiplication, but this parallel multiplier will take large area and also power consumption.
In the FIR filter design, multiplier is the maximum priority will take to give the performance,
but this MCM multiplier and Adders it will take large area and maximum power
consumption, so in this proposed work, replaced the MCM multiplier to Truncated
multiplier with design of conventional RCA based carry select adder and also replaced the
Adders in the FIR Filter design to Conventional RCA Carry select adders. Normally the
truncated will designed on full adder, based upon this modification conventional carry select
adder will perform high speed operation in carry addition process, it will take less area and
power consumption compared to normal full adders, so the overall process of FIR filter
design with truncated will take high performance and better results. In the proposed system
of FIR Filter design results to be analysis with Truncated conventional carry select adder is
better than the regular FIR Filter design, and also shown the performance of proposed
design in terms of delay, area, and power.

RCA Based CSLA Design:

A B C D

1:0 RCA 0

1:0 RCA 1

MUX

CARRY
SUM
Gate level Design of RCA Based CSLA Design:

A B

0 1

RCA RCA

CIN

SUM CARRY

Truth table for RCA Based CSLA Design:

CIN RCA RCA A B RCA RCA RCA RCA CARRY SUM

CIN CIN CARRY- SUM- CARRY- SUM-1

0 0 1

0 0 1 0 0 0 0 0 1 0 0

0 0 1 0 1 0 1 1 0 0 1

0 0 1 1 0 0 1 1 0 0 1

0 0 1 1 1 1 0 1 1 1 0

0 0 1 0 0 0 0 0 1 0 0

0 0 1 0 1 0 1 1 0 0 1

0 0 1 1 0 0 1 1 0 0 1

1 0 1 1 1 1 0 1 1 1 1

1 0 1 0 0 0 0 0 1 0 1

1 0 1 0 1 0 1 1 0 1 0

1 0 1 1 0 0 1 1 0 1 0
 1 0 1 1 1 1 0 1 1 1 1

1 0 1 0 0 0 0 0 1 0 1

1 0 1 0 1 0 1 1 0 1 0

1 0 1 1 0 0 1 1 0 1 0

1 0 1 1 1 1 0 1 1 1 1

Truncation Multiplier Architecture using Conventional RCA based CSLA:

 A5B1
A4B2 A5B2 A6B1
A0B7 A0B6 A1B6 A1B5 A2B4 A2B3 A3B3 A7B0
A3B4 A4B3 A6B0

1:0 RCA 0 RCA - 2 BIT 0 RCA - 3 BIT

0
1:0 RCA 1 RCA - 2 BIT 1 RCA - 3 BIT
1

MUX MUX MUX

A1B7 A2B6 A3B5 A4B4 A5B3 A6B2 A7B1

1:0 RCA 0 RCA - 2 BIT 0 RCA - 3 BIT 0

1:0 RCA 1 RCA - 2 BIT 1 RCA - 3 BIT
1

MUX MUX MUX

A6B3
A2B7 A5B6 A4B5 A5B4 A7B2
P8
RCA - 3 BIT 0 RCA - 3 BIT 0
RCA - 3 BIT 1 RCA - 3 BIT
1

MUX MUX
P9
A3B7 A6B6 A5B5 A6B4 A7B3
RCA - 2 BIT 0 RCA - 3 BIT 0
RCA - 2 BIT 1 RCA - 3 BIT
1

MUX MUX
P10
A6B7 A5B6 A6B5 A7B4
RCA - 1 BIT 0 RCA - 3 BIT 0
RCA - 1 BIT 1 RCA - 3 BIT
1

MUX MUX

P11 A5B7 A6B6 A7B5

RCA - 3 BIT 0
RCA - 3 BIT
1

MUX
P12
A6B7 A7B6
RCA - 2 BIT 0
RCA - 2 BIT
1

MUX
P13
A7B7

RCA - 1 BIT 0
RCA - 1 BIT
1

MUX

P15 P14
Module-5: Modified Truncation Multiplier with Common Boolean logic based Carry Select
Adder

In this project, the design contains Transpose form of high performance and high speed
filter design using finite impulse response (FIR) filter with technique of pipelined inherently
and supported multiple constant multiplication (MCM) in significant with saving power
computation. In digital signal processing, the multiplier is a highly required thing, the
example of parallel multiplier provide a high-speed and highly reliable method for
multiplication, but this parallel multiplier will take large area and also power consumption.
In the FIR filter design, multiplier and adders is the maximum priority will take to give the
performance, but this MCM multiplier and Adders it will take large area and maximum
power consumption, so in this proposed work, replaced the MCM multiplier to Truncated
multiplier with design of Common Boolean logic based carry select adder and also replaced
the Adders in the FIR Filter design to Common Boolean logic based Carry select adders.
Normally the truncated will designed on full adder, based upon this modification of
Common Boolean logic based carry select adder will perform high speed operation in carry
addition process, it will take less area and power consumption compared to normal full
adders, so the overall process of FIR filter design with truncated will take high performance
and better results. In the proposed system of FIR Filter design results to be analysis with
Truncated Common Boolean logic based carry select adder is better than the regular FIR
Filter design, and also shown the performance of proposed design in terms of delay, area,
and power.

CBL Based CSLA Design:

A B C D

1:0 RCA 0
1:0 CBL 1

MUX

CARRY
SUM
Gate level Design of CBL Based CSLA Design:

A B

RCA CBL

CIN

SUM CARRY

Truth table for SQRT Based CSLA Design:

RCA CBL A B RCA RCA CBL CBL CARRY SUM

CIN CIN CARRY SUM CARRY SUM

0 1 0 0 0 0 0 1 0 0

0 1 0 1 0 1 1 0 0 1

0 1 1 0 0 1 1 0 0 1

0 1 1 1 1 0 1 1 1 0

0 1 0 0 0 0 0 1 0 1

0 1 0 1 0 1 1 0 1 0

0 1 1 0 0 1 1 0 1 0

0 1 1 1 1 0 1 1 1 1
Truncation Multiplier Architecture using Common Boolean logic based CSLA:

A5B1
A4B2 A5B2 A6B1
A0B7 A0B6 A1B6 A1B5 A2B4 A2B3 A3B3 A7B0
A3B4 A4B3 A6B0

1:0 RCA 0 RCA - 2 BIT 0 RCA - 3 BIT

0
1:0 CBL 1 CBL- 2 BIT 1 CBL- 3 BIT
1

MUX MUX MUX

A1B7 A2B6 A3B5 A4B4 A5B3 A6B2 A7B1

1:0 RCA 0 RCA - 2 BIT 0 RCA - 3 BIT 0

1:0 CBL 1 CBL- 2 BIT 1 CBL- 3 BIT
1

MUX MUX MUX

A6B3
A2B7 A5B6 A4B5 A5B4 A7B2
P8
RCA - 3 BIT 0 RCA - 3 BIT 0
CBL- 3 BIT 1 CBL- 3 BIT
1

MUX MUX
P9
A3B7 A6B6 A5B5 A6B4 A7B3
RCA - 2 BIT 0 RCA - 3 BIT 0
CBL- 2 BIT 1 CBL- 3 BIT
1

MUX MUX
P10
A6B7 A5B6 A6B5 A7B4
RCA - 1 BIT 0 RCA - 3 BIT 0
CBL- 1 BIT 1 CBL- 3 BIT
1

MUX MUX

P11 A5B7 A6B6 A7B5

RCA - 3 BIT 0
CBL- 3 BIT
1

MUX
P12
A6B7 A7B6
RCA - 2 BIT 0
CBL- 2 BIT
1

MUX
P13
A7B7

RCA - 1 BIT 0
CBL- 1 BIT
1

MUX

P15 P14
Problem Statement:

Since a recent technology of digital signal processing application is a most high priority in
today technology such as 3G technology, LTE, Tele communication, audio and video signal
processing, so on. In this DSP application, the filtering part is the main priority to reduce the
signal noise, fluctuation in all type of gadgets. Here, the filtering part will have differentiated
in two types, such as digital and analog filtering, the major category of digital filtering is FIR.
An FIR filter it not required a feedback based inputs, which means, this filters is not
computed any rounding errors in summing and multiplication. An FIR filter is inherently
stable to produce output values and it can be no maximum value impulse response Nth
order times, it can easily design and also easily configure sequence of linear phase
coefficient, it will also applicable to detect the phase sensitive applications such as crossover
filter design, mastering, seismology and data communications. In this filter to meet the
coefficient specification in certain things, which can be suitable with time domain and
frequency domain. The main disadvantages of FIR filter design are more power consumption
and large area size is required for multipliers, adders and delayed element in number of Nth
order based TAP.

In the High performance FIR Filter architecture will have MCM multiplication and normal
adders it will perform inherently pipelined and also produced the results on significant way
with save computation results. This MCM multiplier will not identified the Signed and
Unsigned operation of inputs, and not concentrate on Carry operation inside of Partial
Product Addition. In the FIR filter design will take large area and also take the stringent
order to meet frequency range with high performance.

Problem Outcomes:

The Possible outcomes of the Study as follow,

 Truncation Multiplier to produce the output in n size from n x n bit inputs.

 Reduced the 2n size of FIR Filter adders to n size.
 Reduced the Hardware complexity in FIR Filter design.
 Increase the High Performance, and impulse response in Nth order
 Reduced the Power Consumption
 Impulse response to be fixed and also increases the accuracy in Cut-off frequency
with help of filter coefficient.
 Rectified the problem of signed and Unsigned configuration in Multiplier, the
truncated multiplier to be designed with Both signed and unsigned configuration.
Comparison for all the single bit adders:

Adders No. of No. of LUT Occupied IOB Delay(ns)

Logic Multiplexer Slices
Gates

RCA-RCA 10 1 1 1 5 6.11

RCA-CBL 9 3 1 1 5 6.11

RCA-BEC 7 1 1 1 5 6.11

SQRT-CSLA- 7 0 1 1 5 6.11
HSG-CS-FSG

Proposed 4 2 1 1 5 6.11
SQRT-HSCG

No. of Logic Gates

12
10
8
6
4
2
0 No. of Logic Gates
Literature Survey:

 B. Ramkumar, Harish M Kittur, 2011 IEEE, discussed about the fast arithmetic operations
using to design adders. In Carry select adder is a one of the design of fast arithmetic
functions. In the Architecture of Carry select adder to significantly have large area to be
reduced, and also power consumption. The proposed architecture of SQRT based CSLA will
modified 8-, 16-, 32- and 64bit square root Carry Select adder architecture with compare to
the regular Carry Select adder, it will show high performance in area, power and delay, this
architecture of SQRT BEC based CSLA will design it will reduce the area, power and delay.

 Suresh R.Rijal, Ms.Sharda, G. Mungale, 2013 discussed about the Multipliers is mostly
required in DSP (digital signal processing) application. In the design of parallel multipliers to
provide an efficient output high speed multiplication, but it will take large area and power
consumption. In the recent technology of digital signal processing application, a partial
product is rounded and also avoid the growth in the size of multiplier. In this proposed work
of this paper, is reduced the area of partial product rounded truncated multiplier, and it
computes the two n-bit numbers to produce n-bit outputs regarding summing MSB bits with
variable correction methods. Its Significantly reduced the area and power consumption
instead of standard multiplier.

 Basant Kumar Mohanty, SujitKumarPatel, 2014 discussed about the operation of adder in
the signal processing application, the carry select adder is mostly involved with data
dependence and also to identify the arithmetic logic operation. In this Carry select adder will
have lot of methods. In this proposed architecture of this design consider will approach
different from of conventional approach, it will reduce and optimized logic units. The
proposed SQRT based carry select adder will design using HSG (Half Sum Generation), FSG
(Full Sum Generation), CG (Carry Generation), CS (Carry Selection) based design it will
provide the performance of less area, and less delay and also less bit widths.

 Basant Kumar Mohanty, Pramod Kumar Meher, 2015 discussed about the FIR Filter design in
Fixed and Reconfigurable method of application, this FIR filters are support inherently
pipelined multiplication, such as Multiplier constant multiplication (MCM) technique it will
save the hardware area size and power consumption. In this Proposed work of this paper
will realization oflow complexity in area of design and less energy per sample, and in this
design using coefficient from the h(x), to reduce the impulse noise, with Nth order structure.

 Balasubramanian, Nikos E. Mastorakis, Padmanabhan, 2009, is discussed about the work of

Full Adder Design with High Speed Gate level of design using gate with XNOR, AND, Inverter,
Multiplexer and complex gates, this work present a design of 32bit Carry ripple adder
implementation with compare the three process of voltage, temperature and power using
CMOS Technology of 65nm. Finally found the comparison of best delay reduction in
proposed work.
 V.Kamalakannan, Ravi.H.N, Shilpakala.V, 2013 is discussed about the work of Reversible gate
design of full adder in quantum computing and it has to possible design logic of extensive
application, they study about the technology aimed at implementing to improve the energy
efficiency in Quantum Computing, using TG-Gate, here the design will contain the full adder
design of TG-Gate will compare the all reversible gate design, hence proved this TG-gate will
produce the better results in area, delay and power consumption. Finally design a Carry skip
adder design using this TG Gate and shown the performance and better results compare to
the all reversible gate design.

 Ms. Anagha U P, Mr. Pramod P, 2015, is discussed and proved a new approach of Carry
Select adder design using SQRT method, this design will have new gate design of HSG (Haft
Sum Generation), FSG (Full Sum Generation), CS (Carry Select), CG (Carry Generation) based
technique. Logic optimization of SQRT CSLA providing a separate carry generator operation
in the final sum of ever operation, and this design will has taken less area and power
consumption.

 Yi-Sheng Lin, I-Chyn Wey, Chien-Chang Peng and Cheng-Chen Ho,2012 is discussed about
adder design of Carry Select adder with Common Boolean logic term. Using the logic gate
design of XOR gate with inverter, AND gate with inverter to design this operation. The mux
operation will decide the full adder output using the selection bit of first sum of addition.
The output of this architecture will design 32bit addition, moreover it will reduce the area
and also power consumption compare to the existing method.

 HimanshuThapliyal and A.P Vinod, 2007 is discussed about the design of online testable gate
in Reversible logic method. Using this Online Testable gate to improve the efficiency in
Reversible gate adders of 4x4 it produced the suitable online testability. The proposed
design of this method to design a Ripple carry adder, Carry skip adder and BCD adder with
Reversible logic design of Feynman gate design. Finally test this reversible logic design using
Feynman gate compared to the Online testable gate method, and hence proved the better
results in Area, unit delay, garbage outputs and power consumption.

 Athira Prasad, Robin Abraham, 2014 is discussed about the work of Multiplier is advance
technology of DSP (Digital Signal Processing Application), with High speed, low power and
layout with reduction in area, time and unit delay in the Design. In the recent multiplier of n
x n will produce the output in 2n bits, so it will take more area, of internal and external
design of architecture. In this proposed work of this paper, a new approach of Truncated
multiplier will design using the 3 type of method, such as rounding, deleting, and
unnecessary bits, this truncated multiplier will produce the n bit output from the n x n bits of
input. Finally shown the comparison of area, power and delay with better results.
 C.S.Manikandababu, R. Devarani, 2013 is discussed about the work of Truncated Multipliers
with precision improvements, this multiplier will reduce the significant parameters of area,
power and delay. The proposed method of this truncated precision multiplier will design
using number of full adders and half adders, the MSB part of the partial product will be used,
and LSB part of partial product will reduced using the three method of rounding, deleting
and truncating in the final part of addition and also provide the output on n bit from the
input of n x n bits. Finally shown the comparison of area, delay and power with better
results.

 Theo Drane, George A and Thomas Rose, 2013, is discussed about the project of Truncated
multiplier with faithfully rounded method, it is the modified method of normal truncated
method will better results, and also reduced the method of partial product with the
technique of rounded, deleted and truncated method. This design presents the 32bit
multiplier using Monte carlo simulation method and shown the better results compare to
the normal truncated operation with maintaining faithfully rounding with arbitrary array.

 KanchanaBhaaskaran V S,BhuvanaB P, 2016 is discussed about the Gate design of BKG with
design of reversible full adders. In the method of quantum dot cellular automation with
computation of logic gate in reversible method with shown the performance of area, delay
and power reduction compare to the all quantum gate operations. In in proposed work to
design a novel architecture full adder using to design with 4x4 BKG gate of reversible
method. Finally shown the comparison of better results in computation of area, delay and
power.

 PravinK. Dakhole,Sujata S. Chiwande, 2012 is discussed about the work of Fredkin

reversible gate design and TSG reversible gate design. In the design of 4bit Carry Skip adder
will design using the forward and backward method of 4x4 TSG gate with Fredkin gate and
shown the comparison of normal quantum computing technique of CMOS technology.
Finally shown the comparison of this 4bit carry skip adder design in the CMOS technology of
65nm with better results.
References:

 "Low-Power and Area-Efficient Carry Select Adder", B. Ramkumar and Harish M Kittur, IEEE
TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1063-8210/$26.00 ©
2011 IEEE.
 "Design and Implementation of 8X8 Truncated Multiplier on FPGA", Suresh R.Rijal (Asst.
Prof. KITS, Ramtek), Ms.Sharda G. Mungale (Asst. Prof. PCEA, Nagpur), International Journal
of Scientific and Research Publications, Volume 3, Issue 3, March 2013.
 "Area–Delay–Power Efficient Carry-Select Adder", Basant Kumar Mohanty, Senior Member,
IEEE, and Sujit Kumar Patel, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS
BRIEFS, VOL. 61, NO. 6, JUNE 2014.
 "A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications",
Basant Kumar Mohanty, Senior Member, IEEE, and Pramod Kumar Meher, Senior Member,
1063-8210 © 2015 IEEE.
 "High Speed Gate Level Synchronous Full Adder Designs", WSEAS TRANSACTIONS on
CIRCUITS and SYSTEMS, PADMANABHAN BALASUBRAMANIAN and NIKOS E. MASTORAKIS,
Oxford Road, Manchester M13 9PL, UNITED KINGDOM.
 "DESIGN OF ADDER / SUBTRACTOR CIRCUITS BASED ON REVERSIBLE GATES",
V.Kamalakannan, Shilpakala.V, Ravi.H.N, International Journal of Advanced Research in
Electrical, Electronics and Instrumentation Engineering, Vol. 2, Issue 8, August 2013.
 "Power and Area Efficient Carry Select Adder", 2015 IEEE Recent Advances in Intelligent
Computational Systems (RAICS) | 10-12 December 2015 | Trivandrum.
 "An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term", I-
Chyn Wey, Cheng-Chen Ho, Yi-Sheng Lin, and Chien-Chang Peng, Proceedings of the
International Multi Conference of Engineers and Computer Science 2012 Vol II.
 "Designing Efficient Online Testable Reversible Adders With New Reversible Gate",
HimanshuThapliyal and A.P Vinod School of Computer Engineering, Nanyang Technological
University, Singapore, 2007 IEEE.
 "Variable Truncated Multiplier with Low Power", AthiraPrasad , Robin Abraham,
International Journal Of Engineering And Computer Science ISSN:2319-7242.
 "Design and implementation of truncated multipliers for precision improvement", 2013
International Conference on Computer Communication and Informatics (ICCCI -2013), Jan.
04 – 06, 2013, Coimbatore, INDIA.
 "On The Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays", Theo
Drane, Thomas Rose and George A. Constantinides, 2013, IEEE TRANSACTIONS ON
COMPUTERS.
 "Design of Reversible Adders Using A Novel Reversible BKG Gate", Bhuvana B,
KanchanaBhaaskaran V S, 2016 Online International Conference on Green Engineering and
Technologies (IC-GET).
 "A Novel Design of Compact Reversible SG Gate and its Applications", Payal Garg, Sandeep
Saini, 2014 International Symposium on Communications and Information Technologies
(ISCIT).