Reg. No.

Question Paper Code : X 10311

B.E./B.Tech. DEGREE EXAMINATIONS, NOVEMBER/DECEMBER 2020
Third Semester
Computer Science and Engineering
CS 8351 – DIGITAL PRINCIPLES AND SYSTEM DESIGN
(Common to Electronics and Telecommunication Engineering/
Information Technology)
(Regulations 2017)

Time : Three Hours Maximum : 100 Marks

Answer ALL questions

PART – A (10×2=20 Marks)

1. Reduce AB + (AC) + AB’C (AB + C).

2. A bulb in a staircase has two switches, one switch being at the ground floor and
the other one at the first floor. The bulb can be turned ON and also can be turned
OFF by any one of the switches irrespective of the state of the other switch. Which
logic gate does the logic of switching of the bulb resembles ?

3. What is priority encoder ?

4. The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater
than the 2-bit input B. What is the number of combinations for which the output
is logic 1 ?

5. How do you eliminate the race around condition in a JK flip-flop ?

6. How many flip-flops are required to build a binary counter that counts from
0 to 1023 ?

7. What are Hazards ?

8. What is state table ?

9. What are the advantages of static RAM and dynamic RAM ?

10. What is PAL ?

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PART – B (5×13=65 Marks)

11. a) Given the Boolean function F = xyz + xyz + wxy + wxy + wxy.
i) Obtain the truth table of the function. (2)
ii) Draw the logic diagram using the original Boolean expression. (2)
iii) Simplify the function to a minimum number of literals using Boolean
algebra. (3)
iv) Obtain the truth table of the function from the simplified expression and
show that it is the same as the one in part.(a). (3)
v) Draw the logic diagram from the simplified expression and compare the
total number of gates with the diagram of part (b). (3)
(OR)
b)
Consider,
= xyz + wxy + (x + z + w) (x + z + w) + xyz + wxy
= xy + wx + x + z
Without using K-Map, show F1 can be simplified to F2 by algebraic
means. (7)
Implement F2 using NAND gates only. Assume all variables are available
in both true and complement form. (6)

1
aDesign
) a combinational circuit with three inputs, x, y and z and three outputs, A, B
and C. When the binary input is 0, 1, 2 or 3 the binary output is one greater
than the input. When the binary input is 4, 5, 6 or 7, the binary output is one
less than the input.
(OR)
Design a code converter that converts a decimal digit from 8 4 – 2 – 1 code to
b)
BCD.

1
aConsider
) the following circuit involving three D-type flip-flops used in a certain type
of counter configuration.
i) If at some instance prior to the occurrence of the clock edge, P, Q and R
have a value 0, 1 and 0 respectively, what shall be the value of PQR after
the clock edge ? (7)
ii) If all the flip-flops were reset to 0 at power on, what is the total number of
distinct outputs (states) represented by PQR generated by the counter ? (6)
(OR)
 -3- X 10311

b) A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED
to GREEN. In each cycle, GREEN is turned on for 70 seconds, YELLOW is
turned on for 5 seconds and the RED is turned on for 75 seconds. This traffic
light has to be implemented using a Finite State Machine (FSM). The only
input to this FSM is a clock of 5 second period. What is the minimum number
of flip-flops required to implement this FSM ? Explain in detail.

14. a) The state table of an asynchronous circuit with three SR latches is shown
below. Reduce the number of states in the state table using implication table.

(OR)

b) An asynchronous sequential circuit is described by the following excitation and

output functions

Y = x1 x2 + (x1 + x2)y

Z=y
i) Draw the logic diagram of the circuit. (3)
ii) Derive the transition table and output map. (3)
iii) Obtain a 2-state flow table. (3)
iv) Describe in words the behaviour of the circuit. (4)

15. a) A 12-bit Hamming code word containing 8 bits of data and 4 parity bits is read
from memory. What was the original 8-bit data word that was written into
memory if the 12-bit word read out is as follows ?

i) 000011101010

ii) 101110000110

iii) 101111110100

(OR)

b) List the PLA and PAL programming table for the BCD to excess-3 code
convert whose Boolean function are simplified as w = A + BC + BD, x = BC +
BD + BCD, y = CD + CD, z = D’.
 X 10311 -4-

PART – C (1×15=15 Marks)

16. a) Given the following Boolean function , F = xy’z + z’y’z + w’xy + wx’y + wxy
i) Draw a corresponding Karnaugh map of the function. (5)
ii) Give minterm and maxterm expressions. (5)
iii) Simplify the function and implement it by NAND gates only. (5)

(OR)
b) A sequential circuit has three flip-flops, A, B, C ; one input x and one output
y. The state diagram is shown below. The circuit is designed by treating the unused
states as don’t care conditions. The final circuit must be analyzed to ensure that
it is self-correcting (i.e., if the circuit enters in any of the unused states, after
finite number of clock cycles it comes to a used state). Use JK flip-flops for
the design.

–––––––––––––
 Reg. No. :

Question Paper Code : 40387

B.E./B.Tech. DEGREE EXAMINATIONS, NOVEMBER/DECEMBER 2021.

Third Semester

Computer Science and Engineering

CS 8351 –– DIGITAL PRINCIPLES AND SYSTEM DESIGN

(Common to Electronics and Telecommunication Engineering/

Information Technology)

(Regulations 2017)

Time : Three hours Maximum : 100 marks

Answer ALL questions.

PART A — (10  2 = 20 marks)

1. What are the basic digital logic gates?

2. Find the complement of the expression – x  y  zx  zx  y .

3. What is priority encoder?

4. List out the applications of multiplexer.

5. What is sequential circuit?

6. How many flip-flops are required to build a binary counter that counts from 0
to 1023?

7. Define hazard and when do hazard occur?

8. Define flow table in asynchronous sequential circuit.

9. List the major differences between PLA and PAL.

10. Differentiate volatile and non-volatile memory.

 PART B — (5  13 = 65 marks)

11. (a) Express the following numbers in decimal

(i) 10110.01012 (3)
(ii) 16.516 (3)
(iii) 26.248 (3)
(iv) FAFA.B16 (2)
(v) 1010.10102 . (2)

Or
(b) Using K map, minimize the expression
F  A,B,C,D   m1,3,4,6,8,9,11,13,15 d0,2,14.

12. (a) Design a full adder and realize using gates. Implement full adder with
two half adders and an OR gate.
Or
(b) (i) Implement the Boolean expression
F A,B,C  using
m0,2,5,6
4 : 1 multiplexer. (7)
(ii) Implement
F  A,B,C,D   using 8 : 1
m0,1,5,6,8,10,12,15
multiplexer. (6)

13. (a) Show that the characteristic equation for the complement output of a
JK flip-flop is Qt  1  J Q  KQ .

Or
(b) Design and implement a synchronous 4-bit up/down binary counter using
T flip-flops.

14. (a) An asynchronous sequential circuit is described by the following

excitation and output function,

Y  x1 x2   x1  x2  y

ZY.
(i) Draw the logic diagram of the circuit. (5)
(ii) Derive the transition table, flow table and output map. (5)
(iii) Describe the behavior of the circuit. (3)

Or
(b) Explain with neat diagram about the static hazard and the way to
eliminate it.

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15. (a) A 12-bit Hamming code word containing 8 bit of data and 4 parity bits is
read from memory. What was the original 8-bit data word that was
written into memory if the 12 bit word read out is as follows?

(i) 00001 110101 0 (4)

(ii) 10111 00001 10 (4)

(iii) 101111 110100 (5)

Or
(b) Tabulate the PLA programming table for the four Boolean functions
listed below. Minimize the numbers of product terms.
Ax, y,z 

m1,2,4,6 Bx, y,z

 m0,1,6,7 CX ,

y,z  m2, 6

Dx, y,z  m1,2,3, 5,7

PART C — (1  15 = 15 marks)

16. (a) Design an adder to perform arithmetic addition of two decimal digits in
BCD.

Or
(b) Design and write a HDL code for combinational circuits that’s a four bit
Binary code to four bit Gray code using Exclusive – OR gates.

————––––——

3 40387